1// Generated by opcode_generator.rb from /home/dima/wk/webkit/Source/JavaScriptCore/b3/air/AirOpcode.opcodes -- do not edit!
2#ifndef AirOpcodeGenerated_h
3#define AirOpcodeGenerated_h
4#include "AirInstInlines.h"
5#include "wtf/PrintStream.h"
6namespace WTF {
7using namespace JSC::B3::Air;
8void printInternal(PrintStream& out, Opcode opcode)
9{
10 switch (opcode) {
11 case Opcode::Nop:
12 out.print("Nop");
13 return;
14 case Opcode::Add32:
15 out.print("Add32");
16 return;
17 case Opcode::Add8:
18 out.print("Add8");
19 return;
20 case Opcode::Add16:
21 out.print("Add16");
22 return;
23 case Opcode::Add64:
24 out.print("Add64");
25 return;
26 case Opcode::AddDouble:
27 out.print("AddDouble");
28 return;
29 case Opcode::AddFloat:
30 out.print("AddFloat");
31 return;
32 case Opcode::Sub32:
33 out.print("Sub32");
34 return;
35 case Opcode::Sub64:
36 out.print("Sub64");
37 return;
38 case Opcode::SubDouble:
39 out.print("SubDouble");
40 return;
41 case Opcode::SubFloat:
42 out.print("SubFloat");
43 return;
44 case Opcode::Neg32:
45 out.print("Neg32");
46 return;
47 case Opcode::Neg64:
48 out.print("Neg64");
49 return;
50 case Opcode::NegateDouble:
51 out.print("NegateDouble");
52 return;
53 case Opcode::NegateFloat:
54 out.print("NegateFloat");
55 return;
56 case Opcode::Mul32:
57 out.print("Mul32");
58 return;
59 case Opcode::Mul64:
60 out.print("Mul64");
61 return;
62 case Opcode::MultiplyAdd32:
63 out.print("MultiplyAdd32");
64 return;
65 case Opcode::MultiplyAdd64:
66 out.print("MultiplyAdd64");
67 return;
68 case Opcode::MultiplySub32:
69 out.print("MultiplySub32");
70 return;
71 case Opcode::MultiplySub64:
72 out.print("MultiplySub64");
73 return;
74 case Opcode::MultiplyNeg32:
75 out.print("MultiplyNeg32");
76 return;
77 case Opcode::MultiplyNeg64:
78 out.print("MultiplyNeg64");
79 return;
80 case Opcode::MultiplySignExtend32:
81 out.print("MultiplySignExtend32");
82 return;
83 case Opcode::Div32:
84 out.print("Div32");
85 return;
86 case Opcode::UDiv32:
87 out.print("UDiv32");
88 return;
89 case Opcode::Div64:
90 out.print("Div64");
91 return;
92 case Opcode::UDiv64:
93 out.print("UDiv64");
94 return;
95 case Opcode::MulDouble:
96 out.print("MulDouble");
97 return;
98 case Opcode::MulFloat:
99 out.print("MulFloat");
100 return;
101 case Opcode::DivDouble:
102 out.print("DivDouble");
103 return;
104 case Opcode::DivFloat:
105 out.print("DivFloat");
106 return;
107 case Opcode::X86ConvertToDoubleWord32:
108 out.print("X86ConvertToDoubleWord32");
109 return;
110 case Opcode::X86ConvertToQuadWord64:
111 out.print("X86ConvertToQuadWord64");
112 return;
113 case Opcode::X86Div32:
114 out.print("X86Div32");
115 return;
116 case Opcode::X86UDiv32:
117 out.print("X86UDiv32");
118 return;
119 case Opcode::X86Div64:
120 out.print("X86Div64");
121 return;
122 case Opcode::X86UDiv64:
123 out.print("X86UDiv64");
124 return;
125 case Opcode::Lea32:
126 out.print("Lea32");
127 return;
128 case Opcode::Lea64:
129 out.print("Lea64");
130 return;
131 case Opcode::And32:
132 out.print("And32");
133 return;
134 case Opcode::And64:
135 out.print("And64");
136 return;
137 case Opcode::AndDouble:
138 out.print("AndDouble");
139 return;
140 case Opcode::AndFloat:
141 out.print("AndFloat");
142 return;
143 case Opcode::OrDouble:
144 out.print("OrDouble");
145 return;
146 case Opcode::OrFloat:
147 out.print("OrFloat");
148 return;
149 case Opcode::XorDouble:
150 out.print("XorDouble");
151 return;
152 case Opcode::XorFloat:
153 out.print("XorFloat");
154 return;
155 case Opcode::Lshift32:
156 out.print("Lshift32");
157 return;
158 case Opcode::Lshift64:
159 out.print("Lshift64");
160 return;
161 case Opcode::Rshift32:
162 out.print("Rshift32");
163 return;
164 case Opcode::Rshift64:
165 out.print("Rshift64");
166 return;
167 case Opcode::Urshift32:
168 out.print("Urshift32");
169 return;
170 case Opcode::Urshift64:
171 out.print("Urshift64");
172 return;
173 case Opcode::RotateRight32:
174 out.print("RotateRight32");
175 return;
176 case Opcode::RotateRight64:
177 out.print("RotateRight64");
178 return;
179 case Opcode::RotateLeft32:
180 out.print("RotateLeft32");
181 return;
182 case Opcode::RotateLeft64:
183 out.print("RotateLeft64");
184 return;
185 case Opcode::Or32:
186 out.print("Or32");
187 return;
188 case Opcode::Or64:
189 out.print("Or64");
190 return;
191 case Opcode::Xor32:
192 out.print("Xor32");
193 return;
194 case Opcode::Xor64:
195 out.print("Xor64");
196 return;
197 case Opcode::Not32:
198 out.print("Not32");
199 return;
200 case Opcode::Not64:
201 out.print("Not64");
202 return;
203 case Opcode::AbsDouble:
204 out.print("AbsDouble");
205 return;
206 case Opcode::AbsFloat:
207 out.print("AbsFloat");
208 return;
209 case Opcode::CeilDouble:
210 out.print("CeilDouble");
211 return;
212 case Opcode::CeilFloat:
213 out.print("CeilFloat");
214 return;
215 case Opcode::FloorDouble:
216 out.print("FloorDouble");
217 return;
218 case Opcode::FloorFloat:
219 out.print("FloorFloat");
220 return;
221 case Opcode::SqrtDouble:
222 out.print("SqrtDouble");
223 return;
224 case Opcode::SqrtFloat:
225 out.print("SqrtFloat");
226 return;
227 case Opcode::ConvertInt32ToDouble:
228 out.print("ConvertInt32ToDouble");
229 return;
230 case Opcode::ConvertInt64ToDouble:
231 out.print("ConvertInt64ToDouble");
232 return;
233 case Opcode::ConvertInt32ToFloat:
234 out.print("ConvertInt32ToFloat");
235 return;
236 case Opcode::ConvertInt64ToFloat:
237 out.print("ConvertInt64ToFloat");
238 return;
239 case Opcode::CountLeadingZeros32:
240 out.print("CountLeadingZeros32");
241 return;
242 case Opcode::CountLeadingZeros64:
243 out.print("CountLeadingZeros64");
244 return;
245 case Opcode::ConvertDoubleToFloat:
246 out.print("ConvertDoubleToFloat");
247 return;
248 case Opcode::ConvertFloatToDouble:
249 out.print("ConvertFloatToDouble");
250 return;
251 case Opcode::Move:
252 out.print("Move");
253 return;
254 case Opcode::Swap32:
255 out.print("Swap32");
256 return;
257 case Opcode::Swap64:
258 out.print("Swap64");
259 return;
260 case Opcode::Move32:
261 out.print("Move32");
262 return;
263 case Opcode::StoreZero32:
264 out.print("StoreZero32");
265 return;
266 case Opcode::StoreZero64:
267 out.print("StoreZero64");
268 return;
269 case Opcode::SignExtend32ToPtr:
270 out.print("SignExtend32ToPtr");
271 return;
272 case Opcode::ZeroExtend8To32:
273 out.print("ZeroExtend8To32");
274 return;
275 case Opcode::SignExtend8To32:
276 out.print("SignExtend8To32");
277 return;
278 case Opcode::ZeroExtend16To32:
279 out.print("ZeroExtend16To32");
280 return;
281 case Opcode::SignExtend16To32:
282 out.print("SignExtend16To32");
283 return;
284 case Opcode::MoveFloat:
285 out.print("MoveFloat");
286 return;
287 case Opcode::MoveDouble:
288 out.print("MoveDouble");
289 return;
290 case Opcode::MoveZeroToDouble:
291 out.print("MoveZeroToDouble");
292 return;
293 case Opcode::Move64ToDouble:
294 out.print("Move64ToDouble");
295 return;
296 case Opcode::Move32ToFloat:
297 out.print("Move32ToFloat");
298 return;
299 case Opcode::MoveDoubleTo64:
300 out.print("MoveDoubleTo64");
301 return;
302 case Opcode::MoveFloatTo32:
303 out.print("MoveFloatTo32");
304 return;
305 case Opcode::Load8:
306 out.print("Load8");
307 return;
308 case Opcode::LoadAcq8:
309 out.print("LoadAcq8");
310 return;
311 case Opcode::Store8:
312 out.print("Store8");
313 return;
314 case Opcode::StoreRel8:
315 out.print("StoreRel8");
316 return;
317 case Opcode::Load8SignedExtendTo32:
318 out.print("Load8SignedExtendTo32");
319 return;
320 case Opcode::LoadAcq8SignedExtendTo32:
321 out.print("LoadAcq8SignedExtendTo32");
322 return;
323 case Opcode::Load16:
324 out.print("Load16");
325 return;
326 case Opcode::LoadAcq16:
327 out.print("LoadAcq16");
328 return;
329 case Opcode::Load16SignedExtendTo32:
330 out.print("Load16SignedExtendTo32");
331 return;
332 case Opcode::LoadAcq16SignedExtendTo32:
333 out.print("LoadAcq16SignedExtendTo32");
334 return;
335 case Opcode::Store16:
336 out.print("Store16");
337 return;
338 case Opcode::StoreRel16:
339 out.print("StoreRel16");
340 return;
341 case Opcode::LoadAcq32:
342 out.print("LoadAcq32");
343 return;
344 case Opcode::StoreRel32:
345 out.print("StoreRel32");
346 return;
347 case Opcode::LoadAcq64:
348 out.print("LoadAcq64");
349 return;
350 case Opcode::StoreRel64:
351 out.print("StoreRel64");
352 return;
353 case Opcode::Xchg8:
354 out.print("Xchg8");
355 return;
356 case Opcode::Xchg16:
357 out.print("Xchg16");
358 return;
359 case Opcode::Xchg32:
360 out.print("Xchg32");
361 return;
362 case Opcode::Xchg64:
363 out.print("Xchg64");
364 return;
365 case Opcode::AtomicStrongCAS8:
366 out.print("AtomicStrongCAS8");
367 return;
368 case Opcode::AtomicStrongCAS16:
369 out.print("AtomicStrongCAS16");
370 return;
371 case Opcode::AtomicStrongCAS32:
372 out.print("AtomicStrongCAS32");
373 return;
374 case Opcode::AtomicStrongCAS64:
375 out.print("AtomicStrongCAS64");
376 return;
377 case Opcode::BranchAtomicStrongCAS8:
378 out.print("BranchAtomicStrongCAS8");
379 return;
380 case Opcode::BranchAtomicStrongCAS16:
381 out.print("BranchAtomicStrongCAS16");
382 return;
383 case Opcode::BranchAtomicStrongCAS32:
384 out.print("BranchAtomicStrongCAS32");
385 return;
386 case Opcode::BranchAtomicStrongCAS64:
387 out.print("BranchAtomicStrongCAS64");
388 return;
389 case Opcode::AtomicAdd8:
390 out.print("AtomicAdd8");
391 return;
392 case Opcode::AtomicAdd16:
393 out.print("AtomicAdd16");
394 return;
395 case Opcode::AtomicAdd32:
396 out.print("AtomicAdd32");
397 return;
398 case Opcode::AtomicAdd64:
399 out.print("AtomicAdd64");
400 return;
401 case Opcode::AtomicSub8:
402 out.print("AtomicSub8");
403 return;
404 case Opcode::AtomicSub16:
405 out.print("AtomicSub16");
406 return;
407 case Opcode::AtomicSub32:
408 out.print("AtomicSub32");
409 return;
410 case Opcode::AtomicSub64:
411 out.print("AtomicSub64");
412 return;
413 case Opcode::AtomicAnd8:
414 out.print("AtomicAnd8");
415 return;
416 case Opcode::AtomicAnd16:
417 out.print("AtomicAnd16");
418 return;
419 case Opcode::AtomicAnd32:
420 out.print("AtomicAnd32");
421 return;
422 case Opcode::AtomicAnd64:
423 out.print("AtomicAnd64");
424 return;
425 case Opcode::AtomicOr8:
426 out.print("AtomicOr8");
427 return;
428 case Opcode::AtomicOr16:
429 out.print("AtomicOr16");
430 return;
431 case Opcode::AtomicOr32:
432 out.print("AtomicOr32");
433 return;
434 case Opcode::AtomicOr64:
435 out.print("AtomicOr64");
436 return;
437 case Opcode::AtomicXor8:
438 out.print("AtomicXor8");
439 return;
440 case Opcode::AtomicXor16:
441 out.print("AtomicXor16");
442 return;
443 case Opcode::AtomicXor32:
444 out.print("AtomicXor32");
445 return;
446 case Opcode::AtomicXor64:
447 out.print("AtomicXor64");
448 return;
449 case Opcode::AtomicNeg8:
450 out.print("AtomicNeg8");
451 return;
452 case Opcode::AtomicNeg16:
453 out.print("AtomicNeg16");
454 return;
455 case Opcode::AtomicNeg32:
456 out.print("AtomicNeg32");
457 return;
458 case Opcode::AtomicNeg64:
459 out.print("AtomicNeg64");
460 return;
461 case Opcode::AtomicNot8:
462 out.print("AtomicNot8");
463 return;
464 case Opcode::AtomicNot16:
465 out.print("AtomicNot16");
466 return;
467 case Opcode::AtomicNot32:
468 out.print("AtomicNot32");
469 return;
470 case Opcode::AtomicNot64:
471 out.print("AtomicNot64");
472 return;
473 case Opcode::AtomicXchgAdd8:
474 out.print("AtomicXchgAdd8");
475 return;
476 case Opcode::AtomicXchgAdd16:
477 out.print("AtomicXchgAdd16");
478 return;
479 case Opcode::AtomicXchgAdd32:
480 out.print("AtomicXchgAdd32");
481 return;
482 case Opcode::AtomicXchgAdd64:
483 out.print("AtomicXchgAdd64");
484 return;
485 case Opcode::AtomicXchg8:
486 out.print("AtomicXchg8");
487 return;
488 case Opcode::AtomicXchg16:
489 out.print("AtomicXchg16");
490 return;
491 case Opcode::AtomicXchg32:
492 out.print("AtomicXchg32");
493 return;
494 case Opcode::AtomicXchg64:
495 out.print("AtomicXchg64");
496 return;
497 case Opcode::LoadLink8:
498 out.print("LoadLink8");
499 return;
500 case Opcode::LoadLinkAcq8:
501 out.print("LoadLinkAcq8");
502 return;
503 case Opcode::StoreCond8:
504 out.print("StoreCond8");
505 return;
506 case Opcode::StoreCondRel8:
507 out.print("StoreCondRel8");
508 return;
509 case Opcode::LoadLink16:
510 out.print("LoadLink16");
511 return;
512 case Opcode::LoadLinkAcq16:
513 out.print("LoadLinkAcq16");
514 return;
515 case Opcode::StoreCond16:
516 out.print("StoreCond16");
517 return;
518 case Opcode::StoreCondRel16:
519 out.print("StoreCondRel16");
520 return;
521 case Opcode::LoadLink32:
522 out.print("LoadLink32");
523 return;
524 case Opcode::LoadLinkAcq32:
525 out.print("LoadLinkAcq32");
526 return;
527 case Opcode::StoreCond32:
528 out.print("StoreCond32");
529 return;
530 case Opcode::StoreCondRel32:
531 out.print("StoreCondRel32");
532 return;
533 case Opcode::LoadLink64:
534 out.print("LoadLink64");
535 return;
536 case Opcode::LoadLinkAcq64:
537 out.print("LoadLinkAcq64");
538 return;
539 case Opcode::StoreCond64:
540 out.print("StoreCond64");
541 return;
542 case Opcode::StoreCondRel64:
543 out.print("StoreCondRel64");
544 return;
545 case Opcode::Depend32:
546 out.print("Depend32");
547 return;
548 case Opcode::Depend64:
549 out.print("Depend64");
550 return;
551 case Opcode::Compare32:
552 out.print("Compare32");
553 return;
554 case Opcode::Compare64:
555 out.print("Compare64");
556 return;
557 case Opcode::Test32:
558 out.print("Test32");
559 return;
560 case Opcode::Test64:
561 out.print("Test64");
562 return;
563 case Opcode::CompareDouble:
564 out.print("CompareDouble");
565 return;
566 case Opcode::CompareFloat:
567 out.print("CompareFloat");
568 return;
569 case Opcode::Branch8:
570 out.print("Branch8");
571 return;
572 case Opcode::Branch32:
573 out.print("Branch32");
574 return;
575 case Opcode::Branch64:
576 out.print("Branch64");
577 return;
578 case Opcode::BranchTest8:
579 out.print("BranchTest8");
580 return;
581 case Opcode::BranchTest32:
582 out.print("BranchTest32");
583 return;
584 case Opcode::BranchTest64:
585 out.print("BranchTest64");
586 return;
587 case Opcode::BranchTestBit64:
588 out.print("BranchTestBit64");
589 return;
590 case Opcode::BranchTestBit32:
591 out.print("BranchTestBit32");
592 return;
593 case Opcode::BranchDouble:
594 out.print("BranchDouble");
595 return;
596 case Opcode::BranchFloat:
597 out.print("BranchFloat");
598 return;
599 case Opcode::BranchAdd32:
600 out.print("BranchAdd32");
601 return;
602 case Opcode::BranchAdd64:
603 out.print("BranchAdd64");
604 return;
605 case Opcode::BranchMul32:
606 out.print("BranchMul32");
607 return;
608 case Opcode::BranchMul64:
609 out.print("BranchMul64");
610 return;
611 case Opcode::BranchSub32:
612 out.print("BranchSub32");
613 return;
614 case Opcode::BranchSub64:
615 out.print("BranchSub64");
616 return;
617 case Opcode::BranchNeg32:
618 out.print("BranchNeg32");
619 return;
620 case Opcode::BranchNeg64:
621 out.print("BranchNeg64");
622 return;
623 case Opcode::MoveConditionally32:
624 out.print("MoveConditionally32");
625 return;
626 case Opcode::MoveConditionally64:
627 out.print("MoveConditionally64");
628 return;
629 case Opcode::MoveConditionallyTest32:
630 out.print("MoveConditionallyTest32");
631 return;
632 case Opcode::MoveConditionallyTest64:
633 out.print("MoveConditionallyTest64");
634 return;
635 case Opcode::MoveConditionallyDouble:
636 out.print("MoveConditionallyDouble");
637 return;
638 case Opcode::MoveConditionallyFloat:
639 out.print("MoveConditionallyFloat");
640 return;
641 case Opcode::MoveDoubleConditionally32:
642 out.print("MoveDoubleConditionally32");
643 return;
644 case Opcode::MoveDoubleConditionally64:
645 out.print("MoveDoubleConditionally64");
646 return;
647 case Opcode::MoveDoubleConditionallyTest32:
648 out.print("MoveDoubleConditionallyTest32");
649 return;
650 case Opcode::MoveDoubleConditionallyTest64:
651 out.print("MoveDoubleConditionallyTest64");
652 return;
653 case Opcode::MoveDoubleConditionallyDouble:
654 out.print("MoveDoubleConditionallyDouble");
655 return;
656 case Opcode::MoveDoubleConditionallyFloat:
657 out.print("MoveDoubleConditionallyFloat");
658 return;
659 case Opcode::MemoryFence:
660 out.print("MemoryFence");
661 return;
662 case Opcode::StoreFence:
663 out.print("StoreFence");
664 return;
665 case Opcode::LoadFence:
666 out.print("LoadFence");
667 return;
668 case Opcode::Jump:
669 out.print("Jump");
670 return;
671 case Opcode::RetVoid:
672 out.print("RetVoid");
673 return;
674 case Opcode::Ret32:
675 out.print("Ret32");
676 return;
677 case Opcode::Ret64:
678 out.print("Ret64");
679 return;
680 case Opcode::RetFloat:
681 out.print("RetFloat");
682 return;
683 case Opcode::RetDouble:
684 out.print("RetDouble");
685 return;
686 case Opcode::Oops:
687 out.print("Oops");
688 return;
689 case Opcode::EntrySwitch:
690 out.print("EntrySwitch");
691 return;
692 case Opcode::Shuffle:
693 out.print("Shuffle");
694 return;
695 case Opcode::Patch:
696 out.print("Patch");
697 return;
698 case Opcode::CCall:
699 out.print("CCall");
700 return;
701 case Opcode::ColdCCall:
702 out.print("ColdCCall");
703 return;
704 case Opcode::WasmBoundsCheck:
705 out.print("WasmBoundsCheck");
706 return;
707 }
708 RELEASE_ASSERT_NOT_REACHED();
709}
710} // namespace WTF
711namespace JSC { namespace B3 { namespace Air {
712const uint8_t g_formTable[4872] = {
713// Nop
714
715// Invalid: Nop with numOperands = 1
716INVALID_INST_FORM,
717// Invalid: Nop with numOperands = 2
718INVALID_INST_FORM, INVALID_INST_FORM,
719// Invalid: Nop with numOperands = 3
720INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
721// Invalid: Nop with numOperands = 4
722INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
723// Invalid: Nop with numOperands = 5
724INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
725// Invalid: Nop with numOperands = 6
726INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
727// Invalid: Add32 with numOperands = 0
728
729// Invalid: Add32 with numOperands = 1
730INVALID_INST_FORM,
731// Add32 U:G:32, UZD:G:32
732ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
733// Add32 U:G:32, U:G:32, ZD:G:32
734ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
735// Invalid: Add32 with numOperands = 4
736INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
737// Invalid: Add32 with numOperands = 5
738INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
739// Invalid: Add32 with numOperands = 6
740INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
741// Invalid: Add8 with numOperands = 0
742
743// Invalid: Add8 with numOperands = 1
744INVALID_INST_FORM,
745// Add8 U:G:8, UD:G:8
746ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
747// Invalid: Add8 with numOperands = 3
748INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
749// Invalid: Add8 with numOperands = 4
750INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
751// Invalid: Add8 with numOperands = 5
752INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
753// Invalid: Add8 with numOperands = 6
754INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
755// Invalid: Add16 with numOperands = 0
756
757// Invalid: Add16 with numOperands = 1
758INVALID_INST_FORM,
759// Add16 U:G:16, UD:G:16
760ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
761// Invalid: Add16 with numOperands = 3
762INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
763// Invalid: Add16 with numOperands = 4
764INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
765// Invalid: Add16 with numOperands = 5
766INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
767// Invalid: Add16 with numOperands = 6
768INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
769// Invalid: Add64 with numOperands = 0
770
771// Invalid: Add64 with numOperands = 1
772INVALID_INST_FORM,
773// Add64 U:G:64, UD:G:64
774ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
775// Add64 U:G:64, U:G:64, D:G:64
776ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
777// Invalid: Add64 with numOperands = 4
778INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
779// Invalid: Add64 with numOperands = 5
780INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
781// Invalid: Add64 with numOperands = 6
782INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
783// Invalid: AddDouble with numOperands = 0
784
785// Invalid: AddDouble with numOperands = 1
786INVALID_INST_FORM,
787// AddDouble U:F:64, UD:F:64
788ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
789// AddDouble U:F:64, U:F:64, D:F:64
790ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
791// Invalid: AddDouble with numOperands = 4
792INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
793// Invalid: AddDouble with numOperands = 5
794INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
795// Invalid: AddDouble with numOperands = 6
796INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
797// Invalid: AddFloat with numOperands = 0
798
799// Invalid: AddFloat with numOperands = 1
800INVALID_INST_FORM,
801// AddFloat U:F:32, UD:F:32
802ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
803// AddFloat U:F:32, U:F:32, D:F:32
804ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
805// Invalid: AddFloat with numOperands = 4
806INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
807// Invalid: AddFloat with numOperands = 5
808INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
809// Invalid: AddFloat with numOperands = 6
810INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
811// Invalid: Sub32 with numOperands = 0
812
813// Invalid: Sub32 with numOperands = 1
814INVALID_INST_FORM,
815// Sub32 U:G:32, UZD:G:32
816ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
817// Sub32 U:G:32, U:G:32, D:G:32
818ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
819// Invalid: Sub32 with numOperands = 4
820INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
821// Invalid: Sub32 with numOperands = 5
822INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
823// Invalid: Sub32 with numOperands = 6
824INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
825// Invalid: Sub64 with numOperands = 0
826
827// Invalid: Sub64 with numOperands = 1
828INVALID_INST_FORM,
829// Sub64 U:G:64, UD:G:64
830ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
831// Sub64 U:G:64, U:G:64, D:G:64
832ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
833// Invalid: Sub64 with numOperands = 4
834INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
835// Invalid: Sub64 with numOperands = 5
836INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
837// Invalid: Sub64 with numOperands = 6
838INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
839// Invalid: SubDouble with numOperands = 0
840
841// Invalid: SubDouble with numOperands = 1
842INVALID_INST_FORM,
843// SubDouble U:F:64, UD:F:64
844ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
845// SubDouble U:F:64, U:F:64, D:F:64
846ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
847// Invalid: SubDouble with numOperands = 4
848INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
849// Invalid: SubDouble with numOperands = 5
850INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
851// Invalid: SubDouble with numOperands = 6
852INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
853// Invalid: SubFloat with numOperands = 0
854
855// Invalid: SubFloat with numOperands = 1
856INVALID_INST_FORM,
857// SubFloat U:F:32, UD:F:32
858ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
859// SubFloat U:F:32, U:F:32, D:F:32
860ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
861// Invalid: SubFloat with numOperands = 4
862INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
863// Invalid: SubFloat with numOperands = 5
864INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
865// Invalid: SubFloat with numOperands = 6
866INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
867// Invalid: Neg32 with numOperands = 0
868
869// Neg32 UZD:G:32
870ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
871// Invalid: Neg32 with numOperands = 2
872INVALID_INST_FORM, INVALID_INST_FORM,
873// Invalid: Neg32 with numOperands = 3
874INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
875// Invalid: Neg32 with numOperands = 4
876INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
877// Invalid: Neg32 with numOperands = 5
878INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
879// Invalid: Neg32 with numOperands = 6
880INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
881// Invalid: Neg64 with numOperands = 0
882
883// Neg64 UD:G:64
884ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
885// Invalid: Neg64 with numOperands = 2
886INVALID_INST_FORM, INVALID_INST_FORM,
887// Invalid: Neg64 with numOperands = 3
888INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
889// Invalid: Neg64 with numOperands = 4
890INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
891// Invalid: Neg64 with numOperands = 5
892INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
893// Invalid: Neg64 with numOperands = 6
894INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
895// Invalid: NegateDouble with numOperands = 0
896
897// Invalid: NegateDouble with numOperands = 1
898INVALID_INST_FORM,
899// NegateDouble U:F:64, D:F:64
900ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
901// Invalid: NegateDouble with numOperands = 3
902INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
903// Invalid: NegateDouble with numOperands = 4
904INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
905// Invalid: NegateDouble with numOperands = 5
906INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
907// Invalid: NegateDouble with numOperands = 6
908INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
909// Invalid: NegateFloat with numOperands = 0
910
911// Invalid: NegateFloat with numOperands = 1
912INVALID_INST_FORM,
913// NegateFloat U:F:32, D:F:32
914ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
915// Invalid: NegateFloat with numOperands = 3
916INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
917// Invalid: NegateFloat with numOperands = 4
918INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
919// Invalid: NegateFloat with numOperands = 5
920INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
921// Invalid: NegateFloat with numOperands = 6
922INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
923// Invalid: Mul32 with numOperands = 0
924
925// Invalid: Mul32 with numOperands = 1
926INVALID_INST_FORM,
927// Mul32 U:G:32, UZD:G:32
928ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
929// Mul32 U:G:32, U:G:32, ZD:G:32
930ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
931// Invalid: Mul32 with numOperands = 4
932INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
933// Invalid: Mul32 with numOperands = 5
934INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
935// Invalid: Mul32 with numOperands = 6
936INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
937// Invalid: Mul64 with numOperands = 0
938
939// Invalid: Mul64 with numOperands = 1
940INVALID_INST_FORM,
941// Mul64 U:G:64, UD:G:64
942ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
943// Mul64 U:G:64, U:G:64, D:G:64
944ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
945// Invalid: Mul64 with numOperands = 4
946INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
947// Invalid: Mul64 with numOperands = 5
948INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
949// Invalid: Mul64 with numOperands = 6
950INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
951// Invalid: MultiplyAdd32 with numOperands = 0
952
953// Invalid: MultiplyAdd32 with numOperands = 1
954INVALID_INST_FORM,
955// Invalid: MultiplyAdd32 with numOperands = 2
956INVALID_INST_FORM, INVALID_INST_FORM,
957// Invalid: MultiplyAdd32 with numOperands = 3
958INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
959// MultiplyAdd32 U:G:32, U:G:32, U:G:32, ZD:G:32
960ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
961// Invalid: MultiplyAdd32 with numOperands = 5
962INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
963// Invalid: MultiplyAdd32 with numOperands = 6
964INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
965// Invalid: MultiplyAdd64 with numOperands = 0
966
967// Invalid: MultiplyAdd64 with numOperands = 1
968INVALID_INST_FORM,
969// Invalid: MultiplyAdd64 with numOperands = 2
970INVALID_INST_FORM, INVALID_INST_FORM,
971// Invalid: MultiplyAdd64 with numOperands = 3
972INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
973// MultiplyAdd64 U:G:64, U:G:64, U:G:64, D:G:64
974ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
975// Invalid: MultiplyAdd64 with numOperands = 5
976INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
977// Invalid: MultiplyAdd64 with numOperands = 6
978INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
979// Invalid: MultiplySub32 with numOperands = 0
980
981// Invalid: MultiplySub32 with numOperands = 1
982INVALID_INST_FORM,
983// Invalid: MultiplySub32 with numOperands = 2
984INVALID_INST_FORM, INVALID_INST_FORM,
985// Invalid: MultiplySub32 with numOperands = 3
986INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
987// MultiplySub32 U:G:32, U:G:32, U:G:32, ZD:G:32
988ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
989// Invalid: MultiplySub32 with numOperands = 5
990INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
991// Invalid: MultiplySub32 with numOperands = 6
992INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
993// Invalid: MultiplySub64 with numOperands = 0
994
995// Invalid: MultiplySub64 with numOperands = 1
996INVALID_INST_FORM,
997// Invalid: MultiplySub64 with numOperands = 2
998INVALID_INST_FORM, INVALID_INST_FORM,
999// Invalid: MultiplySub64 with numOperands = 3
1000INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1001// MultiplySub64 U:G:64, U:G:64, U:G:64, D:G:64
1002ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1003// Invalid: MultiplySub64 with numOperands = 5
1004INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1005// Invalid: MultiplySub64 with numOperands = 6
1006INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1007// Invalid: MultiplyNeg32 with numOperands = 0
1008
1009// Invalid: MultiplyNeg32 with numOperands = 1
1010INVALID_INST_FORM,
1011// Invalid: MultiplyNeg32 with numOperands = 2
1012INVALID_INST_FORM, INVALID_INST_FORM,
1013// MultiplyNeg32 U:G:32, U:G:32, ZD:G:32
1014ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1015// Invalid: MultiplyNeg32 with numOperands = 4
1016INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1017// Invalid: MultiplyNeg32 with numOperands = 5
1018INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1019// Invalid: MultiplyNeg32 with numOperands = 6
1020INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1021// Invalid: MultiplyNeg64 with numOperands = 0
1022
1023// Invalid: MultiplyNeg64 with numOperands = 1
1024INVALID_INST_FORM,
1025// Invalid: MultiplyNeg64 with numOperands = 2
1026INVALID_INST_FORM, INVALID_INST_FORM,
1027// MultiplyNeg64 U:G:64, U:G:64, ZD:G:64
1028ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
1029// Invalid: MultiplyNeg64 with numOperands = 4
1030INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1031// Invalid: MultiplyNeg64 with numOperands = 5
1032INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1033// Invalid: MultiplyNeg64 with numOperands = 6
1034INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1035// Invalid: MultiplySignExtend32 with numOperands = 0
1036
1037// Invalid: MultiplySignExtend32 with numOperands = 1
1038INVALID_INST_FORM,
1039// Invalid: MultiplySignExtend32 with numOperands = 2
1040INVALID_INST_FORM, INVALID_INST_FORM,
1041// MultiplySignExtend32 U:G:32, U:G:32, ZD:G:64
1042ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
1043// Invalid: MultiplySignExtend32 with numOperands = 4
1044INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1045// Invalid: MultiplySignExtend32 with numOperands = 5
1046INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1047// Invalid: MultiplySignExtend32 with numOperands = 6
1048INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1049// Invalid: Div32 with numOperands = 0
1050
1051// Invalid: Div32 with numOperands = 1
1052INVALID_INST_FORM,
1053// Invalid: Div32 with numOperands = 2
1054INVALID_INST_FORM, INVALID_INST_FORM,
1055// Div32 U:G:32, U:G:32, ZD:G:32
1056ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1057// Invalid: Div32 with numOperands = 4
1058INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1059// Invalid: Div32 with numOperands = 5
1060INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1061// Invalid: Div32 with numOperands = 6
1062INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1063// Invalid: UDiv32 with numOperands = 0
1064
1065// Invalid: UDiv32 with numOperands = 1
1066INVALID_INST_FORM,
1067// Invalid: UDiv32 with numOperands = 2
1068INVALID_INST_FORM, INVALID_INST_FORM,
1069// UDiv32 U:G:32, U:G:32, ZD:G:32
1070ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1071// Invalid: UDiv32 with numOperands = 4
1072INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1073// Invalid: UDiv32 with numOperands = 5
1074INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1075// Invalid: UDiv32 with numOperands = 6
1076INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1077// Invalid: Div64 with numOperands = 0
1078
1079// Invalid: Div64 with numOperands = 1
1080INVALID_INST_FORM,
1081// Invalid: Div64 with numOperands = 2
1082INVALID_INST_FORM, INVALID_INST_FORM,
1083// Div64 U:G:64, U:G:64, D:G:64
1084ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1085// Invalid: Div64 with numOperands = 4
1086INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1087// Invalid: Div64 with numOperands = 5
1088INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1089// Invalid: Div64 with numOperands = 6
1090INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1091// Invalid: UDiv64 with numOperands = 0
1092
1093// Invalid: UDiv64 with numOperands = 1
1094INVALID_INST_FORM,
1095// Invalid: UDiv64 with numOperands = 2
1096INVALID_INST_FORM, INVALID_INST_FORM,
1097// UDiv64 U:G:64, U:G:64, D:G:64
1098ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1099// Invalid: UDiv64 with numOperands = 4
1100INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1101// Invalid: UDiv64 with numOperands = 5
1102INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1103// Invalid: UDiv64 with numOperands = 6
1104INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1105// Invalid: MulDouble with numOperands = 0
1106
1107// Invalid: MulDouble with numOperands = 1
1108INVALID_INST_FORM,
1109// MulDouble U:F:64, UD:F:64
1110ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1111// MulDouble U:F:64, U:F:64, D:F:64
1112ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1113// Invalid: MulDouble with numOperands = 4
1114INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1115// Invalid: MulDouble with numOperands = 5
1116INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1117// Invalid: MulDouble with numOperands = 6
1118INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1119// Invalid: MulFloat with numOperands = 0
1120
1121// Invalid: MulFloat with numOperands = 1
1122INVALID_INST_FORM,
1123// MulFloat U:F:32, UD:F:32
1124ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1125// MulFloat U:F:32, U:F:32, D:F:32
1126ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1127// Invalid: MulFloat with numOperands = 4
1128INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1129// Invalid: MulFloat with numOperands = 5
1130INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1131// Invalid: MulFloat with numOperands = 6
1132INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1133// Invalid: DivDouble with numOperands = 0
1134
1135// Invalid: DivDouble with numOperands = 1
1136INVALID_INST_FORM,
1137// DivDouble U:F:64, UD:F:64
1138ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1139// DivDouble U:F:64, U:F:32, D:F:64
1140ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1141// Invalid: DivDouble with numOperands = 4
1142INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1143// Invalid: DivDouble with numOperands = 5
1144INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1145// Invalid: DivDouble with numOperands = 6
1146INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1147// Invalid: DivFloat with numOperands = 0
1148
1149// Invalid: DivFloat with numOperands = 1
1150INVALID_INST_FORM,
1151// DivFloat U:F:32, UD:F:32
1152ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1153// DivFloat U:F:32, U:F:32, D:F:32
1154ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1155// Invalid: DivFloat with numOperands = 4
1156INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1157// Invalid: DivFloat with numOperands = 5
1158INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1159// Invalid: DivFloat with numOperands = 6
1160INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1161// Invalid: X86ConvertToDoubleWord32 with numOperands = 0
1162
1163// Invalid: X86ConvertToDoubleWord32 with numOperands = 1
1164INVALID_INST_FORM,
1165// X86ConvertToDoubleWord32 U:G:32, ZD:G:32
1166ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1167// Invalid: X86ConvertToDoubleWord32 with numOperands = 3
1168INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1169// Invalid: X86ConvertToDoubleWord32 with numOperands = 4
1170INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1171// Invalid: X86ConvertToDoubleWord32 with numOperands = 5
1172INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1173// Invalid: X86ConvertToDoubleWord32 with numOperands = 6
1174INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1175// Invalid: X86ConvertToQuadWord64 with numOperands = 0
1176
1177// Invalid: X86ConvertToQuadWord64 with numOperands = 1
1178INVALID_INST_FORM,
1179// X86ConvertToQuadWord64 U:G:64, D:G:64
1180ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1181// Invalid: X86ConvertToQuadWord64 with numOperands = 3
1182INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1183// Invalid: X86ConvertToQuadWord64 with numOperands = 4
1184INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1185// Invalid: X86ConvertToQuadWord64 with numOperands = 5
1186INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1187// Invalid: X86ConvertToQuadWord64 with numOperands = 6
1188INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1189// Invalid: X86Div32 with numOperands = 0
1190
1191// Invalid: X86Div32 with numOperands = 1
1192INVALID_INST_FORM,
1193// Invalid: X86Div32 with numOperands = 2
1194INVALID_INST_FORM, INVALID_INST_FORM,
1195// X86Div32 UZD:G:32, UZD:G:32, U:G:32
1196ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
1197// Invalid: X86Div32 with numOperands = 4
1198INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1199// Invalid: X86Div32 with numOperands = 5
1200INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1201// Invalid: X86Div32 with numOperands = 6
1202INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1203// Invalid: X86UDiv32 with numOperands = 0
1204
1205// Invalid: X86UDiv32 with numOperands = 1
1206INVALID_INST_FORM,
1207// Invalid: X86UDiv32 with numOperands = 2
1208INVALID_INST_FORM, INVALID_INST_FORM,
1209// X86UDiv32 UZD:G:32, UZD:G:32, U:G:32
1210ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
1211// Invalid: X86UDiv32 with numOperands = 4
1212INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1213// Invalid: X86UDiv32 with numOperands = 5
1214INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1215// Invalid: X86UDiv32 with numOperands = 6
1216INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1217// Invalid: X86Div64 with numOperands = 0
1218
1219// Invalid: X86Div64 with numOperands = 1
1220INVALID_INST_FORM,
1221// Invalid: X86Div64 with numOperands = 2
1222INVALID_INST_FORM, INVALID_INST_FORM,
1223// X86Div64 UZD:G:64, UZD:G:64, U:G:64
1224ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
1225// Invalid: X86Div64 with numOperands = 4
1226INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1227// Invalid: X86Div64 with numOperands = 5
1228INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1229// Invalid: X86Div64 with numOperands = 6
1230INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1231// Invalid: X86UDiv64 with numOperands = 0
1232
1233// Invalid: X86UDiv64 with numOperands = 1
1234INVALID_INST_FORM,
1235// Invalid: X86UDiv64 with numOperands = 2
1236INVALID_INST_FORM, INVALID_INST_FORM,
1237// X86UDiv64 UZD:G:64, UZD:G:64, U:G:64
1238ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
1239// Invalid: X86UDiv64 with numOperands = 4
1240INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1241// Invalid: X86UDiv64 with numOperands = 5
1242INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1243// Invalid: X86UDiv64 with numOperands = 6
1244INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1245// Invalid: Lea32 with numOperands = 0
1246
1247// Invalid: Lea32 with numOperands = 1
1248INVALID_INST_FORM,
1249// Lea32 UA:G:32, D:G:32
1250ENCODE_INST_FORM(Arg::UseAddr, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
1251// Invalid: Lea32 with numOperands = 3
1252INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1253// Invalid: Lea32 with numOperands = 4
1254INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1255// Invalid: Lea32 with numOperands = 5
1256INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1257// Invalid: Lea32 with numOperands = 6
1258INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1259// Invalid: Lea64 with numOperands = 0
1260
1261// Invalid: Lea64 with numOperands = 1
1262INVALID_INST_FORM,
1263// Lea64 UA:G:64, D:G:64
1264ENCODE_INST_FORM(Arg::UseAddr, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1265// Invalid: Lea64 with numOperands = 3
1266INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1267// Invalid: Lea64 with numOperands = 4
1268INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1269// Invalid: Lea64 with numOperands = 5
1270INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1271// Invalid: Lea64 with numOperands = 6
1272INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1273// Invalid: And32 with numOperands = 0
1274
1275// Invalid: And32 with numOperands = 1
1276INVALID_INST_FORM,
1277// And32 U:G:32, UZD:G:32
1278ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1279// And32 U:G:32, U:G:32, ZD:G:32
1280ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1281// Invalid: And32 with numOperands = 4
1282INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1283// Invalid: And32 with numOperands = 5
1284INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1285// Invalid: And32 with numOperands = 6
1286INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1287// Invalid: And64 with numOperands = 0
1288
1289// Invalid: And64 with numOperands = 1
1290INVALID_INST_FORM,
1291// And64 U:G:64, UD:G:64
1292ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1293// And64 U:G:64, U:G:64, D:G:64
1294ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1295// Invalid: And64 with numOperands = 4
1296INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1297// Invalid: And64 with numOperands = 5
1298INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1299// Invalid: And64 with numOperands = 6
1300INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1301// Invalid: AndDouble with numOperands = 0
1302
1303// Invalid: AndDouble with numOperands = 1
1304INVALID_INST_FORM,
1305// AndDouble U:F:64, UD:F:64
1306ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1307// AndDouble U:F:64, U:F:64, D:F:64
1308ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1309// Invalid: AndDouble with numOperands = 4
1310INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1311// Invalid: AndDouble with numOperands = 5
1312INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1313// Invalid: AndDouble with numOperands = 6
1314INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1315// Invalid: AndFloat with numOperands = 0
1316
1317// Invalid: AndFloat with numOperands = 1
1318INVALID_INST_FORM,
1319// AndFloat U:F:32, UD:F:32
1320ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1321// AndFloat U:F:32, U:F:32, D:F:32
1322ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1323// Invalid: AndFloat with numOperands = 4
1324INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1325// Invalid: AndFloat with numOperands = 5
1326INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1327// Invalid: AndFloat with numOperands = 6
1328INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1329// Invalid: OrDouble with numOperands = 0
1330
1331// Invalid: OrDouble with numOperands = 1
1332INVALID_INST_FORM,
1333// OrDouble U:F:64, UD:F:64
1334ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1335// OrDouble U:F:64, U:F:64, D:F:64
1336ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1337// Invalid: OrDouble with numOperands = 4
1338INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1339// Invalid: OrDouble with numOperands = 5
1340INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1341// Invalid: OrDouble with numOperands = 6
1342INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1343// Invalid: OrFloat with numOperands = 0
1344
1345// Invalid: OrFloat with numOperands = 1
1346INVALID_INST_FORM,
1347// OrFloat U:F:32, UD:F:32
1348ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1349// OrFloat U:F:32, U:F:32, D:F:32
1350ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1351// Invalid: OrFloat with numOperands = 4
1352INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1353// Invalid: OrFloat with numOperands = 5
1354INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1355// Invalid: OrFloat with numOperands = 6
1356INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1357// Invalid: XorDouble with numOperands = 0
1358
1359// Invalid: XorDouble with numOperands = 1
1360INVALID_INST_FORM,
1361// XorDouble U:F:64, UD:F:64
1362ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1363// XorDouble U:F:64, U:F:64, D:F:64
1364ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1365// Invalid: XorDouble with numOperands = 4
1366INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1367// Invalid: XorDouble with numOperands = 5
1368INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1369// Invalid: XorDouble with numOperands = 6
1370INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1371// Invalid: XorFloat with numOperands = 0
1372
1373// Invalid: XorFloat with numOperands = 1
1374INVALID_INST_FORM,
1375// XorFloat U:F:32, UD:F:32
1376ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1377// XorFloat U:F:32, U:F:32, D:F:32
1378ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1379// Invalid: XorFloat with numOperands = 4
1380INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1381// Invalid: XorFloat with numOperands = 5
1382INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1383// Invalid: XorFloat with numOperands = 6
1384INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1385// Invalid: Lshift32 with numOperands = 0
1386
1387// Invalid: Lshift32 with numOperands = 1
1388INVALID_INST_FORM,
1389// Lshift32 U:G:32, UZD:G:32
1390ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1391// Lshift32 U:G:32, U:G:32, ZD:G:32
1392ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1393// Invalid: Lshift32 with numOperands = 4
1394INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1395// Invalid: Lshift32 with numOperands = 5
1396INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1397// Invalid: Lshift32 with numOperands = 6
1398INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1399// Invalid: Lshift64 with numOperands = 0
1400
1401// Invalid: Lshift64 with numOperands = 1
1402INVALID_INST_FORM,
1403// Lshift64 U:G:64, UD:G:64
1404ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1405// Lshift64 U:G:64, U:G:64, D:G:64
1406ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1407// Invalid: Lshift64 with numOperands = 4
1408INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1409// Invalid: Lshift64 with numOperands = 5
1410INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1411// Invalid: Lshift64 with numOperands = 6
1412INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1413// Invalid: Rshift32 with numOperands = 0
1414
1415// Invalid: Rshift32 with numOperands = 1
1416INVALID_INST_FORM,
1417// Rshift32 U:G:32, UZD:G:32
1418ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1419// Rshift32 U:G:32, U:G:32, ZD:G:32
1420ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1421// Invalid: Rshift32 with numOperands = 4
1422INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1423// Invalid: Rshift32 with numOperands = 5
1424INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1425// Invalid: Rshift32 with numOperands = 6
1426INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1427// Invalid: Rshift64 with numOperands = 0
1428
1429// Invalid: Rshift64 with numOperands = 1
1430INVALID_INST_FORM,
1431// Rshift64 U:G:64, UD:G:64
1432ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1433// Rshift64 U:G:64, U:G:64, D:G:64
1434ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1435// Invalid: Rshift64 with numOperands = 4
1436INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1437// Invalid: Rshift64 with numOperands = 5
1438INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1439// Invalid: Rshift64 with numOperands = 6
1440INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1441// Invalid: Urshift32 with numOperands = 0
1442
1443// Invalid: Urshift32 with numOperands = 1
1444INVALID_INST_FORM,
1445// Urshift32 U:G:32, UZD:G:32
1446ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1447// Urshift32 U:G:32, U:G:32, ZD:G:32
1448ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1449// Invalid: Urshift32 with numOperands = 4
1450INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1451// Invalid: Urshift32 with numOperands = 5
1452INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1453// Invalid: Urshift32 with numOperands = 6
1454INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1455// Invalid: Urshift64 with numOperands = 0
1456
1457// Invalid: Urshift64 with numOperands = 1
1458INVALID_INST_FORM,
1459// Urshift64 U:G:64, UD:G:64
1460ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1461// Urshift64 U:G:64, U:G:64, D:G:64
1462ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1463// Invalid: Urshift64 with numOperands = 4
1464INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1465// Invalid: Urshift64 with numOperands = 5
1466INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1467// Invalid: Urshift64 with numOperands = 6
1468INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1469// Invalid: RotateRight32 with numOperands = 0
1470
1471// Invalid: RotateRight32 with numOperands = 1
1472INVALID_INST_FORM,
1473// RotateRight32 U:G:32, UZD:G:32
1474ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1475// RotateRight32 U:G:32, U:G:32, ZD:G:32
1476ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1477// Invalid: RotateRight32 with numOperands = 4
1478INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1479// Invalid: RotateRight32 with numOperands = 5
1480INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1481// Invalid: RotateRight32 with numOperands = 6
1482INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1483// Invalid: RotateRight64 with numOperands = 0
1484
1485// Invalid: RotateRight64 with numOperands = 1
1486INVALID_INST_FORM,
1487// RotateRight64 U:G:64, UD:G:64
1488ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1489// RotateRight64 U:G:64, U:G:64, D:G:64
1490ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1491// Invalid: RotateRight64 with numOperands = 4
1492INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1493// Invalid: RotateRight64 with numOperands = 5
1494INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1495// Invalid: RotateRight64 with numOperands = 6
1496INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1497// Invalid: RotateLeft32 with numOperands = 0
1498
1499// Invalid: RotateLeft32 with numOperands = 1
1500INVALID_INST_FORM,
1501// RotateLeft32 U:G:32, UZD:G:32
1502ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1503// Invalid: RotateLeft32 with numOperands = 3
1504INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1505// Invalid: RotateLeft32 with numOperands = 4
1506INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1507// Invalid: RotateLeft32 with numOperands = 5
1508INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1509// Invalid: RotateLeft32 with numOperands = 6
1510INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1511// Invalid: RotateLeft64 with numOperands = 0
1512
1513// Invalid: RotateLeft64 with numOperands = 1
1514INVALID_INST_FORM,
1515// RotateLeft64 U:G:64, UD:G:64
1516ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1517// Invalid: RotateLeft64 with numOperands = 3
1518INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1519// Invalid: RotateLeft64 with numOperands = 4
1520INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1521// Invalid: RotateLeft64 with numOperands = 5
1522INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1523// Invalid: RotateLeft64 with numOperands = 6
1524INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1525// Invalid: Or32 with numOperands = 0
1526
1527// Invalid: Or32 with numOperands = 1
1528INVALID_INST_FORM,
1529// Or32 U:G:32, UZD:G:32
1530ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1531// Or32 U:G:32, U:G:32, ZD:G:32
1532ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1533// Invalid: Or32 with numOperands = 4
1534INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1535// Invalid: Or32 with numOperands = 5
1536INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1537// Invalid: Or32 with numOperands = 6
1538INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1539// Invalid: Or64 with numOperands = 0
1540
1541// Invalid: Or64 with numOperands = 1
1542INVALID_INST_FORM,
1543// Or64 U:G:64, UD:G:64
1544ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1545// Or64 U:G:64, U:G:64, D:G:64
1546ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1547// Invalid: Or64 with numOperands = 4
1548INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1549// Invalid: Or64 with numOperands = 5
1550INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1551// Invalid: Or64 with numOperands = 6
1552INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1553// Invalid: Xor32 with numOperands = 0
1554
1555// Invalid: Xor32 with numOperands = 1
1556INVALID_INST_FORM,
1557// Xor32 U:G:32, UZD:G:32
1558ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1559// Xor32 U:G:32, U:G:32, ZD:G:32
1560ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1561// Invalid: Xor32 with numOperands = 4
1562INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1563// Invalid: Xor32 with numOperands = 5
1564INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1565// Invalid: Xor32 with numOperands = 6
1566INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1567// Invalid: Xor64 with numOperands = 0
1568
1569// Invalid: Xor64 with numOperands = 1
1570INVALID_INST_FORM,
1571// Xor64 U:G:64, UD:G:64
1572ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1573// Xor64 U:G:64, U:G:64, D:G:64
1574ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1575// Invalid: Xor64 with numOperands = 4
1576INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1577// Invalid: Xor64 with numOperands = 5
1578INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1579// Invalid: Xor64 with numOperands = 6
1580INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1581// Invalid: Not32 with numOperands = 0
1582
1583// Not32 UZD:G:32
1584ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1585// Not32 U:G:32, ZD:G:32
1586ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1587// Invalid: Not32 with numOperands = 3
1588INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1589// Invalid: Not32 with numOperands = 4
1590INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1591// Invalid: Not32 with numOperands = 5
1592INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1593// Invalid: Not32 with numOperands = 6
1594INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1595// Invalid: Not64 with numOperands = 0
1596
1597// Not64 UD:G:64
1598ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1599// Not64 U:G:64, D:G:64
1600ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1601// Invalid: Not64 with numOperands = 3
1602INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1603// Invalid: Not64 with numOperands = 4
1604INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1605// Invalid: Not64 with numOperands = 5
1606INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1607// Invalid: Not64 with numOperands = 6
1608INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1609// Invalid: AbsDouble with numOperands = 0
1610
1611// Invalid: AbsDouble with numOperands = 1
1612INVALID_INST_FORM,
1613// AbsDouble U:F:64, D:F:64
1614ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1615// Invalid: AbsDouble with numOperands = 3
1616INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1617// Invalid: AbsDouble with numOperands = 4
1618INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1619// Invalid: AbsDouble with numOperands = 5
1620INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1621// Invalid: AbsDouble with numOperands = 6
1622INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1623// Invalid: AbsFloat with numOperands = 0
1624
1625// Invalid: AbsFloat with numOperands = 1
1626INVALID_INST_FORM,
1627// AbsFloat U:F:32, D:F:32
1628ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1629// Invalid: AbsFloat with numOperands = 3
1630INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1631// Invalid: AbsFloat with numOperands = 4
1632INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1633// Invalid: AbsFloat with numOperands = 5
1634INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1635// Invalid: AbsFloat with numOperands = 6
1636INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1637// Invalid: CeilDouble with numOperands = 0
1638
1639// Invalid: CeilDouble with numOperands = 1
1640INVALID_INST_FORM,
1641// CeilDouble U:F:64, D:F:64
1642ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1643// Invalid: CeilDouble with numOperands = 3
1644INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1645// Invalid: CeilDouble with numOperands = 4
1646INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1647// Invalid: CeilDouble with numOperands = 5
1648INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1649// Invalid: CeilDouble with numOperands = 6
1650INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1651// Invalid: CeilFloat with numOperands = 0
1652
1653// Invalid: CeilFloat with numOperands = 1
1654INVALID_INST_FORM,
1655// CeilFloat U:F:32, D:F:32
1656ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1657// Invalid: CeilFloat with numOperands = 3
1658INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1659// Invalid: CeilFloat with numOperands = 4
1660INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1661// Invalid: CeilFloat with numOperands = 5
1662INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1663// Invalid: CeilFloat with numOperands = 6
1664INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1665// Invalid: FloorDouble with numOperands = 0
1666
1667// Invalid: FloorDouble with numOperands = 1
1668INVALID_INST_FORM,
1669// FloorDouble U:F:64, D:F:64
1670ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1671// Invalid: FloorDouble with numOperands = 3
1672INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1673// Invalid: FloorDouble with numOperands = 4
1674INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1675// Invalid: FloorDouble with numOperands = 5
1676INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1677// Invalid: FloorDouble with numOperands = 6
1678INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1679// Invalid: FloorFloat with numOperands = 0
1680
1681// Invalid: FloorFloat with numOperands = 1
1682INVALID_INST_FORM,
1683// FloorFloat U:F:32, D:F:32
1684ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1685// Invalid: FloorFloat with numOperands = 3
1686INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1687// Invalid: FloorFloat with numOperands = 4
1688INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1689// Invalid: FloorFloat with numOperands = 5
1690INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1691// Invalid: FloorFloat with numOperands = 6
1692INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1693// Invalid: SqrtDouble with numOperands = 0
1694
1695// Invalid: SqrtDouble with numOperands = 1
1696INVALID_INST_FORM,
1697// SqrtDouble U:F:64, D:F:64
1698ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1699// Invalid: SqrtDouble with numOperands = 3
1700INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1701// Invalid: SqrtDouble with numOperands = 4
1702INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1703// Invalid: SqrtDouble with numOperands = 5
1704INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1705// Invalid: SqrtDouble with numOperands = 6
1706INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1707// Invalid: SqrtFloat with numOperands = 0
1708
1709// Invalid: SqrtFloat with numOperands = 1
1710INVALID_INST_FORM,
1711// SqrtFloat U:F:32, D:F:32
1712ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1713// Invalid: SqrtFloat with numOperands = 3
1714INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1715// Invalid: SqrtFloat with numOperands = 4
1716INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1717// Invalid: SqrtFloat with numOperands = 5
1718INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1719// Invalid: SqrtFloat with numOperands = 6
1720INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1721// Invalid: ConvertInt32ToDouble with numOperands = 0
1722
1723// Invalid: ConvertInt32ToDouble with numOperands = 1
1724INVALID_INST_FORM,
1725// ConvertInt32ToDouble U:G:32, D:F:64
1726ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1727// Invalid: ConvertInt32ToDouble with numOperands = 3
1728INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1729// Invalid: ConvertInt32ToDouble with numOperands = 4
1730INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1731// Invalid: ConvertInt32ToDouble with numOperands = 5
1732INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1733// Invalid: ConvertInt32ToDouble with numOperands = 6
1734INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1735// Invalid: ConvertInt64ToDouble with numOperands = 0
1736
1737// Invalid: ConvertInt64ToDouble with numOperands = 1
1738INVALID_INST_FORM,
1739// ConvertInt64ToDouble U:G:64, D:F:64
1740ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1741// Invalid: ConvertInt64ToDouble with numOperands = 3
1742INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1743// Invalid: ConvertInt64ToDouble with numOperands = 4
1744INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1745// Invalid: ConvertInt64ToDouble with numOperands = 5
1746INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1747// Invalid: ConvertInt64ToDouble with numOperands = 6
1748INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1749// Invalid: ConvertInt32ToFloat with numOperands = 0
1750
1751// Invalid: ConvertInt32ToFloat with numOperands = 1
1752INVALID_INST_FORM,
1753// ConvertInt32ToFloat U:G:32, D:F:32
1754ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1755// Invalid: ConvertInt32ToFloat with numOperands = 3
1756INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1757// Invalid: ConvertInt32ToFloat with numOperands = 4
1758INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1759// Invalid: ConvertInt32ToFloat with numOperands = 5
1760INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1761// Invalid: ConvertInt32ToFloat with numOperands = 6
1762INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1763// Invalid: ConvertInt64ToFloat with numOperands = 0
1764
1765// Invalid: ConvertInt64ToFloat with numOperands = 1
1766INVALID_INST_FORM,
1767// ConvertInt64ToFloat U:G:64, D:F:32
1768ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1769// Invalid: ConvertInt64ToFloat with numOperands = 3
1770INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1771// Invalid: ConvertInt64ToFloat with numOperands = 4
1772INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1773// Invalid: ConvertInt64ToFloat with numOperands = 5
1774INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1775// Invalid: ConvertInt64ToFloat with numOperands = 6
1776INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1777// Invalid: CountLeadingZeros32 with numOperands = 0
1778
1779// Invalid: CountLeadingZeros32 with numOperands = 1
1780INVALID_INST_FORM,
1781// CountLeadingZeros32 U:G:32, ZD:G:32
1782ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1783// Invalid: CountLeadingZeros32 with numOperands = 3
1784INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1785// Invalid: CountLeadingZeros32 with numOperands = 4
1786INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1787// Invalid: CountLeadingZeros32 with numOperands = 5
1788INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1789// Invalid: CountLeadingZeros32 with numOperands = 6
1790INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1791// Invalid: CountLeadingZeros64 with numOperands = 0
1792
1793// Invalid: CountLeadingZeros64 with numOperands = 1
1794INVALID_INST_FORM,
1795// CountLeadingZeros64 U:G:64, D:G:64
1796ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1797// Invalid: CountLeadingZeros64 with numOperands = 3
1798INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1799// Invalid: CountLeadingZeros64 with numOperands = 4
1800INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1801// Invalid: CountLeadingZeros64 with numOperands = 5
1802INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1803// Invalid: CountLeadingZeros64 with numOperands = 6
1804INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1805// Invalid: ConvertDoubleToFloat with numOperands = 0
1806
1807// Invalid: ConvertDoubleToFloat with numOperands = 1
1808INVALID_INST_FORM,
1809// ConvertDoubleToFloat U:F:64, D:F:32
1810ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1811// Invalid: ConvertDoubleToFloat with numOperands = 3
1812INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1813// Invalid: ConvertDoubleToFloat with numOperands = 4
1814INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1815// Invalid: ConvertDoubleToFloat with numOperands = 5
1816INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1817// Invalid: ConvertDoubleToFloat with numOperands = 6
1818INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1819// Invalid: ConvertFloatToDouble with numOperands = 0
1820
1821// Invalid: ConvertFloatToDouble with numOperands = 1
1822INVALID_INST_FORM,
1823// ConvertFloatToDouble U:F:32, D:F:64
1824ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1825// Invalid: ConvertFloatToDouble with numOperands = 3
1826INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1827// Invalid: ConvertFloatToDouble with numOperands = 4
1828INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1829// Invalid: ConvertFloatToDouble with numOperands = 5
1830INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1831// Invalid: ConvertFloatToDouble with numOperands = 6
1832INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1833// Invalid: Move with numOperands = 0
1834
1835// Invalid: Move with numOperands = 1
1836INVALID_INST_FORM,
1837// Move U:G:Ptr, D:G:Ptr
1838ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
1839// Move U:G:Ptr, D:G:Ptr, S:G:Ptr
1840ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Scratch, GP, POINTER_WIDTH),
1841// Invalid: Move with numOperands = 4
1842INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1843// Invalid: Move with numOperands = 5
1844INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1845// Invalid: Move with numOperands = 6
1846INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1847// Invalid: Swap32 with numOperands = 0
1848
1849// Invalid: Swap32 with numOperands = 1
1850INVALID_INST_FORM,
1851// Swap32 UD:G:32, UD:G:32
1852ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
1853// Invalid: Swap32 with numOperands = 3
1854INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1855// Invalid: Swap32 with numOperands = 4
1856INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1857// Invalid: Swap32 with numOperands = 5
1858INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1859// Invalid: Swap32 with numOperands = 6
1860INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1861// Invalid: Swap64 with numOperands = 0
1862
1863// Invalid: Swap64 with numOperands = 1
1864INVALID_INST_FORM,
1865// Swap64 UD:G:64, UD:G:64
1866ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1867// Invalid: Swap64 with numOperands = 3
1868INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1869// Invalid: Swap64 with numOperands = 4
1870INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1871// Invalid: Swap64 with numOperands = 5
1872INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1873// Invalid: Swap64 with numOperands = 6
1874INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1875// Invalid: Move32 with numOperands = 0
1876
1877// Invalid: Move32 with numOperands = 1
1878INVALID_INST_FORM,
1879// Move32 U:G:32, ZD:G:32
1880ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1881// Move32 U:G:32, ZD:G:32, S:G:32
1882ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32),
1883// Invalid: Move32 with numOperands = 4
1884INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1885// Invalid: Move32 with numOperands = 5
1886INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1887// Invalid: Move32 with numOperands = 6
1888INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1889// Invalid: StoreZero32 with numOperands = 0
1890
1891// StoreZero32 D:G:32
1892ENCODE_INST_FORM(Arg::Def, GP, Width32),
1893// Invalid: StoreZero32 with numOperands = 2
1894INVALID_INST_FORM, INVALID_INST_FORM,
1895// Invalid: StoreZero32 with numOperands = 3
1896INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1897// Invalid: StoreZero32 with numOperands = 4
1898INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1899// Invalid: StoreZero32 with numOperands = 5
1900INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1901// Invalid: StoreZero32 with numOperands = 6
1902INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1903// Invalid: StoreZero64 with numOperands = 0
1904
1905// StoreZero64 D:G:64
1906ENCODE_INST_FORM(Arg::Def, GP, Width64),
1907// Invalid: StoreZero64 with numOperands = 2
1908INVALID_INST_FORM, INVALID_INST_FORM,
1909// Invalid: StoreZero64 with numOperands = 3
1910INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1911// Invalid: StoreZero64 with numOperands = 4
1912INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1913// Invalid: StoreZero64 with numOperands = 5
1914INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1915// Invalid: StoreZero64 with numOperands = 6
1916INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1917// Invalid: SignExtend32ToPtr with numOperands = 0
1918
1919// Invalid: SignExtend32ToPtr with numOperands = 1
1920INVALID_INST_FORM,
1921// SignExtend32ToPtr U:G:32, D:G:Ptr
1922ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
1923// Invalid: SignExtend32ToPtr with numOperands = 3
1924INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1925// Invalid: SignExtend32ToPtr with numOperands = 4
1926INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1927// Invalid: SignExtend32ToPtr with numOperands = 5
1928INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1929// Invalid: SignExtend32ToPtr with numOperands = 6
1930INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1931// Invalid: ZeroExtend8To32 with numOperands = 0
1932
1933// Invalid: ZeroExtend8To32 with numOperands = 1
1934INVALID_INST_FORM,
1935// ZeroExtend8To32 U:G:8, ZD:G:32
1936ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1937// Invalid: ZeroExtend8To32 with numOperands = 3
1938INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1939// Invalid: ZeroExtend8To32 with numOperands = 4
1940INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1941// Invalid: ZeroExtend8To32 with numOperands = 5
1942INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1943// Invalid: ZeroExtend8To32 with numOperands = 6
1944INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1945// Invalid: SignExtend8To32 with numOperands = 0
1946
1947// Invalid: SignExtend8To32 with numOperands = 1
1948INVALID_INST_FORM,
1949// SignExtend8To32 U:G:8, ZD:G:32
1950ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1951// Invalid: SignExtend8To32 with numOperands = 3
1952INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1953// Invalid: SignExtend8To32 with numOperands = 4
1954INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1955// Invalid: SignExtend8To32 with numOperands = 5
1956INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1957// Invalid: SignExtend8To32 with numOperands = 6
1958INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1959// Invalid: ZeroExtend16To32 with numOperands = 0
1960
1961// Invalid: ZeroExtend16To32 with numOperands = 1
1962INVALID_INST_FORM,
1963// ZeroExtend16To32 U:G:16, ZD:G:32
1964ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1965// Invalid: ZeroExtend16To32 with numOperands = 3
1966INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1967// Invalid: ZeroExtend16To32 with numOperands = 4
1968INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1969// Invalid: ZeroExtend16To32 with numOperands = 5
1970INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1971// Invalid: ZeroExtend16To32 with numOperands = 6
1972INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1973// Invalid: SignExtend16To32 with numOperands = 0
1974
1975// Invalid: SignExtend16To32 with numOperands = 1
1976INVALID_INST_FORM,
1977// SignExtend16To32 U:G:16, ZD:G:32
1978ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1979// Invalid: SignExtend16To32 with numOperands = 3
1980INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1981// Invalid: SignExtend16To32 with numOperands = 4
1982INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1983// Invalid: SignExtend16To32 with numOperands = 5
1984INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1985// Invalid: SignExtend16To32 with numOperands = 6
1986INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1987// Invalid: MoveFloat with numOperands = 0
1988
1989// Invalid: MoveFloat with numOperands = 1
1990INVALID_INST_FORM,
1991// MoveFloat U:F:32, D:F:32
1992ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1993// MoveFloat U:F:32, D:F:32, S:F:32
1994ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32), ENCODE_INST_FORM(Arg::Scratch, FP, Width32),
1995// Invalid: MoveFloat with numOperands = 4
1996INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1997// Invalid: MoveFloat with numOperands = 5
1998INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1999// Invalid: MoveFloat with numOperands = 6
2000INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2001// Invalid: MoveDouble with numOperands = 0
2002
2003// Invalid: MoveDouble with numOperands = 1
2004INVALID_INST_FORM,
2005// MoveDouble U:F:64, D:F:64
2006ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
2007// MoveDouble U:F:64, D:F:64, S:F:64
2008ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64), ENCODE_INST_FORM(Arg::Scratch, FP, Width64),
2009// Invalid: MoveDouble with numOperands = 4
2010INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2011// Invalid: MoveDouble with numOperands = 5
2012INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2013// Invalid: MoveDouble with numOperands = 6
2014INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2015// Invalid: MoveZeroToDouble with numOperands = 0
2016
2017// MoveZeroToDouble D:F:64
2018ENCODE_INST_FORM(Arg::Def, FP, Width64),
2019// Invalid: MoveZeroToDouble with numOperands = 2
2020INVALID_INST_FORM, INVALID_INST_FORM,
2021// Invalid: MoveZeroToDouble with numOperands = 3
2022INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2023// Invalid: MoveZeroToDouble with numOperands = 4
2024INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2025// Invalid: MoveZeroToDouble with numOperands = 5
2026INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2027// Invalid: MoveZeroToDouble with numOperands = 6
2028INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2029// Invalid: Move64ToDouble with numOperands = 0
2030
2031// Invalid: Move64ToDouble with numOperands = 1
2032INVALID_INST_FORM,
2033// Move64ToDouble U:G:64, D:F:64
2034ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
2035// Invalid: Move64ToDouble with numOperands = 3
2036INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2037// Invalid: Move64ToDouble with numOperands = 4
2038INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2039// Invalid: Move64ToDouble with numOperands = 5
2040INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2041// Invalid: Move64ToDouble with numOperands = 6
2042INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2043// Invalid: Move32ToFloat with numOperands = 0
2044
2045// Invalid: Move32ToFloat with numOperands = 1
2046INVALID_INST_FORM,
2047// Move32ToFloat U:G:32, D:F:32
2048ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
2049// Invalid: Move32ToFloat with numOperands = 3
2050INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2051// Invalid: Move32ToFloat with numOperands = 4
2052INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2053// Invalid: Move32ToFloat with numOperands = 5
2054INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2055// Invalid: Move32ToFloat with numOperands = 6
2056INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2057// Invalid: MoveDoubleTo64 with numOperands = 0
2058
2059// Invalid: MoveDoubleTo64 with numOperands = 1
2060INVALID_INST_FORM,
2061// MoveDoubleTo64 U:F:64, D:G:64
2062ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
2063// Invalid: MoveDoubleTo64 with numOperands = 3
2064INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2065// Invalid: MoveDoubleTo64 with numOperands = 4
2066INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2067// Invalid: MoveDoubleTo64 with numOperands = 5
2068INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2069// Invalid: MoveDoubleTo64 with numOperands = 6
2070INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2071// Invalid: MoveFloatTo32 with numOperands = 0
2072
2073// Invalid: MoveFloatTo32 with numOperands = 1
2074INVALID_INST_FORM,
2075// MoveFloatTo32 U:F:32, D:G:32
2076ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
2077// Invalid: MoveFloatTo32 with numOperands = 3
2078INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2079// Invalid: MoveFloatTo32 with numOperands = 4
2080INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2081// Invalid: MoveFloatTo32 with numOperands = 5
2082INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2083// Invalid: MoveFloatTo32 with numOperands = 6
2084INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2085// Invalid: Load8 with numOperands = 0
2086
2087// Invalid: Load8 with numOperands = 1
2088INVALID_INST_FORM,
2089// Load8 U:G:8, ZD:G:32
2090ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2091// Invalid: Load8 with numOperands = 3
2092INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2093// Invalid: Load8 with numOperands = 4
2094INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2095// Invalid: Load8 with numOperands = 5
2096INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2097// Invalid: Load8 with numOperands = 6
2098INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2099// Invalid: LoadAcq8 with numOperands = 0
2100
2101// Invalid: LoadAcq8 with numOperands = 1
2102INVALID_INST_FORM,
2103// LoadAcq8 U:G:8, ZD:G:32
2104ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2105// Invalid: LoadAcq8 with numOperands = 3
2106INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2107// Invalid: LoadAcq8 with numOperands = 4
2108INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2109// Invalid: LoadAcq8 with numOperands = 5
2110INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2111// Invalid: LoadAcq8 with numOperands = 6
2112INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2113// Invalid: Store8 with numOperands = 0
2114
2115// Invalid: Store8 with numOperands = 1
2116INVALID_INST_FORM,
2117// Store8 U:G:8, D:G:8
2118ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8),
2119// Invalid: Store8 with numOperands = 3
2120INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2121// Invalid: Store8 with numOperands = 4
2122INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2123// Invalid: Store8 with numOperands = 5
2124INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2125// Invalid: Store8 with numOperands = 6
2126INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2127// Invalid: StoreRel8 with numOperands = 0
2128
2129// Invalid: StoreRel8 with numOperands = 1
2130INVALID_INST_FORM,
2131// StoreRel8 U:G:8, D:G:8
2132ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8),
2133// Invalid: StoreRel8 with numOperands = 3
2134INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2135// Invalid: StoreRel8 with numOperands = 4
2136INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2137// Invalid: StoreRel8 with numOperands = 5
2138INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2139// Invalid: StoreRel8 with numOperands = 6
2140INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2141// Invalid: Load8SignedExtendTo32 with numOperands = 0
2142
2143// Invalid: Load8SignedExtendTo32 with numOperands = 1
2144INVALID_INST_FORM,
2145// Load8SignedExtendTo32 U:G:8, ZD:G:32
2146ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2147// Invalid: Load8SignedExtendTo32 with numOperands = 3
2148INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2149// Invalid: Load8SignedExtendTo32 with numOperands = 4
2150INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2151// Invalid: Load8SignedExtendTo32 with numOperands = 5
2152INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2153// Invalid: Load8SignedExtendTo32 with numOperands = 6
2154INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2155// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 0
2156
2157// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 1
2158INVALID_INST_FORM,
2159// LoadAcq8SignedExtendTo32 U:G:8, ZD:G:32
2160ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2161// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 3
2162INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2163// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 4
2164INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2165// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 5
2166INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2167// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 6
2168INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2169// Invalid: Load16 with numOperands = 0
2170
2171// Invalid: Load16 with numOperands = 1
2172INVALID_INST_FORM,
2173// Load16 U:G:16, ZD:G:32
2174ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2175// Invalid: Load16 with numOperands = 3
2176INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2177// Invalid: Load16 with numOperands = 4
2178INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2179// Invalid: Load16 with numOperands = 5
2180INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2181// Invalid: Load16 with numOperands = 6
2182INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2183// Invalid: LoadAcq16 with numOperands = 0
2184
2185// Invalid: LoadAcq16 with numOperands = 1
2186INVALID_INST_FORM,
2187// LoadAcq16 U:G:16, ZD:G:32
2188ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2189// Invalid: LoadAcq16 with numOperands = 3
2190INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2191// Invalid: LoadAcq16 with numOperands = 4
2192INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2193// Invalid: LoadAcq16 with numOperands = 5
2194INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2195// Invalid: LoadAcq16 with numOperands = 6
2196INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2197// Invalid: Load16SignedExtendTo32 with numOperands = 0
2198
2199// Invalid: Load16SignedExtendTo32 with numOperands = 1
2200INVALID_INST_FORM,
2201// Load16SignedExtendTo32 U:G:16, ZD:G:32
2202ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2203// Invalid: Load16SignedExtendTo32 with numOperands = 3
2204INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2205// Invalid: Load16SignedExtendTo32 with numOperands = 4
2206INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2207// Invalid: Load16SignedExtendTo32 with numOperands = 5
2208INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2209// Invalid: Load16SignedExtendTo32 with numOperands = 6
2210INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2211// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 0
2212
2213// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 1
2214INVALID_INST_FORM,
2215// LoadAcq16SignedExtendTo32 U:G:16, ZD:G:32
2216ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2217// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 3
2218INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2219// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 4
2220INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2221// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 5
2222INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2223// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 6
2224INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2225// Invalid: Store16 with numOperands = 0
2226
2227// Invalid: Store16 with numOperands = 1
2228INVALID_INST_FORM,
2229// Store16 U:G:16, D:G:16
2230ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16),
2231// Invalid: Store16 with numOperands = 3
2232INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2233// Invalid: Store16 with numOperands = 4
2234INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2235// Invalid: Store16 with numOperands = 5
2236INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2237// Invalid: Store16 with numOperands = 6
2238INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2239// Invalid: StoreRel16 with numOperands = 0
2240
2241// Invalid: StoreRel16 with numOperands = 1
2242INVALID_INST_FORM,
2243// StoreRel16 U:G:16, D:G:16
2244ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16),
2245// Invalid: StoreRel16 with numOperands = 3
2246INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2247// Invalid: StoreRel16 with numOperands = 4
2248INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2249// Invalid: StoreRel16 with numOperands = 5
2250INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2251// Invalid: StoreRel16 with numOperands = 6
2252INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2253// Invalid: LoadAcq32 with numOperands = 0
2254
2255// Invalid: LoadAcq32 with numOperands = 1
2256INVALID_INST_FORM,
2257// LoadAcq32 U:G:32, ZD:G:32
2258ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2259// Invalid: LoadAcq32 with numOperands = 3
2260INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2261// Invalid: LoadAcq32 with numOperands = 4
2262INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2263// Invalid: LoadAcq32 with numOperands = 5
2264INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2265// Invalid: LoadAcq32 with numOperands = 6
2266INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2267// Invalid: StoreRel32 with numOperands = 0
2268
2269// Invalid: StoreRel32 with numOperands = 1
2270INVALID_INST_FORM,
2271// StoreRel32 U:G:32, ZD:G:32
2272ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2273// Invalid: StoreRel32 with numOperands = 3
2274INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2275// Invalid: StoreRel32 with numOperands = 4
2276INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2277// Invalid: StoreRel32 with numOperands = 5
2278INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2279// Invalid: StoreRel32 with numOperands = 6
2280INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2281// Invalid: LoadAcq64 with numOperands = 0
2282
2283// Invalid: LoadAcq64 with numOperands = 1
2284INVALID_INST_FORM,
2285// LoadAcq64 U:G:64, ZD:G:64
2286ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
2287// Invalid: LoadAcq64 with numOperands = 3
2288INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2289// Invalid: LoadAcq64 with numOperands = 4
2290INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2291// Invalid: LoadAcq64 with numOperands = 5
2292INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2293// Invalid: LoadAcq64 with numOperands = 6
2294INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2295// Invalid: StoreRel64 with numOperands = 0
2296
2297// Invalid: StoreRel64 with numOperands = 1
2298INVALID_INST_FORM,
2299// StoreRel64 U:G:64, ZD:G:64
2300ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
2301// Invalid: StoreRel64 with numOperands = 3
2302INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2303// Invalid: StoreRel64 with numOperands = 4
2304INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2305// Invalid: StoreRel64 with numOperands = 5
2306INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2307// Invalid: StoreRel64 with numOperands = 6
2308INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2309// Invalid: Xchg8 with numOperands = 0
2310
2311// Invalid: Xchg8 with numOperands = 1
2312INVALID_INST_FORM,
2313// Xchg8 UD:G:8, UD:G:8
2314ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2315// Invalid: Xchg8 with numOperands = 3
2316INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2317// Invalid: Xchg8 with numOperands = 4
2318INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2319// Invalid: Xchg8 with numOperands = 5
2320INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2321// Invalid: Xchg8 with numOperands = 6
2322INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2323// Invalid: Xchg16 with numOperands = 0
2324
2325// Invalid: Xchg16 with numOperands = 1
2326INVALID_INST_FORM,
2327// Xchg16 UD:G:16, UD:G:16
2328ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2329// Invalid: Xchg16 with numOperands = 3
2330INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2331// Invalid: Xchg16 with numOperands = 4
2332INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2333// Invalid: Xchg16 with numOperands = 5
2334INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2335// Invalid: Xchg16 with numOperands = 6
2336INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2337// Invalid: Xchg32 with numOperands = 0
2338
2339// Invalid: Xchg32 with numOperands = 1
2340INVALID_INST_FORM,
2341// Xchg32 UD:G:32, UD:G:32
2342ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2343// Invalid: Xchg32 with numOperands = 3
2344INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2345// Invalid: Xchg32 with numOperands = 4
2346INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2347// Invalid: Xchg32 with numOperands = 5
2348INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2349// Invalid: Xchg32 with numOperands = 6
2350INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2351// Invalid: Xchg64 with numOperands = 0
2352
2353// Invalid: Xchg64 with numOperands = 1
2354INVALID_INST_FORM,
2355// Xchg64 UD:G:64, UD:G:64
2356ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2357// Invalid: Xchg64 with numOperands = 3
2358INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2359// Invalid: Xchg64 with numOperands = 4
2360INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2361// Invalid: Xchg64 with numOperands = 5
2362INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2363// Invalid: Xchg64 with numOperands = 6
2364INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2365// Invalid: AtomicStrongCAS8 with numOperands = 0
2366
2367// Invalid: AtomicStrongCAS8 with numOperands = 1
2368INVALID_INST_FORM,
2369// Invalid: AtomicStrongCAS8 with numOperands = 2
2370INVALID_INST_FORM, INVALID_INST_FORM,
2371// AtomicStrongCAS8 UD:G:8, U:G:8, UD:G:8
2372ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2373// Invalid: AtomicStrongCAS8 with numOperands = 4
2374INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2375// AtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8, ZD:G:8
2376ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2377// Invalid: AtomicStrongCAS8 with numOperands = 6
2378INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2379// Invalid: AtomicStrongCAS16 with numOperands = 0
2380
2381// Invalid: AtomicStrongCAS16 with numOperands = 1
2382INVALID_INST_FORM,
2383// Invalid: AtomicStrongCAS16 with numOperands = 2
2384INVALID_INST_FORM, INVALID_INST_FORM,
2385// AtomicStrongCAS16 UD:G:16, U:G:32, UD:G:16
2386ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2387// Invalid: AtomicStrongCAS16 with numOperands = 4
2388INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2389// AtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16, ZD:G:8
2390ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2391// Invalid: AtomicStrongCAS16 with numOperands = 6
2392INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2393// Invalid: AtomicStrongCAS32 with numOperands = 0
2394
2395// Invalid: AtomicStrongCAS32 with numOperands = 1
2396INVALID_INST_FORM,
2397// Invalid: AtomicStrongCAS32 with numOperands = 2
2398INVALID_INST_FORM, INVALID_INST_FORM,
2399// AtomicStrongCAS32 UD:G:32, U:G:32, UD:G:32
2400ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2401// Invalid: AtomicStrongCAS32 with numOperands = 4
2402INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2403// AtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32, ZD:G:8
2404ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2405// Invalid: AtomicStrongCAS32 with numOperands = 6
2406INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2407// Invalid: AtomicStrongCAS64 with numOperands = 0
2408
2409// Invalid: AtomicStrongCAS64 with numOperands = 1
2410INVALID_INST_FORM,
2411// Invalid: AtomicStrongCAS64 with numOperands = 2
2412INVALID_INST_FORM, INVALID_INST_FORM,
2413// AtomicStrongCAS64 UD:G:64, U:G:64, UD:G:64
2414ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2415// Invalid: AtomicStrongCAS64 with numOperands = 4
2416INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2417// AtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64, ZD:G:8
2418ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2419// Invalid: AtomicStrongCAS64 with numOperands = 6
2420INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2421// Invalid: BranchAtomicStrongCAS8 with numOperands = 0
2422
2423// Invalid: BranchAtomicStrongCAS8 with numOperands = 1
2424INVALID_INST_FORM,
2425// Invalid: BranchAtomicStrongCAS8 with numOperands = 2
2426INVALID_INST_FORM, INVALID_INST_FORM,
2427// Invalid: BranchAtomicStrongCAS8 with numOperands = 3
2428INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2429// BranchAtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8
2430ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2431// Invalid: BranchAtomicStrongCAS8 with numOperands = 5
2432INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2433// Invalid: BranchAtomicStrongCAS8 with numOperands = 6
2434INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2435// Invalid: BranchAtomicStrongCAS16 with numOperands = 0
2436
2437// Invalid: BranchAtomicStrongCAS16 with numOperands = 1
2438INVALID_INST_FORM,
2439// Invalid: BranchAtomicStrongCAS16 with numOperands = 2
2440INVALID_INST_FORM, INVALID_INST_FORM,
2441// Invalid: BranchAtomicStrongCAS16 with numOperands = 3
2442INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2443// BranchAtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16
2444ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2445// Invalid: BranchAtomicStrongCAS16 with numOperands = 5
2446INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2447// Invalid: BranchAtomicStrongCAS16 with numOperands = 6
2448INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2449// Invalid: BranchAtomicStrongCAS32 with numOperands = 0
2450
2451// Invalid: BranchAtomicStrongCAS32 with numOperands = 1
2452INVALID_INST_FORM,
2453// Invalid: BranchAtomicStrongCAS32 with numOperands = 2
2454INVALID_INST_FORM, INVALID_INST_FORM,
2455// Invalid: BranchAtomicStrongCAS32 with numOperands = 3
2456INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2457// BranchAtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32
2458ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2459// Invalid: BranchAtomicStrongCAS32 with numOperands = 5
2460INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2461// Invalid: BranchAtomicStrongCAS32 with numOperands = 6
2462INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2463// Invalid: BranchAtomicStrongCAS64 with numOperands = 0
2464
2465// Invalid: BranchAtomicStrongCAS64 with numOperands = 1
2466INVALID_INST_FORM,
2467// Invalid: BranchAtomicStrongCAS64 with numOperands = 2
2468INVALID_INST_FORM, INVALID_INST_FORM,
2469// Invalid: BranchAtomicStrongCAS64 with numOperands = 3
2470INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2471// BranchAtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64
2472ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2473// Invalid: BranchAtomicStrongCAS64 with numOperands = 5
2474INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2475// Invalid: BranchAtomicStrongCAS64 with numOperands = 6
2476INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2477// Invalid: AtomicAdd8 with numOperands = 0
2478
2479// Invalid: AtomicAdd8 with numOperands = 1
2480INVALID_INST_FORM,
2481// AtomicAdd8 U:G:8, UD:G:8
2482ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2483// Invalid: AtomicAdd8 with numOperands = 3
2484INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2485// Invalid: AtomicAdd8 with numOperands = 4
2486INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2487// Invalid: AtomicAdd8 with numOperands = 5
2488INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2489// Invalid: AtomicAdd8 with numOperands = 6
2490INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2491// Invalid: AtomicAdd16 with numOperands = 0
2492
2493// Invalid: AtomicAdd16 with numOperands = 1
2494INVALID_INST_FORM,
2495// AtomicAdd16 U:G:16, UD:G:16
2496ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2497// Invalid: AtomicAdd16 with numOperands = 3
2498INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2499// Invalid: AtomicAdd16 with numOperands = 4
2500INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2501// Invalid: AtomicAdd16 with numOperands = 5
2502INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2503// Invalid: AtomicAdd16 with numOperands = 6
2504INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2505// Invalid: AtomicAdd32 with numOperands = 0
2506
2507// Invalid: AtomicAdd32 with numOperands = 1
2508INVALID_INST_FORM,
2509// AtomicAdd32 U:G:32, UD:G:32
2510ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2511// Invalid: AtomicAdd32 with numOperands = 3
2512INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2513// Invalid: AtomicAdd32 with numOperands = 4
2514INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2515// Invalid: AtomicAdd32 with numOperands = 5
2516INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2517// Invalid: AtomicAdd32 with numOperands = 6
2518INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2519// Invalid: AtomicAdd64 with numOperands = 0
2520
2521// Invalid: AtomicAdd64 with numOperands = 1
2522INVALID_INST_FORM,
2523// AtomicAdd64 U:G:64, UD:G:64
2524ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2525// Invalid: AtomicAdd64 with numOperands = 3
2526INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2527// Invalid: AtomicAdd64 with numOperands = 4
2528INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2529// Invalid: AtomicAdd64 with numOperands = 5
2530INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2531// Invalid: AtomicAdd64 with numOperands = 6
2532INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2533// Invalid: AtomicSub8 with numOperands = 0
2534
2535// Invalid: AtomicSub8 with numOperands = 1
2536INVALID_INST_FORM,
2537// AtomicSub8 U:G:8, UD:G:8
2538ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2539// Invalid: AtomicSub8 with numOperands = 3
2540INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2541// Invalid: AtomicSub8 with numOperands = 4
2542INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2543// Invalid: AtomicSub8 with numOperands = 5
2544INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2545// Invalid: AtomicSub8 with numOperands = 6
2546INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2547// Invalid: AtomicSub16 with numOperands = 0
2548
2549// Invalid: AtomicSub16 with numOperands = 1
2550INVALID_INST_FORM,
2551// AtomicSub16 U:G:16, UD:G:16
2552ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2553// Invalid: AtomicSub16 with numOperands = 3
2554INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2555// Invalid: AtomicSub16 with numOperands = 4
2556INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2557// Invalid: AtomicSub16 with numOperands = 5
2558INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2559// Invalid: AtomicSub16 with numOperands = 6
2560INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2561// Invalid: AtomicSub32 with numOperands = 0
2562
2563// Invalid: AtomicSub32 with numOperands = 1
2564INVALID_INST_FORM,
2565// AtomicSub32 U:G:32, UD:G:32
2566ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2567// Invalid: AtomicSub32 with numOperands = 3
2568INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2569// Invalid: AtomicSub32 with numOperands = 4
2570INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2571// Invalid: AtomicSub32 with numOperands = 5
2572INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2573// Invalid: AtomicSub32 with numOperands = 6
2574INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2575// Invalid: AtomicSub64 with numOperands = 0
2576
2577// Invalid: AtomicSub64 with numOperands = 1
2578INVALID_INST_FORM,
2579// AtomicSub64 U:G:64, UD:G:64
2580ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2581// Invalid: AtomicSub64 with numOperands = 3
2582INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2583// Invalid: AtomicSub64 with numOperands = 4
2584INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2585// Invalid: AtomicSub64 with numOperands = 5
2586INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2587// Invalid: AtomicSub64 with numOperands = 6
2588INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2589// Invalid: AtomicAnd8 with numOperands = 0
2590
2591// Invalid: AtomicAnd8 with numOperands = 1
2592INVALID_INST_FORM,
2593// AtomicAnd8 U:G:8, UD:G:8
2594ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2595// Invalid: AtomicAnd8 with numOperands = 3
2596INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2597// Invalid: AtomicAnd8 with numOperands = 4
2598INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2599// Invalid: AtomicAnd8 with numOperands = 5
2600INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2601// Invalid: AtomicAnd8 with numOperands = 6
2602INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2603// Invalid: AtomicAnd16 with numOperands = 0
2604
2605// Invalid: AtomicAnd16 with numOperands = 1
2606INVALID_INST_FORM,
2607// AtomicAnd16 U:G:16, UD:G:16
2608ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2609// Invalid: AtomicAnd16 with numOperands = 3
2610INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2611// Invalid: AtomicAnd16 with numOperands = 4
2612INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2613// Invalid: AtomicAnd16 with numOperands = 5
2614INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2615// Invalid: AtomicAnd16 with numOperands = 6
2616INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2617// Invalid: AtomicAnd32 with numOperands = 0
2618
2619// Invalid: AtomicAnd32 with numOperands = 1
2620INVALID_INST_FORM,
2621// AtomicAnd32 U:G:32, UD:G:32
2622ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2623// Invalid: AtomicAnd32 with numOperands = 3
2624INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2625// Invalid: AtomicAnd32 with numOperands = 4
2626INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2627// Invalid: AtomicAnd32 with numOperands = 5
2628INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2629// Invalid: AtomicAnd32 with numOperands = 6
2630INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2631// Invalid: AtomicAnd64 with numOperands = 0
2632
2633// Invalid: AtomicAnd64 with numOperands = 1
2634INVALID_INST_FORM,
2635// AtomicAnd64 U:G:64, UD:G:64
2636ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2637// Invalid: AtomicAnd64 with numOperands = 3
2638INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2639// Invalid: AtomicAnd64 with numOperands = 4
2640INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2641// Invalid: AtomicAnd64 with numOperands = 5
2642INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2643// Invalid: AtomicAnd64 with numOperands = 6
2644INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2645// Invalid: AtomicOr8 with numOperands = 0
2646
2647// Invalid: AtomicOr8 with numOperands = 1
2648INVALID_INST_FORM,
2649// AtomicOr8 U:G:8, UD:G:8
2650ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2651// Invalid: AtomicOr8 with numOperands = 3
2652INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2653// Invalid: AtomicOr8 with numOperands = 4
2654INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2655// Invalid: AtomicOr8 with numOperands = 5
2656INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2657// Invalid: AtomicOr8 with numOperands = 6
2658INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2659// Invalid: AtomicOr16 with numOperands = 0
2660
2661// Invalid: AtomicOr16 with numOperands = 1
2662INVALID_INST_FORM,
2663// AtomicOr16 U:G:16, UD:G:16
2664ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2665// Invalid: AtomicOr16 with numOperands = 3
2666INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2667// Invalid: AtomicOr16 with numOperands = 4
2668INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2669// Invalid: AtomicOr16 with numOperands = 5
2670INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2671// Invalid: AtomicOr16 with numOperands = 6
2672INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2673// Invalid: AtomicOr32 with numOperands = 0
2674
2675// Invalid: AtomicOr32 with numOperands = 1
2676INVALID_INST_FORM,
2677// AtomicOr32 U:G:32, UD:G:32
2678ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2679// Invalid: AtomicOr32 with numOperands = 3
2680INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2681// Invalid: AtomicOr32 with numOperands = 4
2682INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2683// Invalid: AtomicOr32 with numOperands = 5
2684INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2685// Invalid: AtomicOr32 with numOperands = 6
2686INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2687// Invalid: AtomicOr64 with numOperands = 0
2688
2689// Invalid: AtomicOr64 with numOperands = 1
2690INVALID_INST_FORM,
2691// AtomicOr64 U:G:64, UD:G:64
2692ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2693// Invalid: AtomicOr64 with numOperands = 3
2694INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2695// Invalid: AtomicOr64 with numOperands = 4
2696INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2697// Invalid: AtomicOr64 with numOperands = 5
2698INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2699// Invalid: AtomicOr64 with numOperands = 6
2700INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2701// Invalid: AtomicXor8 with numOperands = 0
2702
2703// Invalid: AtomicXor8 with numOperands = 1
2704INVALID_INST_FORM,
2705// AtomicXor8 U:G:8, UD:G:8
2706ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2707// Invalid: AtomicXor8 with numOperands = 3
2708INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2709// Invalid: AtomicXor8 with numOperands = 4
2710INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2711// Invalid: AtomicXor8 with numOperands = 5
2712INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2713// Invalid: AtomicXor8 with numOperands = 6
2714INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2715// Invalid: AtomicXor16 with numOperands = 0
2716
2717// Invalid: AtomicXor16 with numOperands = 1
2718INVALID_INST_FORM,
2719// AtomicXor16 U:G:16, UD:G:16
2720ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2721// Invalid: AtomicXor16 with numOperands = 3
2722INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2723// Invalid: AtomicXor16 with numOperands = 4
2724INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2725// Invalid: AtomicXor16 with numOperands = 5
2726INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2727// Invalid: AtomicXor16 with numOperands = 6
2728INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2729// Invalid: AtomicXor32 with numOperands = 0
2730
2731// Invalid: AtomicXor32 with numOperands = 1
2732INVALID_INST_FORM,
2733// AtomicXor32 U:G:32, UD:G:32
2734ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2735// Invalid: AtomicXor32 with numOperands = 3
2736INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2737// Invalid: AtomicXor32 with numOperands = 4
2738INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2739// Invalid: AtomicXor32 with numOperands = 5
2740INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2741// Invalid: AtomicXor32 with numOperands = 6
2742INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2743// Invalid: AtomicXor64 with numOperands = 0
2744
2745// Invalid: AtomicXor64 with numOperands = 1
2746INVALID_INST_FORM,
2747// AtomicXor64 U:G:64, UD:G:64
2748ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2749// Invalid: AtomicXor64 with numOperands = 3
2750INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2751// Invalid: AtomicXor64 with numOperands = 4
2752INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2753// Invalid: AtomicXor64 with numOperands = 5
2754INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2755// Invalid: AtomicXor64 with numOperands = 6
2756INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2757// Invalid: AtomicNeg8 with numOperands = 0
2758
2759// AtomicNeg8 UD:G:8
2760ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2761// Invalid: AtomicNeg8 with numOperands = 2
2762INVALID_INST_FORM, INVALID_INST_FORM,
2763// Invalid: AtomicNeg8 with numOperands = 3
2764INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2765// Invalid: AtomicNeg8 with numOperands = 4
2766INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2767// Invalid: AtomicNeg8 with numOperands = 5
2768INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2769// Invalid: AtomicNeg8 with numOperands = 6
2770INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2771// Invalid: AtomicNeg16 with numOperands = 0
2772
2773// AtomicNeg16 UD:G:16
2774ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2775// Invalid: AtomicNeg16 with numOperands = 2
2776INVALID_INST_FORM, INVALID_INST_FORM,
2777// Invalid: AtomicNeg16 with numOperands = 3
2778INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2779// Invalid: AtomicNeg16 with numOperands = 4
2780INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2781// Invalid: AtomicNeg16 with numOperands = 5
2782INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2783// Invalid: AtomicNeg16 with numOperands = 6
2784INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2785// Invalid: AtomicNeg32 with numOperands = 0
2786
2787// AtomicNeg32 UD:G:32
2788ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2789// Invalid: AtomicNeg32 with numOperands = 2
2790INVALID_INST_FORM, INVALID_INST_FORM,
2791// Invalid: AtomicNeg32 with numOperands = 3
2792INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2793// Invalid: AtomicNeg32 with numOperands = 4
2794INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2795// Invalid: AtomicNeg32 with numOperands = 5
2796INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2797// Invalid: AtomicNeg32 with numOperands = 6
2798INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2799// Invalid: AtomicNeg64 with numOperands = 0
2800
2801// AtomicNeg64 UD:G:64
2802ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2803// Invalid: AtomicNeg64 with numOperands = 2
2804INVALID_INST_FORM, INVALID_INST_FORM,
2805// Invalid: AtomicNeg64 with numOperands = 3
2806INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2807// Invalid: AtomicNeg64 with numOperands = 4
2808INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2809// Invalid: AtomicNeg64 with numOperands = 5
2810INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2811// Invalid: AtomicNeg64 with numOperands = 6
2812INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2813// Invalid: AtomicNot8 with numOperands = 0
2814
2815// AtomicNot8 UD:G:8
2816ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2817// Invalid: AtomicNot8 with numOperands = 2
2818INVALID_INST_FORM, INVALID_INST_FORM,
2819// Invalid: AtomicNot8 with numOperands = 3
2820INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2821// Invalid: AtomicNot8 with numOperands = 4
2822INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2823// Invalid: AtomicNot8 with numOperands = 5
2824INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2825// Invalid: AtomicNot8 with numOperands = 6
2826INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2827// Invalid: AtomicNot16 with numOperands = 0
2828
2829// AtomicNot16 UD:G:16
2830ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2831// Invalid: AtomicNot16 with numOperands = 2
2832INVALID_INST_FORM, INVALID_INST_FORM,
2833// Invalid: AtomicNot16 with numOperands = 3
2834INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2835// Invalid: AtomicNot16 with numOperands = 4
2836INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2837// Invalid: AtomicNot16 with numOperands = 5
2838INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2839// Invalid: AtomicNot16 with numOperands = 6
2840INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2841// Invalid: AtomicNot32 with numOperands = 0
2842
2843// AtomicNot32 UD:G:32
2844ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2845// Invalid: AtomicNot32 with numOperands = 2
2846INVALID_INST_FORM, INVALID_INST_FORM,
2847// Invalid: AtomicNot32 with numOperands = 3
2848INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2849// Invalid: AtomicNot32 with numOperands = 4
2850INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2851// Invalid: AtomicNot32 with numOperands = 5
2852INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2853// Invalid: AtomicNot32 with numOperands = 6
2854INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2855// Invalid: AtomicNot64 with numOperands = 0
2856
2857// AtomicNot64 UD:G:64
2858ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2859// Invalid: AtomicNot64 with numOperands = 2
2860INVALID_INST_FORM, INVALID_INST_FORM,
2861// Invalid: AtomicNot64 with numOperands = 3
2862INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2863// Invalid: AtomicNot64 with numOperands = 4
2864INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2865// Invalid: AtomicNot64 with numOperands = 5
2866INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2867// Invalid: AtomicNot64 with numOperands = 6
2868INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2869// Invalid: AtomicXchgAdd8 with numOperands = 0
2870
2871// Invalid: AtomicXchgAdd8 with numOperands = 1
2872INVALID_INST_FORM,
2873// AtomicXchgAdd8 UD:G:8, UD:G:8
2874ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2875// Invalid: AtomicXchgAdd8 with numOperands = 3
2876INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2877// Invalid: AtomicXchgAdd8 with numOperands = 4
2878INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2879// Invalid: AtomicXchgAdd8 with numOperands = 5
2880INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2881// Invalid: AtomicXchgAdd8 with numOperands = 6
2882INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2883// Invalid: AtomicXchgAdd16 with numOperands = 0
2884
2885// Invalid: AtomicXchgAdd16 with numOperands = 1
2886INVALID_INST_FORM,
2887// AtomicXchgAdd16 UD:G:16, UD:G:16
2888ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2889// Invalid: AtomicXchgAdd16 with numOperands = 3
2890INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2891// Invalid: AtomicXchgAdd16 with numOperands = 4
2892INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2893// Invalid: AtomicXchgAdd16 with numOperands = 5
2894INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2895// Invalid: AtomicXchgAdd16 with numOperands = 6
2896INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2897// Invalid: AtomicXchgAdd32 with numOperands = 0
2898
2899// Invalid: AtomicXchgAdd32 with numOperands = 1
2900INVALID_INST_FORM,
2901// AtomicXchgAdd32 UD:G:32, UD:G:32
2902ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2903// Invalid: AtomicXchgAdd32 with numOperands = 3
2904INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2905// Invalid: AtomicXchgAdd32 with numOperands = 4
2906INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2907// Invalid: AtomicXchgAdd32 with numOperands = 5
2908INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2909// Invalid: AtomicXchgAdd32 with numOperands = 6
2910INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2911// Invalid: AtomicXchgAdd64 with numOperands = 0
2912
2913// Invalid: AtomicXchgAdd64 with numOperands = 1
2914INVALID_INST_FORM,
2915// AtomicXchgAdd64 UD:G:64, UD:G:64
2916ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2917// Invalid: AtomicXchgAdd64 with numOperands = 3
2918INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2919// Invalid: AtomicXchgAdd64 with numOperands = 4
2920INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2921// Invalid: AtomicXchgAdd64 with numOperands = 5
2922INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2923// Invalid: AtomicXchgAdd64 with numOperands = 6
2924INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2925// Invalid: AtomicXchg8 with numOperands = 0
2926
2927// Invalid: AtomicXchg8 with numOperands = 1
2928INVALID_INST_FORM,
2929// AtomicXchg8 UD:G:8, UD:G:8
2930ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2931// Invalid: AtomicXchg8 with numOperands = 3
2932INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2933// Invalid: AtomicXchg8 with numOperands = 4
2934INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2935// Invalid: AtomicXchg8 with numOperands = 5
2936INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2937// Invalid: AtomicXchg8 with numOperands = 6
2938INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2939// Invalid: AtomicXchg16 with numOperands = 0
2940
2941// Invalid: AtomicXchg16 with numOperands = 1
2942INVALID_INST_FORM,
2943// AtomicXchg16 UD:G:16, UD:G:16
2944ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2945// Invalid: AtomicXchg16 with numOperands = 3
2946INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2947// Invalid: AtomicXchg16 with numOperands = 4
2948INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2949// Invalid: AtomicXchg16 with numOperands = 5
2950INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2951// Invalid: AtomicXchg16 with numOperands = 6
2952INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2953// Invalid: AtomicXchg32 with numOperands = 0
2954
2955// Invalid: AtomicXchg32 with numOperands = 1
2956INVALID_INST_FORM,
2957// AtomicXchg32 UD:G:32, UD:G:32
2958ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2959// Invalid: AtomicXchg32 with numOperands = 3
2960INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2961// Invalid: AtomicXchg32 with numOperands = 4
2962INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2963// Invalid: AtomicXchg32 with numOperands = 5
2964INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2965// Invalid: AtomicXchg32 with numOperands = 6
2966INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2967// Invalid: AtomicXchg64 with numOperands = 0
2968
2969// Invalid: AtomicXchg64 with numOperands = 1
2970INVALID_INST_FORM,
2971// AtomicXchg64 UD:G:64, UD:G:64
2972ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2973// Invalid: AtomicXchg64 with numOperands = 3
2974INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2975// Invalid: AtomicXchg64 with numOperands = 4
2976INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2977// Invalid: AtomicXchg64 with numOperands = 5
2978INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2979// Invalid: AtomicXchg64 with numOperands = 6
2980INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2981// Invalid: LoadLink8 with numOperands = 0
2982
2983// Invalid: LoadLink8 with numOperands = 1
2984INVALID_INST_FORM,
2985// LoadLink8 U:G:8, ZD:G:8
2986ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2987// Invalid: LoadLink8 with numOperands = 3
2988INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2989// Invalid: LoadLink8 with numOperands = 4
2990INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2991// Invalid: LoadLink8 with numOperands = 5
2992INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2993// Invalid: LoadLink8 with numOperands = 6
2994INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2995// Invalid: LoadLinkAcq8 with numOperands = 0
2996
2997// Invalid: LoadLinkAcq8 with numOperands = 1
2998INVALID_INST_FORM,
2999// LoadLinkAcq8 U:G:8, ZD:G:8
3000ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
3001// Invalid: LoadLinkAcq8 with numOperands = 3
3002INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3003// Invalid: LoadLinkAcq8 with numOperands = 4
3004INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3005// Invalid: LoadLinkAcq8 with numOperands = 5
3006INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3007// Invalid: LoadLinkAcq8 with numOperands = 6
3008INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3009// Invalid: StoreCond8 with numOperands = 0
3010
3011// Invalid: StoreCond8 with numOperands = 1
3012INVALID_INST_FORM,
3013// Invalid: StoreCond8 with numOperands = 2
3014INVALID_INST_FORM, INVALID_INST_FORM,
3015// StoreCond8 U:G:8, D:G:8, EZD:G:8
3016ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3017// Invalid: StoreCond8 with numOperands = 4
3018INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3019// Invalid: StoreCond8 with numOperands = 5
3020INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3021// Invalid: StoreCond8 with numOperands = 6
3022INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3023// Invalid: StoreCondRel8 with numOperands = 0
3024
3025// Invalid: StoreCondRel8 with numOperands = 1
3026INVALID_INST_FORM,
3027// Invalid: StoreCondRel8 with numOperands = 2
3028INVALID_INST_FORM, INVALID_INST_FORM,
3029// StoreCondRel8 U:G:8, D:G:8, EZD:G:8
3030ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3031// Invalid: StoreCondRel8 with numOperands = 4
3032INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3033// Invalid: StoreCondRel8 with numOperands = 5
3034INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3035// Invalid: StoreCondRel8 with numOperands = 6
3036INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3037// Invalid: LoadLink16 with numOperands = 0
3038
3039// Invalid: LoadLink16 with numOperands = 1
3040INVALID_INST_FORM,
3041// LoadLink16 U:G:16, ZD:G:16
3042ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width16),
3043// Invalid: LoadLink16 with numOperands = 3
3044INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3045// Invalid: LoadLink16 with numOperands = 4
3046INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3047// Invalid: LoadLink16 with numOperands = 5
3048INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3049// Invalid: LoadLink16 with numOperands = 6
3050INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3051// Invalid: LoadLinkAcq16 with numOperands = 0
3052
3053// Invalid: LoadLinkAcq16 with numOperands = 1
3054INVALID_INST_FORM,
3055// LoadLinkAcq16 U:G:16, ZD:G:16
3056ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width16),
3057// Invalid: LoadLinkAcq16 with numOperands = 3
3058INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3059// Invalid: LoadLinkAcq16 with numOperands = 4
3060INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3061// Invalid: LoadLinkAcq16 with numOperands = 5
3062INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3063// Invalid: LoadLinkAcq16 with numOperands = 6
3064INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3065// Invalid: StoreCond16 with numOperands = 0
3066
3067// Invalid: StoreCond16 with numOperands = 1
3068INVALID_INST_FORM,
3069// Invalid: StoreCond16 with numOperands = 2
3070INVALID_INST_FORM, INVALID_INST_FORM,
3071// StoreCond16 U:G:16, D:G:16, EZD:G:8
3072ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3073// Invalid: StoreCond16 with numOperands = 4
3074INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3075// Invalid: StoreCond16 with numOperands = 5
3076INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3077// Invalid: StoreCond16 with numOperands = 6
3078INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3079// Invalid: StoreCondRel16 with numOperands = 0
3080
3081// Invalid: StoreCondRel16 with numOperands = 1
3082INVALID_INST_FORM,
3083// Invalid: StoreCondRel16 with numOperands = 2
3084INVALID_INST_FORM, INVALID_INST_FORM,
3085// StoreCondRel16 U:G:16, D:G:16, EZD:G:8
3086ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3087// Invalid: StoreCondRel16 with numOperands = 4
3088INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3089// Invalid: StoreCondRel16 with numOperands = 5
3090INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3091// Invalid: StoreCondRel16 with numOperands = 6
3092INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3093// Invalid: LoadLink32 with numOperands = 0
3094
3095// Invalid: LoadLink32 with numOperands = 1
3096INVALID_INST_FORM,
3097// LoadLink32 U:G:32, ZD:G:32
3098ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3099// Invalid: LoadLink32 with numOperands = 3
3100INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3101// Invalid: LoadLink32 with numOperands = 4
3102INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3103// Invalid: LoadLink32 with numOperands = 5
3104INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3105// Invalid: LoadLink32 with numOperands = 6
3106INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3107// Invalid: LoadLinkAcq32 with numOperands = 0
3108
3109// Invalid: LoadLinkAcq32 with numOperands = 1
3110INVALID_INST_FORM,
3111// LoadLinkAcq32 U:G:32, ZD:G:32
3112ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3113// Invalid: LoadLinkAcq32 with numOperands = 3
3114INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3115// Invalid: LoadLinkAcq32 with numOperands = 4
3116INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3117// Invalid: LoadLinkAcq32 with numOperands = 5
3118INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3119// Invalid: LoadLinkAcq32 with numOperands = 6
3120INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3121// Invalid: StoreCond32 with numOperands = 0
3122
3123// Invalid: StoreCond32 with numOperands = 1
3124INVALID_INST_FORM,
3125// Invalid: StoreCond32 with numOperands = 2
3126INVALID_INST_FORM, INVALID_INST_FORM,
3127// StoreCond32 U:G:32, D:G:32, EZD:G:8
3128ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3129// Invalid: StoreCond32 with numOperands = 4
3130INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3131// Invalid: StoreCond32 with numOperands = 5
3132INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3133// Invalid: StoreCond32 with numOperands = 6
3134INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3135// Invalid: StoreCondRel32 with numOperands = 0
3136
3137// Invalid: StoreCondRel32 with numOperands = 1
3138INVALID_INST_FORM,
3139// Invalid: StoreCondRel32 with numOperands = 2
3140INVALID_INST_FORM, INVALID_INST_FORM,
3141// StoreCondRel32 U:G:32, D:G:32, EZD:G:8
3142ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3143// Invalid: StoreCondRel32 with numOperands = 4
3144INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3145// Invalid: StoreCondRel32 with numOperands = 5
3146INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3147// Invalid: StoreCondRel32 with numOperands = 6
3148INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3149// Invalid: LoadLink64 with numOperands = 0
3150
3151// Invalid: LoadLink64 with numOperands = 1
3152INVALID_INST_FORM,
3153// LoadLink64 U:G:64, ZD:G:64
3154ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3155// Invalid: LoadLink64 with numOperands = 3
3156INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3157// Invalid: LoadLink64 with numOperands = 4
3158INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3159// Invalid: LoadLink64 with numOperands = 5
3160INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3161// Invalid: LoadLink64 with numOperands = 6
3162INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3163// Invalid: LoadLinkAcq64 with numOperands = 0
3164
3165// Invalid: LoadLinkAcq64 with numOperands = 1
3166INVALID_INST_FORM,
3167// LoadLinkAcq64 U:G:64, ZD:G:64
3168ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3169// Invalid: LoadLinkAcq64 with numOperands = 3
3170INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3171// Invalid: LoadLinkAcq64 with numOperands = 4
3172INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3173// Invalid: LoadLinkAcq64 with numOperands = 5
3174INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3175// Invalid: LoadLinkAcq64 with numOperands = 6
3176INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3177// Invalid: StoreCond64 with numOperands = 0
3178
3179// Invalid: StoreCond64 with numOperands = 1
3180INVALID_INST_FORM,
3181// Invalid: StoreCond64 with numOperands = 2
3182INVALID_INST_FORM, INVALID_INST_FORM,
3183// StoreCond64 U:G:64, D:G:64, EZD:G:8
3184ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3185// Invalid: StoreCond64 with numOperands = 4
3186INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3187// Invalid: StoreCond64 with numOperands = 5
3188INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3189// Invalid: StoreCond64 with numOperands = 6
3190INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3191// Invalid: StoreCondRel64 with numOperands = 0
3192
3193// Invalid: StoreCondRel64 with numOperands = 1
3194INVALID_INST_FORM,
3195// Invalid: StoreCondRel64 with numOperands = 2
3196INVALID_INST_FORM, INVALID_INST_FORM,
3197// StoreCondRel64 U:G:64, D:G:64, EZD:G:8
3198ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3199// Invalid: StoreCondRel64 with numOperands = 4
3200INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3201// Invalid: StoreCondRel64 with numOperands = 5
3202INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3203// Invalid: StoreCondRel64 with numOperands = 6
3204INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3205// Invalid: Depend32 with numOperands = 0
3206
3207// Invalid: Depend32 with numOperands = 1
3208INVALID_INST_FORM,
3209// Depend32 U:G:32, ZD:G:32
3210ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3211// Invalid: Depend32 with numOperands = 3
3212INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3213// Invalid: Depend32 with numOperands = 4
3214INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3215// Invalid: Depend32 with numOperands = 5
3216INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3217// Invalid: Depend32 with numOperands = 6
3218INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3219// Invalid: Depend64 with numOperands = 0
3220
3221// Invalid: Depend64 with numOperands = 1
3222INVALID_INST_FORM,
3223// Depend64 U:G:64, ZD:G:64
3224ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3225// Invalid: Depend64 with numOperands = 3
3226INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3227// Invalid: Depend64 with numOperands = 4
3228INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3229// Invalid: Depend64 with numOperands = 5
3230INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3231// Invalid: Depend64 with numOperands = 6
3232INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3233// Invalid: Compare32 with numOperands = 0
3234
3235// Invalid: Compare32 with numOperands = 1
3236INVALID_INST_FORM,
3237// Invalid: Compare32 with numOperands = 2
3238INVALID_INST_FORM, INVALID_INST_FORM,
3239// Invalid: Compare32 with numOperands = 3
3240INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3241// Compare32 U:G:32, U:G:32, U:G:32, ZD:G:32
3242ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3243// Invalid: Compare32 with numOperands = 5
3244INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3245// Invalid: Compare32 with numOperands = 6
3246INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3247// Invalid: Compare64 with numOperands = 0
3248
3249// Invalid: Compare64 with numOperands = 1
3250INVALID_INST_FORM,
3251// Invalid: Compare64 with numOperands = 2
3252INVALID_INST_FORM, INVALID_INST_FORM,
3253// Invalid: Compare64 with numOperands = 3
3254INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3255// Compare64 U:G:32, U:G:64, U:G:64, ZD:G:32
3256ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3257// Invalid: Compare64 with numOperands = 5
3258INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3259// Invalid: Compare64 with numOperands = 6
3260INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3261// Invalid: Test32 with numOperands = 0
3262
3263// Invalid: Test32 with numOperands = 1
3264INVALID_INST_FORM,
3265// Invalid: Test32 with numOperands = 2
3266INVALID_INST_FORM, INVALID_INST_FORM,
3267// Invalid: Test32 with numOperands = 3
3268INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3269// Test32 U:G:32, U:G:32, U:G:32, ZD:G:32
3270ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3271// Invalid: Test32 with numOperands = 5
3272INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3273// Invalid: Test32 with numOperands = 6
3274INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3275// Invalid: Test64 with numOperands = 0
3276
3277// Invalid: Test64 with numOperands = 1
3278INVALID_INST_FORM,
3279// Invalid: Test64 with numOperands = 2
3280INVALID_INST_FORM, INVALID_INST_FORM,
3281// Invalid: Test64 with numOperands = 3
3282INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3283// Test64 U:G:32, U:G:64, U:G:64, ZD:G:32
3284ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3285// Invalid: Test64 with numOperands = 5
3286INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3287// Invalid: Test64 with numOperands = 6
3288INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3289// Invalid: CompareDouble with numOperands = 0
3290
3291// Invalid: CompareDouble with numOperands = 1
3292INVALID_INST_FORM,
3293// Invalid: CompareDouble with numOperands = 2
3294INVALID_INST_FORM, INVALID_INST_FORM,
3295// Invalid: CompareDouble with numOperands = 3
3296INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3297// CompareDouble U:G:32, U:F:64, U:F:64, ZD:G:32
3298ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3299// Invalid: CompareDouble with numOperands = 5
3300INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3301// Invalid: CompareDouble with numOperands = 6
3302INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3303// Invalid: CompareFloat with numOperands = 0
3304
3305// Invalid: CompareFloat with numOperands = 1
3306INVALID_INST_FORM,
3307// Invalid: CompareFloat with numOperands = 2
3308INVALID_INST_FORM, INVALID_INST_FORM,
3309// Invalid: CompareFloat with numOperands = 3
3310INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3311// CompareFloat U:G:32, U:F:32, U:F:32, ZD:G:32
3312ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3313// Invalid: CompareFloat with numOperands = 5
3314INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3315// Invalid: CompareFloat with numOperands = 6
3316INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3317// Invalid: Branch8 with numOperands = 0
3318
3319// Invalid: Branch8 with numOperands = 1
3320INVALID_INST_FORM,
3321// Invalid: Branch8 with numOperands = 2
3322INVALID_INST_FORM, INVALID_INST_FORM,
3323// Branch8 U:G:32, U:G:8, U:G:8
3324ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3325// Invalid: Branch8 with numOperands = 4
3326INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3327// Invalid: Branch8 with numOperands = 5
3328INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3329// Invalid: Branch8 with numOperands = 6
3330INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3331// Invalid: Branch32 with numOperands = 0
3332
3333// Invalid: Branch32 with numOperands = 1
3334INVALID_INST_FORM,
3335// Invalid: Branch32 with numOperands = 2
3336INVALID_INST_FORM, INVALID_INST_FORM,
3337// Branch32 U:G:32, U:G:32, U:G:32
3338ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
3339// Invalid: Branch32 with numOperands = 4
3340INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3341// Invalid: Branch32 with numOperands = 5
3342INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3343// Invalid: Branch32 with numOperands = 6
3344INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3345// Invalid: Branch64 with numOperands = 0
3346
3347// Invalid: Branch64 with numOperands = 1
3348INVALID_INST_FORM,
3349// Invalid: Branch64 with numOperands = 2
3350INVALID_INST_FORM, INVALID_INST_FORM,
3351// Branch64 U:G:32, U:G:64, U:G:64
3352ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
3353// Invalid: Branch64 with numOperands = 4
3354INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3355// Invalid: Branch64 with numOperands = 5
3356INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3357// Invalid: Branch64 with numOperands = 6
3358INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3359// Invalid: BranchTest8 with numOperands = 0
3360
3361// Invalid: BranchTest8 with numOperands = 1
3362INVALID_INST_FORM,
3363// Invalid: BranchTest8 with numOperands = 2
3364INVALID_INST_FORM, INVALID_INST_FORM,
3365// BranchTest8 U:G:32, U:G:8, U:G:8
3366ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3367// Invalid: BranchTest8 with numOperands = 4
3368INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3369// Invalid: BranchTest8 with numOperands = 5
3370INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3371// Invalid: BranchTest8 with numOperands = 6
3372INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3373// Invalid: BranchTest32 with numOperands = 0
3374
3375// Invalid: BranchTest32 with numOperands = 1
3376INVALID_INST_FORM,
3377// Invalid: BranchTest32 with numOperands = 2
3378INVALID_INST_FORM, INVALID_INST_FORM,
3379// BranchTest32 U:G:32, U:G:32, U:G:32
3380ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
3381// Invalid: BranchTest32 with numOperands = 4
3382INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3383// Invalid: BranchTest32 with numOperands = 5
3384INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3385// Invalid: BranchTest32 with numOperands = 6
3386INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3387// Invalid: BranchTest64 with numOperands = 0
3388
3389// Invalid: BranchTest64 with numOperands = 1
3390INVALID_INST_FORM,
3391// Invalid: BranchTest64 with numOperands = 2
3392INVALID_INST_FORM, INVALID_INST_FORM,
3393// BranchTest64 U:G:32, U:G:64, U:G:64
3394ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
3395// Invalid: BranchTest64 with numOperands = 4
3396INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3397// Invalid: BranchTest64 with numOperands = 5
3398INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3399// Invalid: BranchTest64 with numOperands = 6
3400INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3401// Invalid: BranchTestBit64 with numOperands = 0
3402
3403// Invalid: BranchTestBit64 with numOperands = 1
3404INVALID_INST_FORM,
3405// Invalid: BranchTestBit64 with numOperands = 2
3406INVALID_INST_FORM, INVALID_INST_FORM,
3407// BranchTestBit64 U:G:32, U:G:64, U:G:8
3408ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3409// Invalid: BranchTestBit64 with numOperands = 4
3410INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3411// Invalid: BranchTestBit64 with numOperands = 5
3412INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3413// Invalid: BranchTestBit64 with numOperands = 6
3414INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3415// Invalid: BranchTestBit32 with numOperands = 0
3416
3417// Invalid: BranchTestBit32 with numOperands = 1
3418INVALID_INST_FORM,
3419// Invalid: BranchTestBit32 with numOperands = 2
3420INVALID_INST_FORM, INVALID_INST_FORM,
3421// BranchTestBit32 U:G:32, U:G:32, U:G:8
3422ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3423// Invalid: BranchTestBit32 with numOperands = 4
3424INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3425// Invalid: BranchTestBit32 with numOperands = 5
3426INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3427// Invalid: BranchTestBit32 with numOperands = 6
3428INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3429// Invalid: BranchDouble with numOperands = 0
3430
3431// Invalid: BranchDouble with numOperands = 1
3432INVALID_INST_FORM,
3433// Invalid: BranchDouble with numOperands = 2
3434INVALID_INST_FORM, INVALID_INST_FORM,
3435// BranchDouble U:G:32, U:F:64, U:F:64
3436ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64),
3437// Invalid: BranchDouble with numOperands = 4
3438INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3439// Invalid: BranchDouble with numOperands = 5
3440INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3441// Invalid: BranchDouble with numOperands = 6
3442INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3443// Invalid: BranchFloat with numOperands = 0
3444
3445// Invalid: BranchFloat with numOperands = 1
3446INVALID_INST_FORM,
3447// Invalid: BranchFloat with numOperands = 2
3448INVALID_INST_FORM, INVALID_INST_FORM,
3449// BranchFloat U:G:32, U:F:32, U:F:32
3450ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32),
3451// Invalid: BranchFloat with numOperands = 4
3452INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3453// Invalid: BranchFloat with numOperands = 5
3454INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3455// Invalid: BranchFloat with numOperands = 6
3456INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3457// Invalid: BranchAdd32 with numOperands = 0
3458
3459// Invalid: BranchAdd32 with numOperands = 1
3460INVALID_INST_FORM,
3461// Invalid: BranchAdd32 with numOperands = 2
3462INVALID_INST_FORM, INVALID_INST_FORM,
3463// BranchAdd32 U:G:32, U:G:32, UZD:G:32
3464ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3465// BranchAdd32 U:G:32, U:G:32, U:G:32, ZD:G:32
3466ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3467// Invalid: BranchAdd32 with numOperands = 5
3468INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3469// Invalid: BranchAdd32 with numOperands = 6
3470INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3471// Invalid: BranchAdd64 with numOperands = 0
3472
3473// Invalid: BranchAdd64 with numOperands = 1
3474INVALID_INST_FORM,
3475// Invalid: BranchAdd64 with numOperands = 2
3476INVALID_INST_FORM, INVALID_INST_FORM,
3477// BranchAdd64 U:G:32, U:G:64, UD:G:64
3478ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
3479// BranchAdd64 U:G:32, U:G:64, U:G:64, ZD:G:64
3480ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3481// Invalid: BranchAdd64 with numOperands = 5
3482INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3483// Invalid: BranchAdd64 with numOperands = 6
3484INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3485// Invalid: BranchMul32 with numOperands = 0
3486
3487// Invalid: BranchMul32 with numOperands = 1
3488INVALID_INST_FORM,
3489// Invalid: BranchMul32 with numOperands = 2
3490INVALID_INST_FORM, INVALID_INST_FORM,
3491// BranchMul32 U:G:32, U:G:32, UZD:G:32
3492ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3493// BranchMul32 U:G:32, U:G:32, U:G:32, ZD:G:32
3494ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3495// Invalid: BranchMul32 with numOperands = 5
3496INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3497// BranchMul32 U:G:32, U:G:32, U:G:32, S:G:32, S:G:32, ZD:G:32
3498ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3499// Invalid: BranchMul64 with numOperands = 0
3500
3501// Invalid: BranchMul64 with numOperands = 1
3502INVALID_INST_FORM,
3503// Invalid: BranchMul64 with numOperands = 2
3504INVALID_INST_FORM, INVALID_INST_FORM,
3505// BranchMul64 U:G:32, U:G:64, UZD:G:64
3506ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64),
3507// Invalid: BranchMul64 with numOperands = 4
3508INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3509// Invalid: BranchMul64 with numOperands = 5
3510INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3511// BranchMul64 U:G:32, U:G:64, U:G:64, S:G:64, S:G:64, ZD:G:64
3512ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Scratch, GP, Width64), ENCODE_INST_FORM(Arg::Scratch, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3513// Invalid: BranchSub32 with numOperands = 0
3514
3515// Invalid: BranchSub32 with numOperands = 1
3516INVALID_INST_FORM,
3517// Invalid: BranchSub32 with numOperands = 2
3518INVALID_INST_FORM, INVALID_INST_FORM,
3519// BranchSub32 U:G:32, U:G:32, UZD:G:32
3520ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3521// Invalid: BranchSub32 with numOperands = 4
3522INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3523// Invalid: BranchSub32 with numOperands = 5
3524INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3525// Invalid: BranchSub32 with numOperands = 6
3526INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3527// Invalid: BranchSub64 with numOperands = 0
3528
3529// Invalid: BranchSub64 with numOperands = 1
3530INVALID_INST_FORM,
3531// Invalid: BranchSub64 with numOperands = 2
3532INVALID_INST_FORM, INVALID_INST_FORM,
3533// BranchSub64 U:G:32, U:G:64, UD:G:64
3534ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
3535// Invalid: BranchSub64 with numOperands = 4
3536INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3537// Invalid: BranchSub64 with numOperands = 5
3538INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3539// Invalid: BranchSub64 with numOperands = 6
3540INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3541// Invalid: BranchNeg32 with numOperands = 0
3542
3543// Invalid: BranchNeg32 with numOperands = 1
3544INVALID_INST_FORM,
3545// BranchNeg32 U:G:32, UZD:G:32
3546ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3547// Invalid: BranchNeg32 with numOperands = 3
3548INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3549// Invalid: BranchNeg32 with numOperands = 4
3550INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3551// Invalid: BranchNeg32 with numOperands = 5
3552INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3553// Invalid: BranchNeg32 with numOperands = 6
3554INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3555// Invalid: BranchNeg64 with numOperands = 0
3556
3557// Invalid: BranchNeg64 with numOperands = 1
3558INVALID_INST_FORM,
3559// BranchNeg64 U:G:32, UZD:G:64
3560ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64),
3561// Invalid: BranchNeg64 with numOperands = 3
3562INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3563// Invalid: BranchNeg64 with numOperands = 4
3564INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3565// Invalid: BranchNeg64 with numOperands = 5
3566INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3567// Invalid: BranchNeg64 with numOperands = 6
3568INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3569// Invalid: MoveConditionally32 with numOperands = 0
3570
3571// Invalid: MoveConditionally32 with numOperands = 1
3572INVALID_INST_FORM,
3573// Invalid: MoveConditionally32 with numOperands = 2
3574INVALID_INST_FORM, INVALID_INST_FORM,
3575// Invalid: MoveConditionally32 with numOperands = 3
3576INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3577// Invalid: MoveConditionally32 with numOperands = 4
3578INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3579// MoveConditionally32 U:G:32, U:G:32, U:G:32, U:G:Ptr, UD:G:Ptr
3580ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3581// MoveConditionally32 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3582ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3583// Invalid: MoveConditionally64 with numOperands = 0
3584
3585// Invalid: MoveConditionally64 with numOperands = 1
3586INVALID_INST_FORM,
3587// Invalid: MoveConditionally64 with numOperands = 2
3588INVALID_INST_FORM, INVALID_INST_FORM,
3589// Invalid: MoveConditionally64 with numOperands = 3
3590INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3591// Invalid: MoveConditionally64 with numOperands = 4
3592INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3593// MoveConditionally64 U:G:32, U:G:64, U:G:64, U:G:Ptr, UD:G:Ptr
3594ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3595// MoveConditionally64 U:G:32, U:G:64, U:G:64, U:G:Ptr, U:G:Ptr, D:G:Ptr
3596ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3597// Invalid: MoveConditionallyTest32 with numOperands = 0
3598
3599// Invalid: MoveConditionallyTest32 with numOperands = 1
3600INVALID_INST_FORM,
3601// Invalid: MoveConditionallyTest32 with numOperands = 2
3602INVALID_INST_FORM, INVALID_INST_FORM,
3603// Invalid: MoveConditionallyTest32 with numOperands = 3
3604INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3605// Invalid: MoveConditionallyTest32 with numOperands = 4
3606INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3607// MoveConditionallyTest32 U:G:32, U:G:32, U:G:32, U:G:Ptr, UD:G:Ptr
3608ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3609// MoveConditionallyTest32 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3610ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3611// Invalid: MoveConditionallyTest64 with numOperands = 0
3612
3613// Invalid: MoveConditionallyTest64 with numOperands = 1
3614INVALID_INST_FORM,
3615// Invalid: MoveConditionallyTest64 with numOperands = 2
3616INVALID_INST_FORM, INVALID_INST_FORM,
3617// Invalid: MoveConditionallyTest64 with numOperands = 3
3618INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3619// Invalid: MoveConditionallyTest64 with numOperands = 4
3620INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3621// MoveConditionallyTest64 U:G:32, U:G:64, U:G:64, U:G:Ptr, UD:G:Ptr
3622ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3623// MoveConditionallyTest64 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3624ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3625// Invalid: MoveConditionallyDouble with numOperands = 0
3626
3627// Invalid: MoveConditionallyDouble with numOperands = 1
3628INVALID_INST_FORM,
3629// Invalid: MoveConditionallyDouble with numOperands = 2
3630INVALID_INST_FORM, INVALID_INST_FORM,
3631// Invalid: MoveConditionallyDouble with numOperands = 3
3632INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3633// Invalid: MoveConditionallyDouble with numOperands = 4
3634INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3635// MoveConditionallyDouble U:G:32, U:F:64, U:F:64, U:G:Ptr, UD:G:Ptr
3636ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3637// MoveConditionallyDouble U:G:32, U:F:64, U:F:64, U:G:Ptr, U:G:Ptr, D:G:Ptr
3638ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3639// Invalid: MoveConditionallyFloat with numOperands = 0
3640
3641// Invalid: MoveConditionallyFloat with numOperands = 1
3642INVALID_INST_FORM,
3643// Invalid: MoveConditionallyFloat with numOperands = 2
3644INVALID_INST_FORM, INVALID_INST_FORM,
3645// Invalid: MoveConditionallyFloat with numOperands = 3
3646INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3647// Invalid: MoveConditionallyFloat with numOperands = 4
3648INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3649// MoveConditionallyFloat U:G:32, U:F:32, U:F:32, U:G:Ptr, UD:G:Ptr
3650ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3651// MoveConditionallyFloat U:G:32, U:F:32, U:F:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3652ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3653// Invalid: MoveDoubleConditionally32 with numOperands = 0
3654
3655// Invalid: MoveDoubleConditionally32 with numOperands = 1
3656INVALID_INST_FORM,
3657// Invalid: MoveDoubleConditionally32 with numOperands = 2
3658INVALID_INST_FORM, INVALID_INST_FORM,
3659// Invalid: MoveDoubleConditionally32 with numOperands = 3
3660INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3661// Invalid: MoveDoubleConditionally32 with numOperands = 4
3662INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3663// Invalid: MoveDoubleConditionally32 with numOperands = 5
3664INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3665// MoveDoubleConditionally32 U:G:32, U:G:32, U:G:32, U:F:64, U:F:64, D:F:64
3666ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3667// Invalid: MoveDoubleConditionally64 with numOperands = 0
3668
3669// Invalid: MoveDoubleConditionally64 with numOperands = 1
3670INVALID_INST_FORM,
3671// Invalid: MoveDoubleConditionally64 with numOperands = 2
3672INVALID_INST_FORM, INVALID_INST_FORM,
3673// Invalid: MoveDoubleConditionally64 with numOperands = 3
3674INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3675// Invalid: MoveDoubleConditionally64 with numOperands = 4
3676INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3677// Invalid: MoveDoubleConditionally64 with numOperands = 5
3678INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3679// MoveDoubleConditionally64 U:G:32, U:G:64, U:G:64, U:F:64, U:F:64, D:F:64
3680ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3681// Invalid: MoveDoubleConditionallyTest32 with numOperands = 0
3682
3683// Invalid: MoveDoubleConditionallyTest32 with numOperands = 1
3684INVALID_INST_FORM,
3685// Invalid: MoveDoubleConditionallyTest32 with numOperands = 2
3686INVALID_INST_FORM, INVALID_INST_FORM,
3687// Invalid: MoveDoubleConditionallyTest32 with numOperands = 3
3688INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3689// Invalid: MoveDoubleConditionallyTest32 with numOperands = 4
3690INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3691// Invalid: MoveDoubleConditionallyTest32 with numOperands = 5
3692INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3693// MoveDoubleConditionallyTest32 U:G:32, U:G:32, U:G:32, U:F:64, U:F:64, D:F:64
3694ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3695// Invalid: MoveDoubleConditionallyTest64 with numOperands = 0
3696
3697// Invalid: MoveDoubleConditionallyTest64 with numOperands = 1
3698INVALID_INST_FORM,
3699// Invalid: MoveDoubleConditionallyTest64 with numOperands = 2
3700INVALID_INST_FORM, INVALID_INST_FORM,
3701// Invalid: MoveDoubleConditionallyTest64 with numOperands = 3
3702INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3703// Invalid: MoveDoubleConditionallyTest64 with numOperands = 4
3704INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3705// Invalid: MoveDoubleConditionallyTest64 with numOperands = 5
3706INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3707// MoveDoubleConditionallyTest64 U:G:32, U:G:64, U:G:64, U:F:64, U:F:64, D:F:64
3708ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3709// Invalid: MoveDoubleConditionallyDouble with numOperands = 0
3710
3711// Invalid: MoveDoubleConditionallyDouble with numOperands = 1
3712INVALID_INST_FORM,
3713// Invalid: MoveDoubleConditionallyDouble with numOperands = 2
3714INVALID_INST_FORM, INVALID_INST_FORM,
3715// Invalid: MoveDoubleConditionallyDouble with numOperands = 3
3716INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3717// Invalid: MoveDoubleConditionallyDouble with numOperands = 4
3718INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3719// Invalid: MoveDoubleConditionallyDouble with numOperands = 5
3720INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3721// MoveDoubleConditionallyDouble U:G:32, U:F:64, U:F:64, U:F:64, U:F:64, D:F:64
3722ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3723// Invalid: MoveDoubleConditionallyFloat with numOperands = 0
3724
3725// Invalid: MoveDoubleConditionallyFloat with numOperands = 1
3726INVALID_INST_FORM,
3727// Invalid: MoveDoubleConditionallyFloat with numOperands = 2
3728INVALID_INST_FORM, INVALID_INST_FORM,
3729// Invalid: MoveDoubleConditionallyFloat with numOperands = 3
3730INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3731// Invalid: MoveDoubleConditionallyFloat with numOperands = 4
3732INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3733// Invalid: MoveDoubleConditionallyFloat with numOperands = 5
3734INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3735// MoveDoubleConditionallyFloat U:G:32, U:F:32, U:F:32, U:F:64, U:F:64, D:F:64
3736ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3737// MemoryFence
3738
3739// Invalid: MemoryFence with numOperands = 1
3740INVALID_INST_FORM,
3741// Invalid: MemoryFence with numOperands = 2
3742INVALID_INST_FORM, INVALID_INST_FORM,
3743// Invalid: MemoryFence with numOperands = 3
3744INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3745// Invalid: MemoryFence with numOperands = 4
3746INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3747// Invalid: MemoryFence with numOperands = 5
3748INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3749// Invalid: MemoryFence with numOperands = 6
3750INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3751// StoreFence
3752
3753// Invalid: StoreFence with numOperands = 1
3754INVALID_INST_FORM,
3755// Invalid: StoreFence with numOperands = 2
3756INVALID_INST_FORM, INVALID_INST_FORM,
3757// Invalid: StoreFence with numOperands = 3
3758INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3759// Invalid: StoreFence with numOperands = 4
3760INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3761// Invalid: StoreFence with numOperands = 5
3762INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3763// Invalid: StoreFence with numOperands = 6
3764INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3765// LoadFence
3766
3767// Invalid: LoadFence with numOperands = 1
3768INVALID_INST_FORM,
3769// Invalid: LoadFence with numOperands = 2
3770INVALID_INST_FORM, INVALID_INST_FORM,
3771// Invalid: LoadFence with numOperands = 3
3772INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3773// Invalid: LoadFence with numOperands = 4
3774INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3775// Invalid: LoadFence with numOperands = 5
3776INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3777// Invalid: LoadFence with numOperands = 6
3778INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3779// Jump
3780
3781// Invalid: Jump with numOperands = 1
3782INVALID_INST_FORM,
3783// Invalid: Jump with numOperands = 2
3784INVALID_INST_FORM, INVALID_INST_FORM,
3785// Invalid: Jump with numOperands = 3
3786INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3787// Invalid: Jump with numOperands = 4
3788INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3789// Invalid: Jump with numOperands = 5
3790INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3791// Invalid: Jump with numOperands = 6
3792INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3793// RetVoid
3794
3795// Invalid: RetVoid with numOperands = 1
3796INVALID_INST_FORM,
3797// Invalid: RetVoid with numOperands = 2
3798INVALID_INST_FORM, INVALID_INST_FORM,
3799// Invalid: RetVoid with numOperands = 3
3800INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3801// Invalid: RetVoid with numOperands = 4
3802INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3803// Invalid: RetVoid with numOperands = 5
3804INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3805// Invalid: RetVoid with numOperands = 6
3806INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3807// Invalid: Ret32 with numOperands = 0
3808
3809// Ret32 U:G:32
3810ENCODE_INST_FORM(Arg::Use, GP, Width32),
3811// Invalid: Ret32 with numOperands = 2
3812INVALID_INST_FORM, INVALID_INST_FORM,
3813// Invalid: Ret32 with numOperands = 3
3814INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3815// Invalid: Ret32 with numOperands = 4
3816INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3817// Invalid: Ret32 with numOperands = 5
3818INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3819// Invalid: Ret32 with numOperands = 6
3820INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3821// Invalid: Ret64 with numOperands = 0
3822
3823// Ret64 U:G:64
3824ENCODE_INST_FORM(Arg::Use, GP, Width64),
3825// Invalid: Ret64 with numOperands = 2
3826INVALID_INST_FORM, INVALID_INST_FORM,
3827// Invalid: Ret64 with numOperands = 3
3828INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3829// Invalid: Ret64 with numOperands = 4
3830INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3831// Invalid: Ret64 with numOperands = 5
3832INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3833// Invalid: Ret64 with numOperands = 6
3834INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3835// Invalid: RetFloat with numOperands = 0
3836
3837// RetFloat U:F:32
3838ENCODE_INST_FORM(Arg::Use, FP, Width32),
3839// Invalid: RetFloat with numOperands = 2
3840INVALID_INST_FORM, INVALID_INST_FORM,
3841// Invalid: RetFloat with numOperands = 3
3842INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3843// Invalid: RetFloat with numOperands = 4
3844INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3845// Invalid: RetFloat with numOperands = 5
3846INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3847// Invalid: RetFloat with numOperands = 6
3848INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3849// Invalid: RetDouble with numOperands = 0
3850
3851// RetDouble U:F:64
3852ENCODE_INST_FORM(Arg::Use, FP, Width64),
3853// Invalid: RetDouble with numOperands = 2
3854INVALID_INST_FORM, INVALID_INST_FORM,
3855// Invalid: RetDouble with numOperands = 3
3856INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3857// Invalid: RetDouble with numOperands = 4
3858INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3859// Invalid: RetDouble with numOperands = 5
3860INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3861// Invalid: RetDouble with numOperands = 6
3862INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3863// Oops
3864
3865// Invalid: Oops with numOperands = 1
3866INVALID_INST_FORM,
3867// Invalid: Oops with numOperands = 2
3868INVALID_INST_FORM, INVALID_INST_FORM,
3869// Invalid: Oops with numOperands = 3
3870INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3871// Invalid: Oops with numOperands = 4
3872INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3873// Invalid: Oops with numOperands = 5
3874INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3875// Invalid: Oops with numOperands = 6
3876INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3877// Invalid: EntrySwitch with numOperands = 0
3878
3879// Invalid: EntrySwitch with numOperands = 1
3880INVALID_INST_FORM,
3881// Invalid: EntrySwitch with numOperands = 2
3882INVALID_INST_FORM, INVALID_INST_FORM,
3883// Invalid: EntrySwitch with numOperands = 3
3884INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3885// Invalid: EntrySwitch with numOperands = 4
3886INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3887// Invalid: EntrySwitch with numOperands = 5
3888INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3889// Invalid: EntrySwitch with numOperands = 6
3890INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3891// Invalid: Shuffle with numOperands = 0
3892
3893// Invalid: Shuffle with numOperands = 1
3894INVALID_INST_FORM,
3895// Invalid: Shuffle with numOperands = 2
3896INVALID_INST_FORM, INVALID_INST_FORM,
3897// Invalid: Shuffle with numOperands = 3
3898INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3899// Invalid: Shuffle with numOperands = 4
3900INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3901// Invalid: Shuffle with numOperands = 5
3902INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3903// Invalid: Shuffle with numOperands = 6
3904INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3905// Invalid: Patch with numOperands = 0
3906
3907// Invalid: Patch with numOperands = 1
3908INVALID_INST_FORM,
3909// Invalid: Patch with numOperands = 2
3910INVALID_INST_FORM, INVALID_INST_FORM,
3911// Invalid: Patch with numOperands = 3
3912INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3913// Invalid: Patch with numOperands = 4
3914INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3915// Invalid: Patch with numOperands = 5
3916INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3917// Invalid: Patch with numOperands = 6
3918INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3919// Invalid: CCall with numOperands = 0
3920
3921// Invalid: CCall with numOperands = 1
3922INVALID_INST_FORM,
3923// Invalid: CCall with numOperands = 2
3924INVALID_INST_FORM, INVALID_INST_FORM,
3925// Invalid: CCall with numOperands = 3
3926INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3927// Invalid: CCall with numOperands = 4
3928INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3929// Invalid: CCall with numOperands = 5
3930INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3931// Invalid: CCall with numOperands = 6
3932INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3933// Invalid: ColdCCall with numOperands = 0
3934
3935// Invalid: ColdCCall with numOperands = 1
3936INVALID_INST_FORM,
3937// Invalid: ColdCCall with numOperands = 2
3938INVALID_INST_FORM, INVALID_INST_FORM,
3939// Invalid: ColdCCall with numOperands = 3
3940INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3941// Invalid: ColdCCall with numOperands = 4
3942INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3943// Invalid: ColdCCall with numOperands = 5
3944INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3945// Invalid: ColdCCall with numOperands = 6
3946INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3947// Invalid: WasmBoundsCheck with numOperands = 0
3948
3949// Invalid: WasmBoundsCheck with numOperands = 1
3950INVALID_INST_FORM,
3951// Invalid: WasmBoundsCheck with numOperands = 2
3952INVALID_INST_FORM, INVALID_INST_FORM,
3953// Invalid: WasmBoundsCheck with numOperands = 3
3954INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3955// Invalid: WasmBoundsCheck with numOperands = 4
3956INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3957// Invalid: WasmBoundsCheck with numOperands = 5
3958INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3959// Invalid: WasmBoundsCheck with numOperands = 6
3960INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3961};
3962void Inst::forEachArgCustom(ScopedLambda<EachArgCallback> lambda)
3963{
3964switch (kind.opcode) {
3965case Opcode::EntrySwitch:
3966EntrySwitchCustom::forEachArg(*this, lambda);
3967break;
3968case Opcode::Shuffle:
3969ShuffleCustom::forEachArg(*this, lambda);
3970break;
3971case Opcode::Patch:
3972PatchCustom::forEachArg(*this, lambda);
3973break;
3974case Opcode::CCall:
3975CCallCustom::forEachArg(*this, lambda);
3976break;
3977case Opcode::ColdCCall:
3978ColdCCallCustom::forEachArg(*this, lambda);
3979break;
3980case Opcode::WasmBoundsCheck:
3981WasmBoundsCheckCustom::forEachArg(*this, lambda);
3982break;
3983default:
3984dataLog("Bad call to forEachArgCustom, not custom opcode: ", kind, "\n");
3985RELEASE_ASSERT_NOT_REACHED();
3986}
3987}
3988bool Inst::isValidForm()
3989{
3990switch (this->kind.opcode) {
3991case Opcode::Nop:
3992switch (this->args.size()) {
3993case 0:
3994OPGEN_RETURN(true);
3995break;
3996break;
3997default:
3998break;
3999}
4000break;
4001case Opcode::Add32:
4002switch (this->args.size()) {
4003case 3:
4004switch (this->args[0].kind()) {
4005case Arg::Imm:
4006switch (this->args[1].kind()) {
4007case Arg::Tmp:
4008switch (this->args[2].kind()) {
4009case Arg::Tmp:
4010if (!Arg::isValidImmForm(args[0].value()))
4011OPGEN_RETURN(false);
4012if (!args[1].tmp().isGP())
4013OPGEN_RETURN(false);
4014if (!args[2].tmp().isGP())
4015OPGEN_RETURN(false);
4016OPGEN_RETURN(true);
4017break;
4018break;
4019default:
4020break;
4021}
4022break;
4023default:
4024break;
4025}
4026break;
4027case Arg::Tmp:
4028switch (this->args[1].kind()) {
4029case Arg::Tmp:
4030switch (this->args[2].kind()) {
4031case Arg::Tmp:
4032if (!args[0].tmp().isGP())
4033OPGEN_RETURN(false);
4034if (!args[1].tmp().isGP())
4035OPGEN_RETURN(false);
4036if (!args[2].tmp().isGP())
4037OPGEN_RETURN(false);
4038OPGEN_RETURN(true);
4039break;
4040break;
4041default:
4042break;
4043}
4044break;
4045default:
4046break;
4047}
4048break;
4049default:
4050break;
4051}
4052break;
4053case 2:
4054switch (this->args[0].kind()) {
4055case Arg::Tmp:
4056switch (this->args[1].kind()) {
4057case Arg::Tmp:
4058if (!args[0].tmp().isGP())
4059OPGEN_RETURN(false);
4060if (!args[1].tmp().isGP())
4061OPGEN_RETURN(false);
4062OPGEN_RETURN(true);
4063break;
4064break;
4065case Arg::Addr:
4066case Arg::Stack:
4067case Arg::CallArg:
4068#if CPU(X86) || CPU(X86_64)
4069if (!args[0].tmp().isGP())
4070OPGEN_RETURN(false);
4071if (!Arg::isValidAddrForm(args[1].offset()))
4072OPGEN_RETURN(false);
4073OPGEN_RETURN(true);
4074#endif
4075break;
4076break;
4077case Arg::Index:
4078#if CPU(X86) || CPU(X86_64)
4079if (!args[0].tmp().isGP())
4080OPGEN_RETURN(false);
4081if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4082OPGEN_RETURN(false);
4083OPGEN_RETURN(true);
4084#endif
4085break;
4086break;
4087default:
4088break;
4089}
4090break;
4091case Arg::Imm:
4092switch (this->args[1].kind()) {
4093case Arg::Addr:
4094case Arg::Stack:
4095case Arg::CallArg:
4096#if CPU(X86) || CPU(X86_64)
4097if (!Arg::isValidImmForm(args[0].value()))
4098OPGEN_RETURN(false);
4099if (!Arg::isValidAddrForm(args[1].offset()))
4100OPGEN_RETURN(false);
4101OPGEN_RETURN(true);
4102#endif
4103break;
4104break;
4105case Arg::Index:
4106#if CPU(X86) || CPU(X86_64)
4107if (!Arg::isValidImmForm(args[0].value()))
4108OPGEN_RETURN(false);
4109if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4110OPGEN_RETURN(false);
4111OPGEN_RETURN(true);
4112#endif
4113break;
4114break;
4115case Arg::Tmp:
4116if (!Arg::isValidImmForm(args[0].value()))
4117OPGEN_RETURN(false);
4118if (!args[1].tmp().isGP())
4119OPGEN_RETURN(false);
4120OPGEN_RETURN(true);
4121break;
4122break;
4123default:
4124break;
4125}
4126break;
4127case Arg::Addr:
4128case Arg::Stack:
4129case Arg::CallArg:
4130switch (this->args[1].kind()) {
4131case Arg::Tmp:
4132#if CPU(X86) || CPU(X86_64)
4133if (!Arg::isValidAddrForm(args[0].offset()))
4134OPGEN_RETURN(false);
4135if (!args[1].tmp().isGP())
4136OPGEN_RETURN(false);
4137OPGEN_RETURN(true);
4138#endif
4139break;
4140break;
4141default:
4142break;
4143}
4144break;
4145case Arg::Index:
4146switch (this->args[1].kind()) {
4147case Arg::Tmp:
4148#if CPU(X86) || CPU(X86_64)
4149if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4150OPGEN_RETURN(false);
4151if (!args[1].tmp().isGP())
4152OPGEN_RETURN(false);
4153OPGEN_RETURN(true);
4154#endif
4155break;
4156break;
4157default:
4158break;
4159}
4160break;
4161default:
4162break;
4163}
4164break;
4165default:
4166break;
4167}
4168break;
4169case Opcode::Add8:
4170switch (this->args.size()) {
4171case 2:
4172switch (this->args[0].kind()) {
4173case Arg::Imm:
4174switch (this->args[1].kind()) {
4175case Arg::Addr:
4176case Arg::Stack:
4177case Arg::CallArg:
4178#if CPU(X86) || CPU(X86_64)
4179if (!Arg::isValidImmForm(args[0].value()))
4180OPGEN_RETURN(false);
4181if (!Arg::isValidAddrForm(args[1].offset()))
4182OPGEN_RETURN(false);
4183OPGEN_RETURN(true);
4184#endif
4185break;
4186break;
4187case Arg::Index:
4188#if CPU(X86) || CPU(X86_64)
4189if (!Arg::isValidImmForm(args[0].value()))
4190OPGEN_RETURN(false);
4191if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
4192OPGEN_RETURN(false);
4193OPGEN_RETURN(true);
4194#endif
4195break;
4196break;
4197default:
4198break;
4199}
4200break;
4201case Arg::Tmp:
4202switch (this->args[1].kind()) {
4203case Arg::Addr:
4204case Arg::Stack:
4205case Arg::CallArg:
4206#if CPU(X86) || CPU(X86_64)
4207if (!args[0].tmp().isGP())
4208OPGEN_RETURN(false);
4209if (!Arg::isValidAddrForm(args[1].offset()))
4210OPGEN_RETURN(false);
4211OPGEN_RETURN(true);
4212#endif
4213break;
4214break;
4215case Arg::Index:
4216#if CPU(X86) || CPU(X86_64)
4217if (!args[0].tmp().isGP())
4218OPGEN_RETURN(false);
4219if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
4220OPGEN_RETURN(false);
4221OPGEN_RETURN(true);
4222#endif
4223break;
4224break;
4225default:
4226break;
4227}
4228break;
4229default:
4230break;
4231}
4232break;
4233default:
4234break;
4235}
4236break;
4237case Opcode::Add16:
4238switch (this->args.size()) {
4239case 2:
4240switch (this->args[0].kind()) {
4241case Arg::Imm:
4242switch (this->args[1].kind()) {
4243case Arg::Addr:
4244case Arg::Stack:
4245case Arg::CallArg:
4246#if CPU(X86) || CPU(X86_64)
4247if (!Arg::isValidImmForm(args[0].value()))
4248OPGEN_RETURN(false);
4249if (!Arg::isValidAddrForm(args[1].offset()))
4250OPGEN_RETURN(false);
4251OPGEN_RETURN(true);
4252#endif
4253break;
4254break;
4255case Arg::Index:
4256#if CPU(X86) || CPU(X86_64)
4257if (!Arg::isValidImmForm(args[0].value()))
4258OPGEN_RETURN(false);
4259if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
4260OPGEN_RETURN(false);
4261OPGEN_RETURN(true);
4262#endif
4263break;
4264break;
4265default:
4266break;
4267}
4268break;
4269case Arg::Tmp:
4270switch (this->args[1].kind()) {
4271case Arg::Addr:
4272case Arg::Stack:
4273case Arg::CallArg:
4274#if CPU(X86) || CPU(X86_64)
4275if (!args[0].tmp().isGP())
4276OPGEN_RETURN(false);
4277if (!Arg::isValidAddrForm(args[1].offset()))
4278OPGEN_RETURN(false);
4279OPGEN_RETURN(true);
4280#endif
4281break;
4282break;
4283case Arg::Index:
4284#if CPU(X86) || CPU(X86_64)
4285if (!args[0].tmp().isGP())
4286OPGEN_RETURN(false);
4287if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
4288OPGEN_RETURN(false);
4289OPGEN_RETURN(true);
4290#endif
4291break;
4292break;
4293default:
4294break;
4295}
4296break;
4297default:
4298break;
4299}
4300break;
4301default:
4302break;
4303}
4304break;
4305case Opcode::Add64:
4306switch (this->args.size()) {
4307case 2:
4308switch (this->args[0].kind()) {
4309case Arg::Tmp:
4310switch (this->args[1].kind()) {
4311case Arg::Tmp:
4312#if CPU(X86_64) || CPU(ARM64)
4313if (!args[0].tmp().isGP())
4314OPGEN_RETURN(false);
4315if (!args[1].tmp().isGP())
4316OPGEN_RETURN(false);
4317OPGEN_RETURN(true);
4318#endif
4319break;
4320break;
4321case Arg::Addr:
4322case Arg::Stack:
4323case Arg::CallArg:
4324#if CPU(X86_64)
4325if (!args[0].tmp().isGP())
4326OPGEN_RETURN(false);
4327if (!Arg::isValidAddrForm(args[1].offset()))
4328OPGEN_RETURN(false);
4329OPGEN_RETURN(true);
4330#endif
4331break;
4332break;
4333case Arg::Index:
4334#if CPU(X86_64)
4335if (!args[0].tmp().isGP())
4336OPGEN_RETURN(false);
4337if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4338OPGEN_RETURN(false);
4339OPGEN_RETURN(true);
4340#endif
4341break;
4342break;
4343default:
4344break;
4345}
4346break;
4347case Arg::Imm:
4348switch (this->args[1].kind()) {
4349case Arg::Addr:
4350case Arg::Stack:
4351case Arg::CallArg:
4352#if CPU(X86_64)
4353if (!Arg::isValidImmForm(args[0].value()))
4354OPGEN_RETURN(false);
4355if (!Arg::isValidAddrForm(args[1].offset()))
4356OPGEN_RETURN(false);
4357OPGEN_RETURN(true);
4358#endif
4359break;
4360break;
4361case Arg::Index:
4362#if CPU(X86_64)
4363if (!Arg::isValidImmForm(args[0].value()))
4364OPGEN_RETURN(false);
4365if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4366OPGEN_RETURN(false);
4367OPGEN_RETURN(true);
4368#endif
4369break;
4370break;
4371case Arg::Tmp:
4372#if CPU(X86_64) || CPU(ARM64)
4373if (!Arg::isValidImmForm(args[0].value()))
4374OPGEN_RETURN(false);
4375if (!args[1].tmp().isGP())
4376OPGEN_RETURN(false);
4377OPGEN_RETURN(true);
4378#endif
4379break;
4380break;
4381default:
4382break;
4383}
4384break;
4385case Arg::Addr:
4386case Arg::Stack:
4387case Arg::CallArg:
4388switch (this->args[1].kind()) {
4389case Arg::Tmp:
4390#if CPU(X86_64)
4391if (!Arg::isValidAddrForm(args[0].offset()))
4392OPGEN_RETURN(false);
4393if (!args[1].tmp().isGP())
4394OPGEN_RETURN(false);
4395OPGEN_RETURN(true);
4396#endif
4397break;
4398break;
4399default:
4400break;
4401}
4402break;
4403case Arg::Index:
4404switch (this->args[1].kind()) {
4405case Arg::Tmp:
4406#if CPU(X86_64)
4407if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
4408OPGEN_RETURN(false);
4409if (!args[1].tmp().isGP())
4410OPGEN_RETURN(false);
4411OPGEN_RETURN(true);
4412#endif
4413break;
4414break;
4415default:
4416break;
4417}
4418break;
4419default:
4420break;
4421}
4422break;
4423case 3:
4424switch (this->args[0].kind()) {
4425case Arg::Imm:
4426switch (this->args[1].kind()) {
4427case Arg::Tmp:
4428switch (this->args[2].kind()) {
4429case Arg::Tmp:
4430#if CPU(X86_64) || CPU(ARM64)
4431if (!Arg::isValidImmForm(args[0].value()))
4432OPGEN_RETURN(false);
4433if (!args[1].tmp().isGP())
4434OPGEN_RETURN(false);
4435if (!args[2].tmp().isGP())
4436OPGEN_RETURN(false);
4437OPGEN_RETURN(true);
4438#endif
4439break;
4440break;
4441default:
4442break;
4443}
4444break;
4445default:
4446break;
4447}
4448break;
4449case Arg::Tmp:
4450switch (this->args[1].kind()) {
4451case Arg::Tmp:
4452switch (this->args[2].kind()) {
4453case Arg::Tmp:
4454#if CPU(X86_64) || CPU(ARM64)
4455if (!args[0].tmp().isGP())
4456OPGEN_RETURN(false);
4457if (!args[1].tmp().isGP())
4458OPGEN_RETURN(false);
4459if (!args[2].tmp().isGP())
4460OPGEN_RETURN(false);
4461OPGEN_RETURN(true);
4462#endif
4463break;
4464break;
4465default:
4466break;
4467}
4468break;
4469default:
4470break;
4471}
4472break;
4473default:
4474break;
4475}
4476break;
4477default:
4478break;
4479}
4480break;
4481case Opcode::AddDouble:
4482switch (this->args.size()) {
4483case 3:
4484switch (this->args[0].kind()) {
4485case Arg::Tmp:
4486switch (this->args[1].kind()) {
4487case Arg::Tmp:
4488switch (this->args[2].kind()) {
4489case Arg::Tmp:
4490if (!args[0].tmp().isFP())
4491OPGEN_RETURN(false);
4492if (!args[1].tmp().isFP())
4493OPGEN_RETURN(false);
4494if (!args[2].tmp().isFP())
4495OPGEN_RETURN(false);
4496OPGEN_RETURN(true);
4497break;
4498break;
4499default:
4500break;
4501}
4502break;
4503case Arg::Addr:
4504case Arg::Stack:
4505case Arg::CallArg:
4506switch (this->args[2].kind()) {
4507case Arg::Tmp:
4508#if CPU(X86) || CPU(X86_64)
4509if (!args[0].tmp().isFP())
4510OPGEN_RETURN(false);
4511if (!Arg::isValidAddrForm(args[1].offset()))
4512OPGEN_RETURN(false);
4513if (!args[2].tmp().isFP())
4514OPGEN_RETURN(false);
4515OPGEN_RETURN(true);
4516#endif
4517break;
4518break;
4519default:
4520break;
4521}
4522break;
4523default:
4524break;
4525}
4526break;
4527case Arg::Addr:
4528case Arg::Stack:
4529case Arg::CallArg:
4530switch (this->args[1].kind()) {
4531case Arg::Tmp:
4532switch (this->args[2].kind()) {
4533case Arg::Tmp:
4534#if CPU(X86) || CPU(X86_64)
4535if (!Arg::isValidAddrForm(args[0].offset()))
4536OPGEN_RETURN(false);
4537if (!args[1].tmp().isFP())
4538OPGEN_RETURN(false);
4539if (!args[2].tmp().isFP())
4540OPGEN_RETURN(false);
4541OPGEN_RETURN(true);
4542#endif
4543break;
4544break;
4545default:
4546break;
4547}
4548break;
4549default:
4550break;
4551}
4552break;
4553case Arg::Index:
4554switch (this->args[1].kind()) {
4555case Arg::Tmp:
4556switch (this->args[2].kind()) {
4557case Arg::Tmp:
4558#if CPU(X86) || CPU(X86_64)
4559if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
4560OPGEN_RETURN(false);
4561if (!args[1].tmp().isFP())
4562OPGEN_RETURN(false);
4563if (!args[2].tmp().isFP())
4564OPGEN_RETURN(false);
4565OPGEN_RETURN(true);
4566#endif
4567break;
4568break;
4569default:
4570break;
4571}
4572break;
4573default:
4574break;
4575}
4576break;
4577default:
4578break;
4579}
4580break;
4581case 2:
4582switch (this->args[0].kind()) {
4583case Arg::Tmp:
4584switch (this->args[1].kind()) {
4585case Arg::Tmp:
4586#if CPU(X86) || CPU(X86_64)
4587if (!args[0].tmp().isFP())
4588OPGEN_RETURN(false);
4589if (!args[1].tmp().isFP())
4590OPGEN_RETURN(false);
4591OPGEN_RETURN(true);
4592#endif
4593break;
4594break;
4595default:
4596break;
4597}
4598break;
4599case Arg::Addr:
4600case Arg::Stack:
4601case Arg::CallArg:
4602switch (this->args[1].kind()) {
4603case Arg::Tmp:
4604#if CPU(X86) || CPU(X86_64)
4605if (!Arg::isValidAddrForm(args[0].offset()))
4606OPGEN_RETURN(false);
4607if (!args[1].tmp().isFP())
4608OPGEN_RETURN(false);
4609OPGEN_RETURN(true);
4610#endif
4611break;
4612break;
4613default:
4614break;
4615}
4616break;
4617default:
4618break;
4619}
4620break;
4621default:
4622break;
4623}
4624break;
4625case Opcode::AddFloat:
4626switch (this->args.size()) {
4627case 3:
4628switch (this->args[0].kind()) {
4629case Arg::Tmp:
4630switch (this->args[1].kind()) {
4631case Arg::Tmp:
4632switch (this->args[2].kind()) {
4633case Arg::Tmp:
4634if (!args[0].tmp().isFP())
4635OPGEN_RETURN(false);
4636if (!args[1].tmp().isFP())
4637OPGEN_RETURN(false);
4638if (!args[2].tmp().isFP())
4639OPGEN_RETURN(false);
4640OPGEN_RETURN(true);
4641break;
4642break;
4643default:
4644break;
4645}
4646break;
4647case Arg::Addr:
4648case Arg::Stack:
4649case Arg::CallArg:
4650switch (this->args[2].kind()) {
4651case Arg::Tmp:
4652#if CPU(X86) || CPU(X86_64)
4653if (!args[0].tmp().isFP())
4654OPGEN_RETURN(false);
4655if (!Arg::isValidAddrForm(args[1].offset()))
4656OPGEN_RETURN(false);
4657if (!args[2].tmp().isFP())
4658OPGEN_RETURN(false);
4659OPGEN_RETURN(true);
4660#endif
4661break;
4662break;
4663default:
4664break;
4665}
4666break;
4667default:
4668break;
4669}
4670break;
4671case Arg::Addr:
4672case Arg::Stack:
4673case Arg::CallArg:
4674switch (this->args[1].kind()) {
4675case Arg::Tmp:
4676switch (this->args[2].kind()) {
4677case Arg::Tmp:
4678#if CPU(X86) || CPU(X86_64)
4679if (!Arg::isValidAddrForm(args[0].offset()))
4680OPGEN_RETURN(false);
4681if (!args[1].tmp().isFP())
4682OPGEN_RETURN(false);
4683if (!args[2].tmp().isFP())
4684OPGEN_RETURN(false);
4685OPGEN_RETURN(true);
4686#endif
4687break;
4688break;
4689default:
4690break;
4691}
4692break;
4693default:
4694break;
4695}
4696break;
4697case Arg::Index:
4698switch (this->args[1].kind()) {
4699case Arg::Tmp:
4700switch (this->args[2].kind()) {
4701case Arg::Tmp:
4702#if CPU(X86) || CPU(X86_64)
4703if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4704OPGEN_RETURN(false);
4705if (!args[1].tmp().isFP())
4706OPGEN_RETURN(false);
4707if (!args[2].tmp().isFP())
4708OPGEN_RETURN(false);
4709OPGEN_RETURN(true);
4710#endif
4711break;
4712break;
4713default:
4714break;
4715}
4716break;
4717default:
4718break;
4719}
4720break;
4721default:
4722break;
4723}
4724break;
4725case 2:
4726switch (this->args[0].kind()) {
4727case Arg::Tmp:
4728switch (this->args[1].kind()) {
4729case Arg::Tmp:
4730#if CPU(X86) || CPU(X86_64)
4731if (!args[0].tmp().isFP())
4732OPGEN_RETURN(false);
4733if (!args[1].tmp().isFP())
4734OPGEN_RETURN(false);
4735OPGEN_RETURN(true);
4736#endif
4737break;
4738break;
4739default:
4740break;
4741}
4742break;
4743case Arg::Addr:
4744case Arg::Stack:
4745case Arg::CallArg:
4746switch (this->args[1].kind()) {
4747case Arg::Tmp:
4748#if CPU(X86) || CPU(X86_64)
4749if (!Arg::isValidAddrForm(args[0].offset()))
4750OPGEN_RETURN(false);
4751if (!args[1].tmp().isFP())
4752OPGEN_RETURN(false);
4753OPGEN_RETURN(true);
4754#endif
4755break;
4756break;
4757default:
4758break;
4759}
4760break;
4761default:
4762break;
4763}
4764break;
4765default:
4766break;
4767}
4768break;
4769case Opcode::Sub32:
4770switch (this->args.size()) {
4771case 2:
4772switch (this->args[0].kind()) {
4773case Arg::Tmp:
4774switch (this->args[1].kind()) {
4775case Arg::Tmp:
4776if (!args[0].tmp().isGP())
4777OPGEN_RETURN(false);
4778if (!args[1].tmp().isGP())
4779OPGEN_RETURN(false);
4780OPGEN_RETURN(true);
4781break;
4782break;
4783case Arg::Addr:
4784case Arg::Stack:
4785case Arg::CallArg:
4786#if CPU(X86) || CPU(X86_64)
4787if (!args[0].tmp().isGP())
4788OPGEN_RETURN(false);
4789if (!Arg::isValidAddrForm(args[1].offset()))
4790OPGEN_RETURN(false);
4791OPGEN_RETURN(true);
4792#endif
4793break;
4794break;
4795case Arg::Index:
4796#if CPU(X86) || CPU(X86_64)
4797if (!args[0].tmp().isGP())
4798OPGEN_RETURN(false);
4799if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4800OPGEN_RETURN(false);
4801OPGEN_RETURN(true);
4802#endif
4803break;
4804break;
4805default:
4806break;
4807}
4808break;
4809case Arg::Imm:
4810switch (this->args[1].kind()) {
4811case Arg::Addr:
4812case Arg::Stack:
4813case Arg::CallArg:
4814#if CPU(X86) || CPU(X86_64)
4815if (!Arg::isValidImmForm(args[0].value()))
4816OPGEN_RETURN(false);
4817if (!Arg::isValidAddrForm(args[1].offset()))
4818OPGEN_RETURN(false);
4819OPGEN_RETURN(true);
4820#endif
4821break;
4822break;
4823case Arg::Index:
4824#if CPU(X86) || CPU(X86_64)
4825if (!Arg::isValidImmForm(args[0].value()))
4826OPGEN_RETURN(false);
4827if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4828OPGEN_RETURN(false);
4829OPGEN_RETURN(true);
4830#endif
4831break;
4832break;
4833case Arg::Tmp:
4834if (!Arg::isValidImmForm(args[0].value()))
4835OPGEN_RETURN(false);
4836if (!args[1].tmp().isGP())
4837OPGEN_RETURN(false);
4838OPGEN_RETURN(true);
4839break;
4840break;
4841default:
4842break;
4843}
4844break;
4845case Arg::Addr:
4846case Arg::Stack:
4847case Arg::CallArg:
4848switch (this->args[1].kind()) {
4849case Arg::Tmp:
4850#if CPU(X86) || CPU(X86_64)
4851if (!Arg::isValidAddrForm(args[0].offset()))
4852OPGEN_RETURN(false);
4853if (!args[1].tmp().isGP())
4854OPGEN_RETURN(false);
4855OPGEN_RETURN(true);
4856#endif
4857break;
4858break;
4859default:
4860break;
4861}
4862break;
4863case Arg::Index:
4864switch (this->args[1].kind()) {
4865case Arg::Tmp:
4866#if CPU(X86) || CPU(X86_64)
4867if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4868OPGEN_RETURN(false);
4869if (!args[1].tmp().isGP())
4870OPGEN_RETURN(false);
4871OPGEN_RETURN(true);
4872#endif
4873break;
4874break;
4875default:
4876break;
4877}
4878break;
4879default:
4880break;
4881}
4882break;
4883case 3:
4884switch (this->args[0].kind()) {
4885case Arg::Tmp:
4886switch (this->args[1].kind()) {
4887case Arg::Tmp:
4888switch (this->args[2].kind()) {
4889case Arg::Tmp:
4890#if CPU(ARM64)
4891if (!args[0].tmp().isGP())
4892OPGEN_RETURN(false);
4893if (!args[1].tmp().isGP())
4894OPGEN_RETURN(false);
4895if (!args[2].tmp().isGP())
4896OPGEN_RETURN(false);
4897OPGEN_RETURN(true);
4898#endif
4899break;
4900break;
4901default:
4902break;
4903}
4904break;
4905default:
4906break;
4907}
4908break;
4909default:
4910break;
4911}
4912break;
4913default:
4914break;
4915}
4916break;
4917case Opcode::Sub64:
4918switch (this->args.size()) {
4919case 2:
4920switch (this->args[0].kind()) {
4921case Arg::Tmp:
4922switch (this->args[1].kind()) {
4923case Arg::Tmp:
4924#if CPU(X86_64) || CPU(ARM64)
4925if (!args[0].tmp().isGP())
4926OPGEN_RETURN(false);
4927if (!args[1].tmp().isGP())
4928OPGEN_RETURN(false);
4929OPGEN_RETURN(true);
4930#endif
4931break;
4932break;
4933case Arg::Addr:
4934case Arg::Stack:
4935case Arg::CallArg:
4936#if CPU(X86_64)
4937if (!args[0].tmp().isGP())
4938OPGEN_RETURN(false);
4939if (!Arg::isValidAddrForm(args[1].offset()))
4940OPGEN_RETURN(false);
4941OPGEN_RETURN(true);
4942#endif
4943break;
4944break;
4945case Arg::Index:
4946#if CPU(X86_64)
4947if (!args[0].tmp().isGP())
4948OPGEN_RETURN(false);
4949if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4950OPGEN_RETURN(false);
4951OPGEN_RETURN(true);
4952#endif
4953break;
4954break;
4955default:
4956break;
4957}
4958break;
4959case Arg::Imm:
4960switch (this->args[1].kind()) {
4961case Arg::Addr:
4962case Arg::Stack:
4963case Arg::CallArg:
4964#if CPU(X86_64)
4965if (!Arg::isValidImmForm(args[0].value()))
4966OPGEN_RETURN(false);
4967if (!Arg::isValidAddrForm(args[1].offset()))
4968OPGEN_RETURN(false);
4969OPGEN_RETURN(true);
4970#endif
4971break;
4972break;
4973case Arg::Index:
4974#if CPU(X86_64)
4975if (!Arg::isValidImmForm(args[0].value()))
4976OPGEN_RETURN(false);
4977if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4978OPGEN_RETURN(false);
4979OPGEN_RETURN(true);
4980#endif
4981break;
4982break;
4983case Arg::Tmp:
4984#if CPU(X86_64) || CPU(ARM64)
4985if (!Arg::isValidImmForm(args[0].value()))
4986OPGEN_RETURN(false);
4987if (!args[1].tmp().isGP())
4988OPGEN_RETURN(false);
4989OPGEN_RETURN(true);
4990#endif
4991break;
4992break;
4993default:
4994break;
4995}
4996break;
4997case Arg::Addr:
4998case Arg::Stack:
4999case Arg::CallArg:
5000switch (this->args[1].kind()) {
5001case Arg::Tmp:
5002#if CPU(X86_64)
5003if (!Arg::isValidAddrForm(args[0].offset()))
5004OPGEN_RETURN(false);
5005if (!args[1].tmp().isGP())
5006OPGEN_RETURN(false);
5007OPGEN_RETURN(true);
5008#endif
5009break;
5010break;
5011default:
5012break;
5013}
5014break;
5015case Arg::Index:
5016switch (this->args[1].kind()) {
5017case Arg::Tmp:
5018#if CPU(X86_64)
5019if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
5020OPGEN_RETURN(false);
5021if (!args[1].tmp().isGP())
5022OPGEN_RETURN(false);
5023OPGEN_RETURN(true);
5024#endif
5025break;
5026break;
5027default:
5028break;
5029}
5030break;
5031default:
5032break;
5033}
5034break;
5035case 3:
5036switch (this->args[0].kind()) {
5037case Arg::Tmp:
5038switch (this->args[1].kind()) {
5039case Arg::Tmp:
5040switch (this->args[2].kind()) {
5041case Arg::Tmp:
5042#if CPU(ARM64)
5043if (!args[0].tmp().isGP())
5044OPGEN_RETURN(false);
5045if (!args[1].tmp().isGP())
5046OPGEN_RETURN(false);
5047if (!args[2].tmp().isGP())
5048OPGEN_RETURN(false);
5049OPGEN_RETURN(true);
5050#endif
5051break;
5052break;
5053default:
5054break;
5055}
5056break;
5057default:
5058break;
5059}
5060break;
5061default:
5062break;
5063}
5064break;
5065default:
5066break;
5067}
5068break;
5069case Opcode::SubDouble:
5070switch (this->args.size()) {
5071case 3:
5072switch (this->args[0].kind()) {
5073case Arg::Tmp:
5074switch (this->args[1].kind()) {
5075case Arg::Tmp:
5076switch (this->args[2].kind()) {
5077case Arg::Tmp:
5078#if CPU(ARM64)
5079if (!args[0].tmp().isFP())
5080OPGEN_RETURN(false);
5081if (!args[1].tmp().isFP())
5082OPGEN_RETURN(false);
5083if (!args[2].tmp().isFP())
5084OPGEN_RETURN(false);
5085OPGEN_RETURN(true);
5086#endif
5087break;
5088break;
5089default:
5090break;
5091}
5092break;
5093case Arg::Addr:
5094case Arg::Stack:
5095case Arg::CallArg:
5096switch (this->args[2].kind()) {
5097case Arg::Tmp:
5098#if CPU(X86) || CPU(X86_64)
5099if (!args[0].tmp().isFP())
5100OPGEN_RETURN(false);
5101if (!Arg::isValidAddrForm(args[1].offset()))
5102OPGEN_RETURN(false);
5103if (!args[2].tmp().isFP())
5104OPGEN_RETURN(false);
5105OPGEN_RETURN(true);
5106#endif
5107break;
5108break;
5109default:
5110break;
5111}
5112break;
5113case Arg::Index:
5114switch (this->args[2].kind()) {
5115case Arg::Tmp:
5116#if CPU(X86) || CPU(X86_64)
5117if (!args[0].tmp().isFP())
5118OPGEN_RETURN(false);
5119if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
5120OPGEN_RETURN(false);
5121if (!args[2].tmp().isFP())
5122OPGEN_RETURN(false);
5123OPGEN_RETURN(true);
5124#endif
5125break;
5126break;
5127default:
5128break;
5129}
5130break;
5131default:
5132break;
5133}
5134break;
5135default:
5136break;
5137}
5138break;
5139case 2:
5140switch (this->args[0].kind()) {
5141case Arg::Tmp:
5142switch (this->args[1].kind()) {
5143case Arg::Tmp:
5144#if CPU(X86) || CPU(X86_64)
5145if (!args[0].tmp().isFP())
5146OPGEN_RETURN(false);
5147if (!args[1].tmp().isFP())
5148OPGEN_RETURN(false);
5149OPGEN_RETURN(true);
5150#endif
5151break;
5152break;
5153default:
5154break;
5155}
5156break;
5157case Arg::Addr:
5158case Arg::Stack:
5159case Arg::CallArg:
5160switch (this->args[1].kind()) {
5161case Arg::Tmp:
5162#if CPU(X86) || CPU(X86_64)
5163if (!Arg::isValidAddrForm(args[0].offset()))
5164OPGEN_RETURN(false);
5165if (!args[1].tmp().isFP())
5166OPGEN_RETURN(false);
5167OPGEN_RETURN(true);
5168#endif
5169break;
5170break;
5171default:
5172break;
5173}
5174break;
5175default:
5176break;
5177}
5178break;
5179default:
5180break;
5181}
5182break;
5183case Opcode::SubFloat:
5184switch (this->args.size()) {
5185case 3:
5186switch (this->args[0].kind()) {
5187case Arg::Tmp:
5188switch (this->args[1].kind()) {
5189case Arg::Tmp:
5190switch (this->args[2].kind()) {
5191case Arg::Tmp:
5192#if CPU(ARM64)
5193if (!args[0].tmp().isFP())
5194OPGEN_RETURN(false);
5195if (!args[1].tmp().isFP())
5196OPGEN_RETURN(false);
5197if (!args[2].tmp().isFP())
5198OPGEN_RETURN(false);
5199OPGEN_RETURN(true);
5200#endif
5201break;
5202break;
5203default:
5204break;
5205}
5206break;
5207case Arg::Addr:
5208case Arg::Stack:
5209case Arg::CallArg:
5210switch (this->args[2].kind()) {
5211case Arg::Tmp:
5212#if CPU(X86) || CPU(X86_64)
5213if (!args[0].tmp().isFP())
5214OPGEN_RETURN(false);
5215if (!Arg::isValidAddrForm(args[1].offset()))
5216OPGEN_RETURN(false);
5217if (!args[2].tmp().isFP())
5218OPGEN_RETURN(false);
5219OPGEN_RETURN(true);
5220#endif
5221break;
5222break;
5223default:
5224break;
5225}
5226break;
5227case Arg::Index:
5228switch (this->args[2].kind()) {
5229case Arg::Tmp:
5230#if CPU(X86) || CPU(X86_64)
5231if (!args[0].tmp().isFP())
5232OPGEN_RETURN(false);
5233if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
5234OPGEN_RETURN(false);
5235if (!args[2].tmp().isFP())
5236OPGEN_RETURN(false);
5237OPGEN_RETURN(true);
5238#endif
5239break;
5240break;
5241default:
5242break;
5243}
5244break;
5245default:
5246break;
5247}
5248break;
5249default:
5250break;
5251}
5252break;
5253case 2:
5254switch (this->args[0].kind()) {
5255case Arg::Tmp:
5256switch (this->args[1].kind()) {
5257case Arg::Tmp:
5258#if CPU(X86) || CPU(X86_64)
5259if (!args[0].tmp().isFP())
5260OPGEN_RETURN(false);
5261if (!args[1].tmp().isFP())
5262OPGEN_RETURN(false);
5263OPGEN_RETURN(true);
5264#endif
5265break;
5266break;
5267default:
5268break;
5269}
5270break;
5271case Arg::Addr:
5272case Arg::Stack:
5273case Arg::CallArg:
5274switch (this->args[1].kind()) {
5275case Arg::Tmp:
5276#if CPU(X86) || CPU(X86_64)
5277if (!Arg::isValidAddrForm(args[0].offset()))
5278OPGEN_RETURN(false);
5279if (!args[1].tmp().isFP())
5280OPGEN_RETURN(false);
5281OPGEN_RETURN(true);
5282#endif
5283break;
5284break;
5285default:
5286break;
5287}
5288break;
5289default:
5290break;
5291}
5292break;
5293default:
5294break;
5295}
5296break;
5297case Opcode::Neg32:
5298switch (this->args.size()) {
5299case 1:
5300switch (this->args[0].kind()) {
5301case Arg::Tmp:
5302if (!args[0].tmp().isGP())
5303OPGEN_RETURN(false);
5304OPGEN_RETURN(true);
5305break;
5306break;
5307case Arg::Addr:
5308case Arg::Stack:
5309case Arg::CallArg:
5310#if CPU(X86) || CPU(X86_64)
5311if (!Arg::isValidAddrForm(args[0].offset()))
5312OPGEN_RETURN(false);
5313OPGEN_RETURN(true);
5314#endif
5315break;
5316break;
5317case Arg::Index:
5318#if CPU(X86) || CPU(X86_64)
5319if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
5320OPGEN_RETURN(false);
5321OPGEN_RETURN(true);
5322#endif
5323break;
5324break;
5325default:
5326break;
5327}
5328break;
5329default:
5330break;
5331}
5332break;
5333case Opcode::Neg64:
5334switch (this->args.size()) {
5335case 1:
5336switch (this->args[0].kind()) {
5337case Arg::Tmp:
5338#if CPU(X86_64) || CPU(ARM64)
5339if (!args[0].tmp().isGP())
5340OPGEN_RETURN(false);
5341OPGEN_RETURN(true);
5342#endif
5343break;
5344break;
5345case Arg::Addr:
5346case Arg::Stack:
5347case Arg::CallArg:
5348#if CPU(X86_64)
5349if (!Arg::isValidAddrForm(args[0].offset()))
5350OPGEN_RETURN(false);
5351OPGEN_RETURN(true);
5352#endif
5353break;
5354break;
5355case Arg::Index:
5356#if CPU(X86_64)
5357if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
5358OPGEN_RETURN(false);
5359OPGEN_RETURN(true);
5360#endif
5361break;
5362break;
5363default:
5364break;
5365}
5366break;
5367default:
5368break;
5369}
5370break;
5371case Opcode::NegateDouble:
5372switch (this->args.size()) {
5373case 2:
5374switch (this->args[0].kind()) {
5375case Arg::Tmp:
5376switch (this->args[1].kind()) {
5377case Arg::Tmp:
5378#if CPU(ARM64)
5379if (!args[0].tmp().isFP())
5380OPGEN_RETURN(false);
5381if (!args[1].tmp().isFP())
5382OPGEN_RETURN(false);
5383OPGEN_RETURN(true);
5384#endif
5385break;
5386break;
5387default:
5388break;
5389}
5390break;
5391default:
5392break;
5393}
5394break;
5395default:
5396break;
5397}
5398break;
5399case Opcode::NegateFloat:
5400switch (this->args.size()) {
5401case 2:
5402switch (this->args[0].kind()) {
5403case Arg::Tmp:
5404switch (this->args[1].kind()) {
5405case Arg::Tmp:
5406#if CPU(ARM64)
5407if (!args[0].tmp().isFP())
5408OPGEN_RETURN(false);
5409if (!args[1].tmp().isFP())
5410OPGEN_RETURN(false);
5411OPGEN_RETURN(true);
5412#endif
5413break;
5414break;
5415default:
5416break;
5417}
5418break;
5419default:
5420break;
5421}
5422break;
5423default:
5424break;
5425}
5426break;
5427case Opcode::Mul32:
5428switch (this->args.size()) {
5429case 2:
5430switch (this->args[0].kind()) {
5431case Arg::Tmp:
5432switch (this->args[1].kind()) {
5433case Arg::Tmp:
5434if (!args[0].tmp().isGP())
5435OPGEN_RETURN(false);
5436if (!args[1].tmp().isGP())
5437OPGEN_RETURN(false);
5438OPGEN_RETURN(true);
5439break;
5440break;
5441default:
5442break;
5443}
5444break;
5445case Arg::Addr:
5446case Arg::Stack:
5447case Arg::CallArg:
5448switch (this->args[1].kind()) {
5449case Arg::Tmp:
5450#if CPU(X86) || CPU(X86_64)
5451if (!Arg::isValidAddrForm(args[0].offset()))
5452OPGEN_RETURN(false);
5453if (!args[1].tmp().isGP())
5454OPGEN_RETURN(false);
5455OPGEN_RETURN(true);
5456#endif
5457break;
5458break;
5459default:
5460break;
5461}
5462break;
5463default:
5464break;
5465}
5466break;
5467case 3:
5468switch (this->args[0].kind()) {
5469case Arg::Tmp:
5470switch (this->args[1].kind()) {
5471case Arg::Tmp:
5472switch (this->args[2].kind()) {
5473case Arg::Tmp:
5474if (!args[0].tmp().isGP())
5475OPGEN_RETURN(false);
5476if (!args[1].tmp().isGP())
5477OPGEN_RETURN(false);
5478if (!args[2].tmp().isGP())
5479OPGEN_RETURN(false);
5480OPGEN_RETURN(true);
5481break;
5482break;
5483default:
5484break;
5485}
5486break;
5487case Arg::Addr:
5488case Arg::Stack:
5489case Arg::CallArg:
5490switch (this->args[2].kind()) {
5491case Arg::Tmp:
5492#if CPU(X86) || CPU(X86_64)
5493if (!args[0].tmp().isGP())
5494OPGEN_RETURN(false);
5495if (!Arg::isValidAddrForm(args[1].offset()))
5496OPGEN_RETURN(false);
5497if (!args[2].tmp().isGP())
5498OPGEN_RETURN(false);
5499OPGEN_RETURN(true);
5500#endif
5501break;
5502break;
5503default:
5504break;
5505}
5506break;
5507default:
5508break;
5509}
5510break;
5511case Arg::Addr:
5512case Arg::Stack:
5513case Arg::CallArg:
5514switch (this->args[1].kind()) {
5515case Arg::Tmp:
5516switch (this->args[2].kind()) {
5517case Arg::Tmp:
5518#if CPU(X86) || CPU(X86_64)
5519if (!Arg::isValidAddrForm(args[0].offset()))
5520OPGEN_RETURN(false);
5521if (!args[1].tmp().isGP())
5522OPGEN_RETURN(false);
5523if (!args[2].tmp().isGP())
5524OPGEN_RETURN(false);
5525OPGEN_RETURN(true);
5526#endif
5527break;
5528break;
5529default:
5530break;
5531}
5532break;
5533default:
5534break;
5535}
5536break;
5537case Arg::Imm:
5538switch (this->args[1].kind()) {
5539case Arg::Tmp:
5540switch (this->args[2].kind()) {
5541case Arg::Tmp:
5542#if CPU(X86) || CPU(X86_64)
5543if (!Arg::isValidImmForm(args[0].value()))
5544OPGEN_RETURN(false);
5545if (!args[1].tmp().isGP())
5546OPGEN_RETURN(false);
5547if (!args[2].tmp().isGP())
5548OPGEN_RETURN(false);
5549OPGEN_RETURN(true);
5550#endif
5551break;
5552break;
5553default:
5554break;
5555}
5556break;
5557default:
5558break;
5559}
5560break;
5561default:
5562break;
5563}
5564break;
5565default:
5566break;
5567}
5568break;
5569case Opcode::Mul64:
5570switch (this->args.size()) {
5571case 2:
5572switch (this->args[0].kind()) {
5573case Arg::Tmp:
5574switch (this->args[1].kind()) {
5575case Arg::Tmp:
5576#if CPU(X86_64) || CPU(ARM64)
5577if (!args[0].tmp().isGP())
5578OPGEN_RETURN(false);
5579if (!args[1].tmp().isGP())
5580OPGEN_RETURN(false);
5581OPGEN_RETURN(true);
5582#endif
5583break;
5584break;
5585default:
5586break;
5587}
5588break;
5589default:
5590break;
5591}
5592break;
5593case 3:
5594switch (this->args[0].kind()) {
5595case Arg::Tmp:
5596switch (this->args[1].kind()) {
5597case Arg::Tmp:
5598switch (this->args[2].kind()) {
5599case Arg::Tmp:
5600if (!args[0].tmp().isGP())
5601OPGEN_RETURN(false);
5602if (!args[1].tmp().isGP())
5603OPGEN_RETURN(false);
5604if (!args[2].tmp().isGP())
5605OPGEN_RETURN(false);
5606OPGEN_RETURN(true);
5607break;
5608break;
5609default:
5610break;
5611}
5612break;
5613default:
5614break;
5615}
5616break;
5617default:
5618break;
5619}
5620break;
5621default:
5622break;
5623}
5624break;
5625case Opcode::MultiplyAdd32:
5626switch (this->args.size()) {
5627case 4:
5628switch (this->args[0].kind()) {
5629case Arg::Tmp:
5630switch (this->args[1].kind()) {
5631case Arg::Tmp:
5632switch (this->args[2].kind()) {
5633case Arg::Tmp:
5634switch (this->args[3].kind()) {
5635case Arg::Tmp:
5636#if CPU(ARM64)
5637if (!args[0].tmp().isGP())
5638OPGEN_RETURN(false);
5639if (!args[1].tmp().isGP())
5640OPGEN_RETURN(false);
5641if (!args[2].tmp().isGP())
5642OPGEN_RETURN(false);
5643if (!args[3].tmp().isGP())
5644OPGEN_RETURN(false);
5645OPGEN_RETURN(true);
5646#endif
5647break;
5648break;
5649default:
5650break;
5651}
5652break;
5653default:
5654break;
5655}
5656break;
5657default:
5658break;
5659}
5660break;
5661default:
5662break;
5663}
5664break;
5665default:
5666break;
5667}
5668break;
5669case Opcode::MultiplyAdd64:
5670switch (this->args.size()) {
5671case 4:
5672switch (this->args[0].kind()) {
5673case Arg::Tmp:
5674switch (this->args[1].kind()) {
5675case Arg::Tmp:
5676switch (this->args[2].kind()) {
5677case Arg::Tmp:
5678switch (this->args[3].kind()) {
5679case Arg::Tmp:
5680#if CPU(ARM64)
5681if (!args[0].tmp().isGP())
5682OPGEN_RETURN(false);
5683if (!args[1].tmp().isGP())
5684OPGEN_RETURN(false);
5685if (!args[2].tmp().isGP())
5686OPGEN_RETURN(false);
5687if (!args[3].tmp().isGP())
5688OPGEN_RETURN(false);
5689OPGEN_RETURN(true);
5690#endif
5691break;
5692break;
5693default:
5694break;
5695}
5696break;
5697default:
5698break;
5699}
5700break;
5701default:
5702break;
5703}
5704break;
5705default:
5706break;
5707}
5708break;
5709default:
5710break;
5711}
5712break;
5713case Opcode::MultiplySub32:
5714switch (this->args.size()) {
5715case 4:
5716switch (this->args[0].kind()) {
5717case Arg::Tmp:
5718switch (this->args[1].kind()) {
5719case Arg::Tmp:
5720switch (this->args[2].kind()) {
5721case Arg::Tmp:
5722switch (this->args[3].kind()) {
5723case Arg::Tmp:
5724#if CPU(ARM64)
5725if (!args[0].tmp().isGP())
5726OPGEN_RETURN(false);
5727if (!args[1].tmp().isGP())
5728OPGEN_RETURN(false);
5729if (!args[2].tmp().isGP())
5730OPGEN_RETURN(false);
5731if (!args[3].tmp().isGP())
5732OPGEN_RETURN(false);
5733OPGEN_RETURN(true);
5734#endif
5735break;
5736break;
5737default:
5738break;
5739}
5740break;
5741default:
5742break;
5743}
5744break;
5745default:
5746break;
5747}
5748break;
5749default:
5750break;
5751}
5752break;
5753default:
5754break;
5755}
5756break;
5757case Opcode::MultiplySub64:
5758switch (this->args.size()) {
5759case 4:
5760switch (this->args[0].kind()) {
5761case Arg::Tmp:
5762switch (this->args[1].kind()) {
5763case Arg::Tmp:
5764switch (this->args[2].kind()) {
5765case Arg::Tmp:
5766switch (this->args[3].kind()) {
5767case Arg::Tmp:
5768#if CPU(ARM64)
5769if (!args[0].tmp().isGP())
5770OPGEN_RETURN(false);
5771if (!args[1].tmp().isGP())
5772OPGEN_RETURN(false);
5773if (!args[2].tmp().isGP())
5774OPGEN_RETURN(false);
5775if (!args[3].tmp().isGP())
5776OPGEN_RETURN(false);
5777OPGEN_RETURN(true);
5778#endif
5779break;
5780break;
5781default:
5782break;
5783}
5784break;
5785default:
5786break;
5787}
5788break;
5789default:
5790break;
5791}
5792break;
5793default:
5794break;
5795}
5796break;
5797default:
5798break;
5799}
5800break;
5801case Opcode::MultiplyNeg32:
5802switch (this->args.size()) {
5803case 3:
5804switch (this->args[0].kind()) {
5805case Arg::Tmp:
5806switch (this->args[1].kind()) {
5807case Arg::Tmp:
5808switch (this->args[2].kind()) {
5809case Arg::Tmp:
5810#if CPU(ARM64)
5811if (!args[0].tmp().isGP())
5812OPGEN_RETURN(false);
5813if (!args[1].tmp().isGP())
5814OPGEN_RETURN(false);
5815if (!args[2].tmp().isGP())
5816OPGEN_RETURN(false);
5817OPGEN_RETURN(true);
5818#endif
5819break;
5820break;
5821default:
5822break;
5823}
5824break;
5825default:
5826break;
5827}
5828break;
5829default:
5830break;
5831}
5832break;
5833default:
5834break;
5835}
5836break;
5837case Opcode::MultiplyNeg64:
5838switch (this->args.size()) {
5839case 3:
5840switch (this->args[0].kind()) {
5841case Arg::Tmp:
5842switch (this->args[1].kind()) {
5843case Arg::Tmp:
5844switch (this->args[2].kind()) {
5845case Arg::Tmp:
5846#if CPU(ARM64)
5847if (!args[0].tmp().isGP())
5848OPGEN_RETURN(false);
5849if (!args[1].tmp().isGP())
5850OPGEN_RETURN(false);
5851if (!args[2].tmp().isGP())
5852OPGEN_RETURN(false);
5853OPGEN_RETURN(true);
5854#endif
5855break;
5856break;
5857default:
5858break;
5859}
5860break;
5861default:
5862break;
5863}
5864break;
5865default:
5866break;
5867}
5868break;
5869default:
5870break;
5871}
5872break;
5873case Opcode::MultiplySignExtend32:
5874switch (this->args.size()) {
5875case 3:
5876switch (this->args[0].kind()) {
5877case Arg::Tmp:
5878switch (this->args[1].kind()) {
5879case Arg::Tmp:
5880switch (this->args[2].kind()) {
5881case Arg::Tmp:
5882#if CPU(ARM64)
5883if (!args[0].tmp().isGP())
5884OPGEN_RETURN(false);
5885if (!args[1].tmp().isGP())
5886OPGEN_RETURN(false);
5887if (!args[2].tmp().isGP())
5888OPGEN_RETURN(false);
5889OPGEN_RETURN(true);
5890#endif
5891break;
5892break;
5893default:
5894break;
5895}
5896break;
5897default:
5898break;
5899}
5900break;
5901default:
5902break;
5903}
5904break;
5905default:
5906break;
5907}
5908break;
5909case Opcode::Div32:
5910switch (this->args.size()) {
5911case 3:
5912switch (this->args[0].kind()) {
5913case Arg::Tmp:
5914switch (this->args[1].kind()) {
5915case Arg::Tmp:
5916switch (this->args[2].kind()) {
5917case Arg::Tmp:
5918#if CPU(ARM64)
5919if (!args[0].tmp().isGP())
5920OPGEN_RETURN(false);
5921if (!args[1].tmp().isGP())
5922OPGEN_RETURN(false);
5923if (!args[2].tmp().isGP())
5924OPGEN_RETURN(false);
5925OPGEN_RETURN(true);
5926#endif
5927break;
5928break;
5929default:
5930break;
5931}
5932break;
5933default:
5934break;
5935}
5936break;
5937default:
5938break;
5939}
5940break;
5941default:
5942break;
5943}
5944break;
5945case Opcode::UDiv32:
5946switch (this->args.size()) {
5947case 3:
5948switch (this->args[0].kind()) {
5949case Arg::Tmp:
5950switch (this->args[1].kind()) {
5951case Arg::Tmp:
5952switch (this->args[2].kind()) {
5953case Arg::Tmp:
5954#if CPU(ARM64)
5955if (!args[0].tmp().isGP())
5956OPGEN_RETURN(false);
5957if (!args[1].tmp().isGP())
5958OPGEN_RETURN(false);
5959if (!args[2].tmp().isGP())
5960OPGEN_RETURN(false);
5961OPGEN_RETURN(true);
5962#endif
5963break;
5964break;
5965default:
5966break;
5967}
5968break;
5969default:
5970break;
5971}
5972break;
5973default:
5974break;
5975}
5976break;
5977default:
5978break;
5979}
5980break;
5981case Opcode::Div64:
5982switch (this->args.size()) {
5983case 3:
5984switch (this->args[0].kind()) {
5985case Arg::Tmp:
5986switch (this->args[1].kind()) {
5987case Arg::Tmp:
5988switch (this->args[2].kind()) {
5989case Arg::Tmp:
5990#if CPU(ARM64)
5991if (!args[0].tmp().isGP())
5992OPGEN_RETURN(false);
5993if (!args[1].tmp().isGP())
5994OPGEN_RETURN(false);
5995if (!args[2].tmp().isGP())
5996OPGEN_RETURN(false);
5997OPGEN_RETURN(true);
5998#endif
5999break;
6000break;
6001default:
6002break;
6003}
6004break;
6005default:
6006break;
6007}
6008break;
6009default:
6010break;
6011}
6012break;
6013default:
6014break;
6015}
6016break;
6017case Opcode::UDiv64:
6018switch (this->args.size()) {
6019case 3:
6020switch (this->args[0].kind()) {
6021case Arg::Tmp:
6022switch (this->args[1].kind()) {
6023case Arg::Tmp:
6024switch (this->args[2].kind()) {
6025case Arg::Tmp:
6026#if CPU(ARM64)
6027if (!args[0].tmp().isGP())
6028OPGEN_RETURN(false);
6029if (!args[1].tmp().isGP())
6030OPGEN_RETURN(false);
6031if (!args[2].tmp().isGP())
6032OPGEN_RETURN(false);
6033OPGEN_RETURN(true);
6034#endif
6035break;
6036break;
6037default:
6038break;
6039}
6040break;
6041default:
6042break;
6043}
6044break;
6045default:
6046break;
6047}
6048break;
6049default:
6050break;
6051}
6052break;
6053case Opcode::MulDouble:
6054switch (this->args.size()) {
6055case 3:
6056switch (this->args[0].kind()) {
6057case Arg::Tmp:
6058switch (this->args[1].kind()) {
6059case Arg::Tmp:
6060switch (this->args[2].kind()) {
6061case Arg::Tmp:
6062if (!args[0].tmp().isFP())
6063OPGEN_RETURN(false);
6064if (!args[1].tmp().isFP())
6065OPGEN_RETURN(false);
6066if (!args[2].tmp().isFP())
6067OPGEN_RETURN(false);
6068OPGEN_RETURN(true);
6069break;
6070break;
6071default:
6072break;
6073}
6074break;
6075case Arg::Addr:
6076case Arg::Stack:
6077case Arg::CallArg:
6078switch (this->args[2].kind()) {
6079case Arg::Tmp:
6080#if CPU(X86) || CPU(X86_64)
6081if (!args[0].tmp().isFP())
6082OPGEN_RETURN(false);
6083if (!Arg::isValidAddrForm(args[1].offset()))
6084OPGEN_RETURN(false);
6085if (!args[2].tmp().isFP())
6086OPGEN_RETURN(false);
6087OPGEN_RETURN(true);
6088#endif
6089break;
6090break;
6091default:
6092break;
6093}
6094break;
6095default:
6096break;
6097}
6098break;
6099case Arg::Addr:
6100case Arg::Stack:
6101case Arg::CallArg:
6102switch (this->args[1].kind()) {
6103case Arg::Tmp:
6104switch (this->args[2].kind()) {
6105case Arg::Tmp:
6106#if CPU(X86) || CPU(X86_64)
6107if (!Arg::isValidAddrForm(args[0].offset()))
6108OPGEN_RETURN(false);
6109if (!args[1].tmp().isFP())
6110OPGEN_RETURN(false);
6111if (!args[2].tmp().isFP())
6112OPGEN_RETURN(false);
6113OPGEN_RETURN(true);
6114#endif
6115break;
6116break;
6117default:
6118break;
6119}
6120break;
6121default:
6122break;
6123}
6124break;
6125case Arg::Index:
6126switch (this->args[1].kind()) {
6127case Arg::Tmp:
6128switch (this->args[2].kind()) {
6129case Arg::Tmp:
6130#if CPU(X86) || CPU(X86_64)
6131if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
6132OPGEN_RETURN(false);
6133if (!args[1].tmp().isFP())
6134OPGEN_RETURN(false);
6135if (!args[2].tmp().isFP())
6136OPGEN_RETURN(false);
6137OPGEN_RETURN(true);
6138#endif
6139break;
6140break;
6141default:
6142break;
6143}
6144break;
6145default:
6146break;
6147}
6148break;
6149default:
6150break;
6151}
6152break;
6153case 2:
6154switch (this->args[0].kind()) {
6155case Arg::Tmp:
6156switch (this->args[1].kind()) {
6157case Arg::Tmp:
6158#if CPU(X86) || CPU(X86_64)
6159if (!args[0].tmp().isFP())
6160OPGEN_RETURN(false);
6161if (!args[1].tmp().isFP())
6162OPGEN_RETURN(false);
6163OPGEN_RETURN(true);
6164#endif
6165break;
6166break;
6167default:
6168break;
6169}
6170break;
6171case Arg::Addr:
6172case Arg::Stack:
6173case Arg::CallArg:
6174switch (this->args[1].kind()) {
6175case Arg::Tmp:
6176#if CPU(X86) || CPU(X86_64)
6177if (!Arg::isValidAddrForm(args[0].offset()))
6178OPGEN_RETURN(false);
6179if (!args[1].tmp().isFP())
6180OPGEN_RETURN(false);
6181OPGEN_RETURN(true);
6182#endif
6183break;
6184break;
6185default:
6186break;
6187}
6188break;
6189default:
6190break;
6191}
6192break;
6193default:
6194break;
6195}
6196break;
6197case Opcode::MulFloat:
6198switch (this->args.size()) {
6199case 3:
6200switch (this->args[0].kind()) {
6201case Arg::Tmp:
6202switch (this->args[1].kind()) {
6203case Arg::Tmp:
6204switch (this->args[2].kind()) {
6205case Arg::Tmp:
6206if (!args[0].tmp().isFP())
6207OPGEN_RETURN(false);
6208if (!args[1].tmp().isFP())
6209OPGEN_RETURN(false);
6210if (!args[2].tmp().isFP())
6211OPGEN_RETURN(false);
6212OPGEN_RETURN(true);
6213break;
6214break;
6215default:
6216break;
6217}
6218break;
6219case Arg::Addr:
6220case Arg::Stack:
6221case Arg::CallArg:
6222switch (this->args[2].kind()) {
6223case Arg::Tmp:
6224#if CPU(X86) || CPU(X86_64)
6225if (!args[0].tmp().isFP())
6226OPGEN_RETURN(false);
6227if (!Arg::isValidAddrForm(args[1].offset()))
6228OPGEN_RETURN(false);
6229if (!args[2].tmp().isFP())
6230OPGEN_RETURN(false);
6231OPGEN_RETURN(true);
6232#endif
6233break;
6234break;
6235default:
6236break;
6237}
6238break;
6239default:
6240break;
6241}
6242break;
6243case Arg::Addr:
6244case Arg::Stack:
6245case Arg::CallArg:
6246switch (this->args[1].kind()) {
6247case Arg::Tmp:
6248switch (this->args[2].kind()) {
6249case Arg::Tmp:
6250#if CPU(X86) || CPU(X86_64)
6251if (!Arg::isValidAddrForm(args[0].offset()))
6252OPGEN_RETURN(false);
6253if (!args[1].tmp().isFP())
6254OPGEN_RETURN(false);
6255if (!args[2].tmp().isFP())
6256OPGEN_RETURN(false);
6257OPGEN_RETURN(true);
6258#endif
6259break;
6260break;
6261default:
6262break;
6263}
6264break;
6265default:
6266break;
6267}
6268break;
6269case Arg::Index:
6270switch (this->args[1].kind()) {
6271case Arg::Tmp:
6272switch (this->args[2].kind()) {
6273case Arg::Tmp:
6274#if CPU(X86) || CPU(X86_64)
6275if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6276OPGEN_RETURN(false);
6277if (!args[1].tmp().isFP())
6278OPGEN_RETURN(false);
6279if (!args[2].tmp().isFP())
6280OPGEN_RETURN(false);
6281OPGEN_RETURN(true);
6282#endif
6283break;
6284break;
6285default:
6286break;
6287}
6288break;
6289default:
6290break;
6291}
6292break;
6293default:
6294break;
6295}
6296break;
6297case 2:
6298switch (this->args[0].kind()) {
6299case Arg::Tmp:
6300switch (this->args[1].kind()) {
6301case Arg::Tmp:
6302#if CPU(X86) || CPU(X86_64)
6303if (!args[0].tmp().isFP())
6304OPGEN_RETURN(false);
6305if (!args[1].tmp().isFP())
6306OPGEN_RETURN(false);
6307OPGEN_RETURN(true);
6308#endif
6309break;
6310break;
6311default:
6312break;
6313}
6314break;
6315case Arg::Addr:
6316case Arg::Stack:
6317case Arg::CallArg:
6318switch (this->args[1].kind()) {
6319case Arg::Tmp:
6320#if CPU(X86) || CPU(X86_64)
6321if (!Arg::isValidAddrForm(args[0].offset()))
6322OPGEN_RETURN(false);
6323if (!args[1].tmp().isFP())
6324OPGEN_RETURN(false);
6325OPGEN_RETURN(true);
6326#endif
6327break;
6328break;
6329default:
6330break;
6331}
6332break;
6333default:
6334break;
6335}
6336break;
6337default:
6338break;
6339}
6340break;
6341case Opcode::DivDouble:
6342switch (this->args.size()) {
6343case 3:
6344switch (this->args[0].kind()) {
6345case Arg::Tmp:
6346switch (this->args[1].kind()) {
6347case Arg::Tmp:
6348switch (this->args[2].kind()) {
6349case Arg::Tmp:
6350#if CPU(ARM64)
6351if (!args[0].tmp().isFP())
6352OPGEN_RETURN(false);
6353if (!args[1].tmp().isFP())
6354OPGEN_RETURN(false);
6355if (!args[2].tmp().isFP())
6356OPGEN_RETURN(false);
6357OPGEN_RETURN(true);
6358#endif
6359break;
6360break;
6361default:
6362break;
6363}
6364break;
6365default:
6366break;
6367}
6368break;
6369default:
6370break;
6371}
6372break;
6373case 2:
6374switch (this->args[0].kind()) {
6375case Arg::Tmp:
6376switch (this->args[1].kind()) {
6377case Arg::Tmp:
6378#if CPU(X86) || CPU(X86_64)
6379if (!args[0].tmp().isFP())
6380OPGEN_RETURN(false);
6381if (!args[1].tmp().isFP())
6382OPGEN_RETURN(false);
6383OPGEN_RETURN(true);
6384#endif
6385break;
6386break;
6387default:
6388break;
6389}
6390break;
6391case Arg::Addr:
6392case Arg::Stack:
6393case Arg::CallArg:
6394switch (this->args[1].kind()) {
6395case Arg::Tmp:
6396#if CPU(X86) || CPU(X86_64)
6397if (!Arg::isValidAddrForm(args[0].offset()))
6398OPGEN_RETURN(false);
6399if (!args[1].tmp().isFP())
6400OPGEN_RETURN(false);
6401OPGEN_RETURN(true);
6402#endif
6403break;
6404break;
6405default:
6406break;
6407}
6408break;
6409default:
6410break;
6411}
6412break;
6413default:
6414break;
6415}
6416break;
6417case Opcode::DivFloat:
6418switch (this->args.size()) {
6419case 3:
6420switch (this->args[0].kind()) {
6421case Arg::Tmp:
6422switch (this->args[1].kind()) {
6423case Arg::Tmp:
6424switch (this->args[2].kind()) {
6425case Arg::Tmp:
6426#if CPU(ARM64)
6427if (!args[0].tmp().isFP())
6428OPGEN_RETURN(false);
6429if (!args[1].tmp().isFP())
6430OPGEN_RETURN(false);
6431if (!args[2].tmp().isFP())
6432OPGEN_RETURN(false);
6433OPGEN_RETURN(true);
6434#endif
6435break;
6436break;
6437default:
6438break;
6439}
6440break;
6441default:
6442break;
6443}
6444break;
6445default:
6446break;
6447}
6448break;
6449case 2:
6450switch (this->args[0].kind()) {
6451case Arg::Tmp:
6452switch (this->args[1].kind()) {
6453case Arg::Tmp:
6454#if CPU(X86) || CPU(X86_64)
6455if (!args[0].tmp().isFP())
6456OPGEN_RETURN(false);
6457if (!args[1].tmp().isFP())
6458OPGEN_RETURN(false);
6459OPGEN_RETURN(true);
6460#endif
6461break;
6462break;
6463default:
6464break;
6465}
6466break;
6467case Arg::Addr:
6468case Arg::Stack:
6469case Arg::CallArg:
6470switch (this->args[1].kind()) {
6471case Arg::Tmp:
6472#if CPU(X86) || CPU(X86_64)
6473if (!Arg::isValidAddrForm(args[0].offset()))
6474OPGEN_RETURN(false);
6475if (!args[1].tmp().isFP())
6476OPGEN_RETURN(false);
6477OPGEN_RETURN(true);
6478#endif
6479break;
6480break;
6481default:
6482break;
6483}
6484break;
6485default:
6486break;
6487}
6488break;
6489default:
6490break;
6491}
6492break;
6493case Opcode::X86ConvertToDoubleWord32:
6494switch (this->args.size()) {
6495case 2:
6496switch (this->args[0].kind()) {
6497case Arg::Tmp:
6498switch (this->args[1].kind()) {
6499case Arg::Tmp:
6500#if CPU(X86) || CPU(X86_64)
6501if (!args[0].tmp().isGP())
6502OPGEN_RETURN(false);
6503if (!args[1].tmp().isGP())
6504OPGEN_RETURN(false);
6505if (!isX86ConvertToDoubleWord32Valid(*this))
6506OPGEN_RETURN(false);
6507OPGEN_RETURN(true);
6508#endif
6509break;
6510break;
6511default:
6512break;
6513}
6514break;
6515default:
6516break;
6517}
6518break;
6519default:
6520break;
6521}
6522break;
6523case Opcode::X86ConvertToQuadWord64:
6524switch (this->args.size()) {
6525case 2:
6526switch (this->args[0].kind()) {
6527case Arg::Tmp:
6528switch (this->args[1].kind()) {
6529case Arg::Tmp:
6530#if CPU(X86_64)
6531if (!args[0].tmp().isGP())
6532OPGEN_RETURN(false);
6533if (!args[1].tmp().isGP())
6534OPGEN_RETURN(false);
6535if (!isX86ConvertToQuadWord64Valid(*this))
6536OPGEN_RETURN(false);
6537OPGEN_RETURN(true);
6538#endif
6539break;
6540break;
6541default:
6542break;
6543}
6544break;
6545default:
6546break;
6547}
6548break;
6549default:
6550break;
6551}
6552break;
6553case Opcode::X86Div32:
6554switch (this->args.size()) {
6555case 3:
6556switch (this->args[0].kind()) {
6557case Arg::Tmp:
6558switch (this->args[1].kind()) {
6559case Arg::Tmp:
6560switch (this->args[2].kind()) {
6561case Arg::Tmp:
6562#if CPU(X86) || CPU(X86_64)
6563if (!args[0].tmp().isGP())
6564OPGEN_RETURN(false);
6565if (!args[1].tmp().isGP())
6566OPGEN_RETURN(false);
6567if (!args[2].tmp().isGP())
6568OPGEN_RETURN(false);
6569if (!isX86Div32Valid(*this))
6570OPGEN_RETURN(false);
6571OPGEN_RETURN(true);
6572#endif
6573break;
6574break;
6575default:
6576break;
6577}
6578break;
6579default:
6580break;
6581}
6582break;
6583default:
6584break;
6585}
6586break;
6587default:
6588break;
6589}
6590break;
6591case Opcode::X86UDiv32:
6592switch (this->args.size()) {
6593case 3:
6594switch (this->args[0].kind()) {
6595case Arg::Tmp:
6596switch (this->args[1].kind()) {
6597case Arg::Tmp:
6598switch (this->args[2].kind()) {
6599case Arg::Tmp:
6600#if CPU(X86) || CPU(X86_64)
6601if (!args[0].tmp().isGP())
6602OPGEN_RETURN(false);
6603if (!args[1].tmp().isGP())
6604OPGEN_RETURN(false);
6605if (!args[2].tmp().isGP())
6606OPGEN_RETURN(false);
6607if (!isX86UDiv32Valid(*this))
6608OPGEN_RETURN(false);
6609OPGEN_RETURN(true);
6610#endif
6611break;
6612break;
6613default:
6614break;
6615}
6616break;
6617default:
6618break;
6619}
6620break;
6621default:
6622break;
6623}
6624break;
6625default:
6626break;
6627}
6628break;
6629case Opcode::X86Div64:
6630switch (this->args.size()) {
6631case 3:
6632switch (this->args[0].kind()) {
6633case Arg::Tmp:
6634switch (this->args[1].kind()) {
6635case Arg::Tmp:
6636switch (this->args[2].kind()) {
6637case Arg::Tmp:
6638#if CPU(X86_64)
6639if (!args[0].tmp().isGP())
6640OPGEN_RETURN(false);
6641if (!args[1].tmp().isGP())
6642OPGEN_RETURN(false);
6643if (!args[2].tmp().isGP())
6644OPGEN_RETURN(false);
6645if (!isX86Div64Valid(*this))
6646OPGEN_RETURN(false);
6647OPGEN_RETURN(true);
6648#endif
6649break;
6650break;
6651default:
6652break;
6653}
6654break;
6655default:
6656break;
6657}
6658break;
6659default:
6660break;
6661}
6662break;
6663default:
6664break;
6665}
6666break;
6667case Opcode::X86UDiv64:
6668switch (this->args.size()) {
6669case 3:
6670switch (this->args[0].kind()) {
6671case Arg::Tmp:
6672switch (this->args[1].kind()) {
6673case Arg::Tmp:
6674switch (this->args[2].kind()) {
6675case Arg::Tmp:
6676#if CPU(X86_64)
6677if (!args[0].tmp().isGP())
6678OPGEN_RETURN(false);
6679if (!args[1].tmp().isGP())
6680OPGEN_RETURN(false);
6681if (!args[2].tmp().isGP())
6682OPGEN_RETURN(false);
6683if (!isX86UDiv64Valid(*this))
6684OPGEN_RETURN(false);
6685OPGEN_RETURN(true);
6686#endif
6687break;
6688break;
6689default:
6690break;
6691}
6692break;
6693default:
6694break;
6695}
6696break;
6697default:
6698break;
6699}
6700break;
6701default:
6702break;
6703}
6704break;
6705case Opcode::Lea32:
6706switch (this->args.size()) {
6707case 2:
6708switch (this->args[0].kind()) {
6709case Arg::Addr:
6710case Arg::Stack:
6711case Arg::CallArg:
6712switch (this->args[1].kind()) {
6713case Arg::Tmp:
6714if (args[0].isStack() && args[0].stackSlot()->isSpill())
6715OPGEN_RETURN(false);
6716if (!Arg::isValidAddrForm(args[0].offset()))
6717OPGEN_RETURN(false);
6718if (!args[1].tmp().isGP())
6719OPGEN_RETURN(false);
6720OPGEN_RETURN(true);
6721break;
6722break;
6723default:
6724break;
6725}
6726break;
6727case Arg::Index:
6728switch (this->args[1].kind()) {
6729case Arg::Tmp:
6730#if CPU(X86) || CPU(X86_64)
6731if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6732OPGEN_RETURN(false);
6733if (!args[1].tmp().isGP())
6734OPGEN_RETURN(false);
6735OPGEN_RETURN(true);
6736#endif
6737break;
6738break;
6739default:
6740break;
6741}
6742break;
6743default:
6744break;
6745}
6746break;
6747default:
6748break;
6749}
6750break;
6751case Opcode::Lea64:
6752switch (this->args.size()) {
6753case 2:
6754switch (this->args[0].kind()) {
6755case Arg::Addr:
6756case Arg::Stack:
6757case Arg::CallArg:
6758switch (this->args[1].kind()) {
6759case Arg::Tmp:
6760if (args[0].isStack() && args[0].stackSlot()->isSpill())
6761OPGEN_RETURN(false);
6762if (!Arg::isValidAddrForm(args[0].offset()))
6763OPGEN_RETURN(false);
6764if (!args[1].tmp().isGP())
6765OPGEN_RETURN(false);
6766OPGEN_RETURN(true);
6767break;
6768break;
6769default:
6770break;
6771}
6772break;
6773case Arg::Index:
6774switch (this->args[1].kind()) {
6775case Arg::Tmp:
6776#if CPU(X86) || CPU(X86_64)
6777if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
6778OPGEN_RETURN(false);
6779if (!args[1].tmp().isGP())
6780OPGEN_RETURN(false);
6781OPGEN_RETURN(true);
6782#endif
6783break;
6784break;
6785default:
6786break;
6787}
6788break;
6789default:
6790break;
6791}
6792break;
6793default:
6794break;
6795}
6796break;
6797case Opcode::And32:
6798switch (this->args.size()) {
6799case 3:
6800switch (this->args[0].kind()) {
6801case Arg::Tmp:
6802switch (this->args[1].kind()) {
6803case Arg::Tmp:
6804switch (this->args[2].kind()) {
6805case Arg::Tmp:
6806if (!args[0].tmp().isGP())
6807OPGEN_RETURN(false);
6808if (!args[1].tmp().isGP())
6809OPGEN_RETURN(false);
6810if (!args[2].tmp().isGP())
6811OPGEN_RETURN(false);
6812OPGEN_RETURN(true);
6813break;
6814break;
6815default:
6816break;
6817}
6818break;
6819case Arg::Addr:
6820case Arg::Stack:
6821case Arg::CallArg:
6822switch (this->args[2].kind()) {
6823case Arg::Tmp:
6824#if CPU(X86) || CPU(X86_64)
6825if (!args[0].tmp().isGP())
6826OPGEN_RETURN(false);
6827if (!Arg::isValidAddrForm(args[1].offset()))
6828OPGEN_RETURN(false);
6829if (!args[2].tmp().isGP())
6830OPGEN_RETURN(false);
6831OPGEN_RETURN(true);
6832#endif
6833break;
6834break;
6835default:
6836break;
6837}
6838break;
6839default:
6840break;
6841}
6842break;
6843case Arg::BitImm:
6844switch (this->args[1].kind()) {
6845case Arg::Tmp:
6846switch (this->args[2].kind()) {
6847case Arg::Tmp:
6848#if CPU(ARM64)
6849if (!Arg::isValidBitImmForm(args[0].value()))
6850OPGEN_RETURN(false);
6851if (!args[1].tmp().isGP())
6852OPGEN_RETURN(false);
6853if (!args[2].tmp().isGP())
6854OPGEN_RETURN(false);
6855OPGEN_RETURN(true);
6856#endif
6857break;
6858break;
6859default:
6860break;
6861}
6862break;
6863default:
6864break;
6865}
6866break;
6867case Arg::Addr:
6868case Arg::Stack:
6869case Arg::CallArg:
6870switch (this->args[1].kind()) {
6871case Arg::Tmp:
6872switch (this->args[2].kind()) {
6873case Arg::Tmp:
6874#if CPU(X86) || CPU(X86_64)
6875if (!Arg::isValidAddrForm(args[0].offset()))
6876OPGEN_RETURN(false);
6877if (!args[1].tmp().isGP())
6878OPGEN_RETURN(false);
6879if (!args[2].tmp().isGP())
6880OPGEN_RETURN(false);
6881OPGEN_RETURN(true);
6882#endif
6883break;
6884break;
6885default:
6886break;
6887}
6888break;
6889default:
6890break;
6891}
6892break;
6893default:
6894break;
6895}
6896break;
6897case 2:
6898switch (this->args[0].kind()) {
6899case Arg::Tmp:
6900switch (this->args[1].kind()) {
6901case Arg::Tmp:
6902if (!args[0].tmp().isGP())
6903OPGEN_RETURN(false);
6904if (!args[1].tmp().isGP())
6905OPGEN_RETURN(false);
6906OPGEN_RETURN(true);
6907break;
6908break;
6909case Arg::Addr:
6910case Arg::Stack:
6911case Arg::CallArg:
6912#if CPU(X86) || CPU(X86_64)
6913if (!args[0].tmp().isGP())
6914OPGEN_RETURN(false);
6915if (!Arg::isValidAddrForm(args[1].offset()))
6916OPGEN_RETURN(false);
6917OPGEN_RETURN(true);
6918#endif
6919break;
6920break;
6921case Arg::Index:
6922#if CPU(X86) || CPU(X86_64)
6923if (!args[0].tmp().isGP())
6924OPGEN_RETURN(false);
6925if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
6926OPGEN_RETURN(false);
6927OPGEN_RETURN(true);
6928#endif
6929break;
6930break;
6931default:
6932break;
6933}
6934break;
6935case Arg::Imm:
6936switch (this->args[1].kind()) {
6937case Arg::Tmp:
6938#if CPU(X86) || CPU(X86_64)
6939if (!Arg::isValidImmForm(args[0].value()))
6940OPGEN_RETURN(false);
6941if (!args[1].tmp().isGP())
6942OPGEN_RETURN(false);
6943OPGEN_RETURN(true);
6944#endif
6945break;
6946break;
6947case Arg::Addr:
6948case Arg::Stack:
6949case Arg::CallArg:
6950#if CPU(X86) || CPU(X86_64)
6951if (!Arg::isValidImmForm(args[0].value()))
6952OPGEN_RETURN(false);
6953if (!Arg::isValidAddrForm(args[1].offset()))
6954OPGEN_RETURN(false);
6955OPGEN_RETURN(true);
6956#endif
6957break;
6958break;
6959case Arg::Index:
6960#if CPU(X86) || CPU(X86_64)
6961if (!Arg::isValidImmForm(args[0].value()))
6962OPGEN_RETURN(false);
6963if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
6964OPGEN_RETURN(false);
6965OPGEN_RETURN(true);
6966#endif
6967break;
6968break;
6969default:
6970break;
6971}
6972break;
6973case Arg::Addr:
6974case Arg::Stack:
6975case Arg::CallArg:
6976switch (this->args[1].kind()) {
6977case Arg::Tmp:
6978#if CPU(X86) || CPU(X86_64)
6979if (!Arg::isValidAddrForm(args[0].offset()))
6980OPGEN_RETURN(false);
6981if (!args[1].tmp().isGP())
6982OPGEN_RETURN(false);
6983OPGEN_RETURN(true);
6984#endif
6985break;
6986break;
6987default:
6988break;
6989}
6990break;
6991case Arg::Index:
6992switch (this->args[1].kind()) {
6993case Arg::Tmp:
6994#if CPU(X86) || CPU(X86_64)
6995if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6996OPGEN_RETURN(false);
6997if (!args[1].tmp().isGP())
6998OPGEN_RETURN(false);
6999OPGEN_RETURN(true);
7000#endif
7001break;
7002break;
7003default:
7004break;
7005}
7006break;
7007default:
7008break;
7009}
7010break;
7011default:
7012break;
7013}
7014break;
7015case Opcode::And64:
7016switch (this->args.size()) {
7017case 3:
7018switch (this->args[0].kind()) {
7019case Arg::Tmp:
7020switch (this->args[1].kind()) {
7021case Arg::Tmp:
7022switch (this->args[2].kind()) {
7023case Arg::Tmp:
7024#if CPU(X86_64) || CPU(ARM64)
7025if (!args[0].tmp().isGP())
7026OPGEN_RETURN(false);
7027if (!args[1].tmp().isGP())
7028OPGEN_RETURN(false);
7029if (!args[2].tmp().isGP())
7030OPGEN_RETURN(false);
7031OPGEN_RETURN(true);
7032#endif
7033break;
7034break;
7035default:
7036break;
7037}
7038break;
7039default:
7040break;
7041}
7042break;
7043#if USE(JSVALUE64)
7044case Arg::BitImm64:
7045switch (this->args[1].kind()) {
7046case Arg::Tmp:
7047switch (this->args[2].kind()) {
7048case Arg::Tmp:
7049#if CPU(ARM64)
7050if (!Arg::isValidBitImm64Form(args[0].value()))
7051OPGEN_RETURN(false);
7052if (!args[1].tmp().isGP())
7053OPGEN_RETURN(false);
7054if (!args[2].tmp().isGP())
7055OPGEN_RETURN(false);
7056OPGEN_RETURN(true);
7057#endif
7058break;
7059break;
7060default:
7061break;
7062}
7063break;
7064default:
7065break;
7066}
7067break;
7068#endif // USE(JSVALUE64)
7069default:
7070break;
7071}
7072break;
7073case 2:
7074switch (this->args[0].kind()) {
7075case Arg::Tmp:
7076switch (this->args[1].kind()) {
7077case Arg::Tmp:
7078#if CPU(X86_64)
7079if (!args[0].tmp().isGP())
7080OPGEN_RETURN(false);
7081if (!args[1].tmp().isGP())
7082OPGEN_RETURN(false);
7083OPGEN_RETURN(true);
7084#endif
7085break;
7086break;
7087case Arg::Addr:
7088case Arg::Stack:
7089case Arg::CallArg:
7090#if CPU(X86_64)
7091if (!args[0].tmp().isGP())
7092OPGEN_RETURN(false);
7093if (!Arg::isValidAddrForm(args[1].offset()))
7094OPGEN_RETURN(false);
7095OPGEN_RETURN(true);
7096#endif
7097break;
7098break;
7099case Arg::Index:
7100#if CPU(X86_64)
7101if (!args[0].tmp().isGP())
7102OPGEN_RETURN(false);
7103if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
7104OPGEN_RETURN(false);
7105OPGEN_RETURN(true);
7106#endif
7107break;
7108break;
7109default:
7110break;
7111}
7112break;
7113case Arg::Imm:
7114switch (this->args[1].kind()) {
7115case Arg::Tmp:
7116#if CPU(X86_64)
7117if (!Arg::isValidImmForm(args[0].value()))
7118OPGEN_RETURN(false);
7119if (!args[1].tmp().isGP())
7120OPGEN_RETURN(false);
7121OPGEN_RETURN(true);
7122#endif
7123break;
7124break;
7125case Arg::Addr:
7126case Arg::Stack:
7127case Arg::CallArg:
7128#if CPU(X86_64)
7129if (!Arg::isValidImmForm(args[0].value()))
7130OPGEN_RETURN(false);
7131if (!Arg::isValidAddrForm(args[1].offset()))
7132OPGEN_RETURN(false);
7133OPGEN_RETURN(true);
7134#endif
7135break;
7136break;
7137case Arg::Index:
7138#if CPU(X86_64)
7139if (!Arg::isValidImmForm(args[0].value()))
7140OPGEN_RETURN(false);
7141if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
7142OPGEN_RETURN(false);
7143OPGEN_RETURN(true);
7144#endif
7145break;
7146break;
7147default:
7148break;
7149}
7150break;
7151case Arg::Addr:
7152case Arg::Stack:
7153case Arg::CallArg:
7154switch (this->args[1].kind()) {
7155case Arg::Tmp:
7156#if CPU(X86_64)
7157if (!Arg::isValidAddrForm(args[0].offset()))
7158OPGEN_RETURN(false);
7159if (!args[1].tmp().isGP())
7160OPGEN_RETURN(false);
7161OPGEN_RETURN(true);
7162#endif
7163break;
7164break;
7165default:
7166break;
7167}
7168break;
7169case Arg::Index:
7170switch (this->args[1].kind()) {
7171case Arg::Tmp:
7172#if CPU(X86_64)
7173if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
7174OPGEN_RETURN(false);
7175if (!args[1].tmp().isGP())
7176OPGEN_RETURN(false);
7177OPGEN_RETURN(true);
7178#endif
7179break;
7180break;
7181default:
7182break;
7183}
7184break;
7185default:
7186break;
7187}
7188break;
7189default:
7190break;
7191}
7192break;
7193case Opcode::AndDouble:
7194switch (this->args.size()) {
7195case 3:
7196switch (this->args[0].kind()) {
7197case Arg::Tmp:
7198switch (this->args[1].kind()) {
7199case Arg::Tmp:
7200switch (this->args[2].kind()) {
7201case Arg::Tmp:
7202if (!args[0].tmp().isFP())
7203OPGEN_RETURN(false);
7204if (!args[1].tmp().isFP())
7205OPGEN_RETURN(false);
7206if (!args[2].tmp().isFP())
7207OPGEN_RETURN(false);
7208OPGEN_RETURN(true);
7209break;
7210break;
7211default:
7212break;
7213}
7214break;
7215default:
7216break;
7217}
7218break;
7219default:
7220break;
7221}
7222break;
7223case 2:
7224switch (this->args[0].kind()) {
7225case Arg::Tmp:
7226switch (this->args[1].kind()) {
7227case Arg::Tmp:
7228#if CPU(X86) || CPU(X86_64)
7229if (!args[0].tmp().isFP())
7230OPGEN_RETURN(false);
7231if (!args[1].tmp().isFP())
7232OPGEN_RETURN(false);
7233OPGEN_RETURN(true);
7234#endif
7235break;
7236break;
7237default:
7238break;
7239}
7240break;
7241default:
7242break;
7243}
7244break;
7245default:
7246break;
7247}
7248break;
7249case Opcode::AndFloat:
7250switch (this->args.size()) {
7251case 3:
7252switch (this->args[0].kind()) {
7253case Arg::Tmp:
7254switch (this->args[1].kind()) {
7255case Arg::Tmp:
7256switch (this->args[2].kind()) {
7257case Arg::Tmp:
7258if (!args[0].tmp().isFP())
7259OPGEN_RETURN(false);
7260if (!args[1].tmp().isFP())
7261OPGEN_RETURN(false);
7262if (!args[2].tmp().isFP())
7263OPGEN_RETURN(false);
7264OPGEN_RETURN(true);
7265break;
7266break;
7267default:
7268break;
7269}
7270break;
7271default:
7272break;
7273}
7274break;
7275default:
7276break;
7277}
7278break;
7279case 2:
7280switch (this->args[0].kind()) {
7281case Arg::Tmp:
7282switch (this->args[1].kind()) {
7283case Arg::Tmp:
7284#if CPU(X86) || CPU(X86_64)
7285if (!args[0].tmp().isFP())
7286OPGEN_RETURN(false);
7287if (!args[1].tmp().isFP())
7288OPGEN_RETURN(false);
7289OPGEN_RETURN(true);
7290#endif
7291break;
7292break;
7293default:
7294break;
7295}
7296break;
7297default:
7298break;
7299}
7300break;
7301default:
7302break;
7303}
7304break;
7305case Opcode::OrDouble:
7306switch (this->args.size()) {
7307case 3:
7308switch (this->args[0].kind()) {
7309case Arg::Tmp:
7310switch (this->args[1].kind()) {
7311case Arg::Tmp:
7312switch (this->args[2].kind()) {
7313case Arg::Tmp:
7314if (!args[0].tmp().isFP())
7315OPGEN_RETURN(false);
7316if (!args[1].tmp().isFP())
7317OPGEN_RETURN(false);
7318if (!args[2].tmp().isFP())
7319OPGEN_RETURN(false);
7320OPGEN_RETURN(true);
7321break;
7322break;
7323default:
7324break;
7325}
7326break;
7327default:
7328break;
7329}
7330break;
7331default:
7332break;
7333}
7334break;
7335case 2:
7336switch (this->args[0].kind()) {
7337case Arg::Tmp:
7338switch (this->args[1].kind()) {
7339case Arg::Tmp:
7340#if CPU(X86) || CPU(X86_64)
7341if (!args[0].tmp().isFP())
7342OPGEN_RETURN(false);
7343if (!args[1].tmp().isFP())
7344OPGEN_RETURN(false);
7345OPGEN_RETURN(true);
7346#endif
7347break;
7348break;
7349default:
7350break;
7351}
7352break;
7353default:
7354break;
7355}
7356break;
7357default:
7358break;
7359}
7360break;
7361case Opcode::OrFloat:
7362switch (this->args.size()) {
7363case 3:
7364switch (this->args[0].kind()) {
7365case Arg::Tmp:
7366switch (this->args[1].kind()) {
7367case Arg::Tmp:
7368switch (this->args[2].kind()) {
7369case Arg::Tmp:
7370if (!args[0].tmp().isFP())
7371OPGEN_RETURN(false);
7372if (!args[1].tmp().isFP())
7373OPGEN_RETURN(false);
7374if (!args[2].tmp().isFP())
7375OPGEN_RETURN(false);
7376OPGEN_RETURN(true);
7377break;
7378break;
7379default:
7380break;
7381}
7382break;
7383default:
7384break;
7385}
7386break;
7387default:
7388break;
7389}
7390break;
7391case 2:
7392switch (this->args[0].kind()) {
7393case Arg::Tmp:
7394switch (this->args[1].kind()) {
7395case Arg::Tmp:
7396#if CPU(X86) || CPU(X86_64)
7397if (!args[0].tmp().isFP())
7398OPGEN_RETURN(false);
7399if (!args[1].tmp().isFP())
7400OPGEN_RETURN(false);
7401OPGEN_RETURN(true);
7402#endif
7403break;
7404break;
7405default:
7406break;
7407}
7408break;
7409default:
7410break;
7411}
7412break;
7413default:
7414break;
7415}
7416break;
7417case Opcode::XorDouble:
7418switch (this->args.size()) {
7419case 3:
7420switch (this->args[0].kind()) {
7421case Arg::Tmp:
7422switch (this->args[1].kind()) {
7423case Arg::Tmp:
7424switch (this->args[2].kind()) {
7425case Arg::Tmp:
7426#if CPU(X86) || CPU(X86_64)
7427if (!args[0].tmp().isFP())
7428OPGEN_RETURN(false);
7429if (!args[1].tmp().isFP())
7430OPGEN_RETURN(false);
7431if (!args[2].tmp().isFP())
7432OPGEN_RETURN(false);
7433OPGEN_RETURN(true);
7434#endif
7435break;
7436break;
7437default:
7438break;
7439}
7440break;
7441default:
7442break;
7443}
7444break;
7445default:
7446break;
7447}
7448break;
7449case 2:
7450switch (this->args[0].kind()) {
7451case Arg::Tmp:
7452switch (this->args[1].kind()) {
7453case Arg::Tmp:
7454#if CPU(X86) || CPU(X86_64)
7455if (!args[0].tmp().isFP())
7456OPGEN_RETURN(false);
7457if (!args[1].tmp().isFP())
7458OPGEN_RETURN(false);
7459OPGEN_RETURN(true);
7460#endif
7461break;
7462break;
7463default:
7464break;
7465}
7466break;
7467default:
7468break;
7469}
7470break;
7471default:
7472break;
7473}
7474break;
7475case Opcode::XorFloat:
7476switch (this->args.size()) {
7477case 3:
7478switch (this->args[0].kind()) {
7479case Arg::Tmp:
7480switch (this->args[1].kind()) {
7481case Arg::Tmp:
7482switch (this->args[2].kind()) {
7483case Arg::Tmp:
7484#if CPU(X86) || CPU(X86_64)
7485if (!args[0].tmp().isFP())
7486OPGEN_RETURN(false);
7487if (!args[1].tmp().isFP())
7488OPGEN_RETURN(false);
7489if (!args[2].tmp().isFP())
7490OPGEN_RETURN(false);
7491OPGEN_RETURN(true);
7492#endif
7493break;
7494break;
7495default:
7496break;
7497}
7498break;
7499default:
7500break;
7501}
7502break;
7503default:
7504break;
7505}
7506break;
7507case 2:
7508switch (this->args[0].kind()) {
7509case Arg::Tmp:
7510switch (this->args[1].kind()) {
7511case Arg::Tmp:
7512#if CPU(X86) || CPU(X86_64)
7513if (!args[0].tmp().isFP())
7514OPGEN_RETURN(false);
7515if (!args[1].tmp().isFP())
7516OPGEN_RETURN(false);
7517OPGEN_RETURN(true);
7518#endif
7519break;
7520break;
7521default:
7522break;
7523}
7524break;
7525default:
7526break;
7527}
7528break;
7529default:
7530break;
7531}
7532break;
7533case Opcode::Lshift32:
7534switch (this->args.size()) {
7535case 3:
7536switch (this->args[0].kind()) {
7537case Arg::Tmp:
7538switch (this->args[1].kind()) {
7539case Arg::Tmp:
7540switch (this->args[2].kind()) {
7541case Arg::Tmp:
7542#if CPU(ARM64)
7543if (!args[0].tmp().isGP())
7544OPGEN_RETURN(false);
7545if (!args[1].tmp().isGP())
7546OPGEN_RETURN(false);
7547if (!args[2].tmp().isGP())
7548OPGEN_RETURN(false);
7549OPGEN_RETURN(true);
7550#endif
7551break;
7552break;
7553default:
7554break;
7555}
7556break;
7557case Arg::Imm:
7558switch (this->args[2].kind()) {
7559case Arg::Tmp:
7560#if CPU(ARM64)
7561if (!args[0].tmp().isGP())
7562OPGEN_RETURN(false);
7563if (!Arg::isValidImmForm(args[1].value()))
7564OPGEN_RETURN(false);
7565if (!args[2].tmp().isGP())
7566OPGEN_RETURN(false);
7567OPGEN_RETURN(true);
7568#endif
7569break;
7570break;
7571default:
7572break;
7573}
7574break;
7575default:
7576break;
7577}
7578break;
7579default:
7580break;
7581}
7582break;
7583case 2:
7584switch (this->args[0].kind()) {
7585case Arg::Tmp:
7586switch (this->args[1].kind()) {
7587case Arg::Tmp:
7588#if CPU(X86) || CPU(X86_64)
7589if (!args[0].tmp().isGP())
7590OPGEN_RETURN(false);
7591if (!args[1].tmp().isGP())
7592OPGEN_RETURN(false);
7593if (!isLshift32Valid(*this))
7594OPGEN_RETURN(false);
7595OPGEN_RETURN(true);
7596#endif
7597break;
7598break;
7599default:
7600break;
7601}
7602break;
7603case Arg::Imm:
7604switch (this->args[1].kind()) {
7605case Arg::Tmp:
7606#if CPU(X86) || CPU(X86_64)
7607if (!Arg::isValidImmForm(args[0].value()))
7608OPGEN_RETURN(false);
7609if (!args[1].tmp().isGP())
7610OPGEN_RETURN(false);
7611OPGEN_RETURN(true);
7612#endif
7613break;
7614break;
7615default:
7616break;
7617}
7618break;
7619default:
7620break;
7621}
7622break;
7623default:
7624break;
7625}
7626break;
7627case Opcode::Lshift64:
7628switch (this->args.size()) {
7629case 3:
7630switch (this->args[0].kind()) {
7631case Arg::Tmp:
7632switch (this->args[1].kind()) {
7633case Arg::Tmp:
7634switch (this->args[2].kind()) {
7635case Arg::Tmp:
7636#if CPU(ARM64)
7637if (!args[0].tmp().isGP())
7638OPGEN_RETURN(false);
7639if (!args[1].tmp().isGP())
7640OPGEN_RETURN(false);
7641if (!args[2].tmp().isGP())
7642OPGEN_RETURN(false);
7643OPGEN_RETURN(true);
7644#endif
7645break;
7646break;
7647default:
7648break;
7649}
7650break;
7651case Arg::Imm:
7652switch (this->args[2].kind()) {
7653case Arg::Tmp:
7654#if CPU(ARM64)
7655if (!args[0].tmp().isGP())
7656OPGEN_RETURN(false);
7657if (!Arg::isValidImmForm(args[1].value()))
7658OPGEN_RETURN(false);
7659if (!args[2].tmp().isGP())
7660OPGEN_RETURN(false);
7661OPGEN_RETURN(true);
7662#endif
7663break;
7664break;
7665default:
7666break;
7667}
7668break;
7669default:
7670break;
7671}
7672break;
7673default:
7674break;
7675}
7676break;
7677case 2:
7678switch (this->args[0].kind()) {
7679case Arg::Tmp:
7680switch (this->args[1].kind()) {
7681case Arg::Tmp:
7682#if CPU(X86_64)
7683if (!args[0].tmp().isGP())
7684OPGEN_RETURN(false);
7685if (!args[1].tmp().isGP())
7686OPGEN_RETURN(false);
7687if (!isLshift64Valid(*this))
7688OPGEN_RETURN(false);
7689OPGEN_RETURN(true);
7690#endif
7691break;
7692break;
7693default:
7694break;
7695}
7696break;
7697case Arg::Imm:
7698switch (this->args[1].kind()) {
7699case Arg::Tmp:
7700#if CPU(X86_64)
7701if (!Arg::isValidImmForm(args[0].value()))
7702OPGEN_RETURN(false);
7703if (!args[1].tmp().isGP())
7704OPGEN_RETURN(false);
7705OPGEN_RETURN(true);
7706#endif
7707break;
7708break;
7709default:
7710break;
7711}
7712break;
7713default:
7714break;
7715}
7716break;
7717default:
7718break;
7719}
7720break;
7721case Opcode::Rshift32:
7722switch (this->args.size()) {
7723case 3:
7724switch (this->args[0].kind()) {
7725case Arg::Tmp:
7726switch (this->args[1].kind()) {
7727case Arg::Tmp:
7728switch (this->args[2].kind()) {
7729case Arg::Tmp:
7730#if CPU(ARM64)
7731if (!args[0].tmp().isGP())
7732OPGEN_RETURN(false);
7733if (!args[1].tmp().isGP())
7734OPGEN_RETURN(false);
7735if (!args[2].tmp().isGP())
7736OPGEN_RETURN(false);
7737OPGEN_RETURN(true);
7738#endif
7739break;
7740break;
7741default:
7742break;
7743}
7744break;
7745case Arg::Imm:
7746switch (this->args[2].kind()) {
7747case Arg::Tmp:
7748#if CPU(ARM64)
7749if (!args[0].tmp().isGP())
7750OPGEN_RETURN(false);
7751if (!Arg::isValidImmForm(args[1].value()))
7752OPGEN_RETURN(false);
7753if (!args[2].tmp().isGP())
7754OPGEN_RETURN(false);
7755OPGEN_RETURN(true);
7756#endif
7757break;
7758break;
7759default:
7760break;
7761}
7762break;
7763default:
7764break;
7765}
7766break;
7767default:
7768break;
7769}
7770break;
7771case 2:
7772switch (this->args[0].kind()) {
7773case Arg::Tmp:
7774switch (this->args[1].kind()) {
7775case Arg::Tmp:
7776#if CPU(X86) || CPU(X86_64)
7777if (!args[0].tmp().isGP())
7778OPGEN_RETURN(false);
7779if (!args[1].tmp().isGP())
7780OPGEN_RETURN(false);
7781if (!isRshift32Valid(*this))
7782OPGEN_RETURN(false);
7783OPGEN_RETURN(true);
7784#endif
7785break;
7786break;
7787default:
7788break;
7789}
7790break;
7791case Arg::Imm:
7792switch (this->args[1].kind()) {
7793case Arg::Tmp:
7794#if CPU(X86) || CPU(X86_64)
7795if (!Arg::isValidImmForm(args[0].value()))
7796OPGEN_RETURN(false);
7797if (!args[1].tmp().isGP())
7798OPGEN_RETURN(false);
7799OPGEN_RETURN(true);
7800#endif
7801break;
7802break;
7803default:
7804break;
7805}
7806break;
7807default:
7808break;
7809}
7810break;
7811default:
7812break;
7813}
7814break;
7815case Opcode::Rshift64:
7816switch (this->args.size()) {
7817case 3:
7818switch (this->args[0].kind()) {
7819case Arg::Tmp:
7820switch (this->args[1].kind()) {
7821case Arg::Tmp:
7822switch (this->args[2].kind()) {
7823case Arg::Tmp:
7824#if CPU(ARM64)
7825if (!args[0].tmp().isGP())
7826OPGEN_RETURN(false);
7827if (!args[1].tmp().isGP())
7828OPGEN_RETURN(false);
7829if (!args[2].tmp().isGP())
7830OPGEN_RETURN(false);
7831OPGEN_RETURN(true);
7832#endif
7833break;
7834break;
7835default:
7836break;
7837}
7838break;
7839case Arg::Imm:
7840switch (this->args[2].kind()) {
7841case Arg::Tmp:
7842#if CPU(ARM64)
7843if (!args[0].tmp().isGP())
7844OPGEN_RETURN(false);
7845if (!Arg::isValidImmForm(args[1].value()))
7846OPGEN_RETURN(false);
7847if (!args[2].tmp().isGP())
7848OPGEN_RETURN(false);
7849OPGEN_RETURN(true);
7850#endif
7851break;
7852break;
7853default:
7854break;
7855}
7856break;
7857default:
7858break;
7859}
7860break;
7861default:
7862break;
7863}
7864break;
7865case 2:
7866switch (this->args[0].kind()) {
7867case Arg::Tmp:
7868switch (this->args[1].kind()) {
7869case Arg::Tmp:
7870#if CPU(X86_64)
7871if (!args[0].tmp().isGP())
7872OPGEN_RETURN(false);
7873if (!args[1].tmp().isGP())
7874OPGEN_RETURN(false);
7875if (!isRshift64Valid(*this))
7876OPGEN_RETURN(false);
7877OPGEN_RETURN(true);
7878#endif
7879break;
7880break;
7881default:
7882break;
7883}
7884break;
7885case Arg::Imm:
7886switch (this->args[1].kind()) {
7887case Arg::Tmp:
7888#if CPU(X86_64)
7889if (!Arg::isValidImmForm(args[0].value()))
7890OPGEN_RETURN(false);
7891if (!args[1].tmp().isGP())
7892OPGEN_RETURN(false);
7893OPGEN_RETURN(true);
7894#endif
7895break;
7896break;
7897default:
7898break;
7899}
7900break;
7901default:
7902break;
7903}
7904break;
7905default:
7906break;
7907}
7908break;
7909case Opcode::Urshift32:
7910switch (this->args.size()) {
7911case 3:
7912switch (this->args[0].kind()) {
7913case Arg::Tmp:
7914switch (this->args[1].kind()) {
7915case Arg::Tmp:
7916switch (this->args[2].kind()) {
7917case Arg::Tmp:
7918#if CPU(ARM64)
7919if (!args[0].tmp().isGP())
7920OPGEN_RETURN(false);
7921if (!args[1].tmp().isGP())
7922OPGEN_RETURN(false);
7923if (!args[2].tmp().isGP())
7924OPGEN_RETURN(false);
7925OPGEN_RETURN(true);
7926#endif
7927break;
7928break;
7929default:
7930break;
7931}
7932break;
7933case Arg::Imm:
7934switch (this->args[2].kind()) {
7935case Arg::Tmp:
7936#if CPU(ARM64)
7937if (!args[0].tmp().isGP())
7938OPGEN_RETURN(false);
7939if (!Arg::isValidImmForm(args[1].value()))
7940OPGEN_RETURN(false);
7941if (!args[2].tmp().isGP())
7942OPGEN_RETURN(false);
7943OPGEN_RETURN(true);
7944#endif
7945break;
7946break;
7947default:
7948break;
7949}
7950break;
7951default:
7952break;
7953}
7954break;
7955default:
7956break;
7957}
7958break;
7959case 2:
7960switch (this->args[0].kind()) {
7961case Arg::Tmp:
7962switch (this->args[1].kind()) {
7963case Arg::Tmp:
7964#if CPU(X86) || CPU(X86_64)
7965if (!args[0].tmp().isGP())
7966OPGEN_RETURN(false);
7967if (!args[1].tmp().isGP())
7968OPGEN_RETURN(false);
7969if (!isUrshift32Valid(*this))
7970OPGEN_RETURN(false);
7971OPGEN_RETURN(true);
7972#endif
7973break;
7974break;
7975default:
7976break;
7977}
7978break;
7979case Arg::Imm:
7980switch (this->args[1].kind()) {
7981case Arg::Tmp:
7982#if CPU(X86) || CPU(X86_64)
7983if (!Arg::isValidImmForm(args[0].value()))
7984OPGEN_RETURN(false);
7985if (!args[1].tmp().isGP())
7986OPGEN_RETURN(false);
7987OPGEN_RETURN(true);
7988#endif
7989break;
7990break;
7991default:
7992break;
7993}
7994break;
7995default:
7996break;
7997}
7998break;
7999default:
8000break;
8001}
8002break;
8003case Opcode::Urshift64:
8004switch (this->args.size()) {
8005case 3:
8006switch (this->args[0].kind()) {
8007case Arg::Tmp:
8008switch (this->args[1].kind()) {
8009case Arg::Tmp:
8010switch (this->args[2].kind()) {
8011case Arg::Tmp:
8012#if CPU(ARM64)
8013if (!args[0].tmp().isGP())
8014OPGEN_RETURN(false);
8015if (!args[1].tmp().isGP())
8016OPGEN_RETURN(false);
8017if (!args[2].tmp().isGP())
8018OPGEN_RETURN(false);
8019OPGEN_RETURN(true);
8020#endif
8021break;
8022break;
8023default:
8024break;
8025}
8026break;
8027case Arg::Imm:
8028switch (this->args[2].kind()) {
8029case Arg::Tmp:
8030#if CPU(ARM64)
8031if (!args[0].tmp().isGP())
8032OPGEN_RETURN(false);
8033if (!Arg::isValidImmForm(args[1].value()))
8034OPGEN_RETURN(false);
8035if (!args[2].tmp().isGP())
8036OPGEN_RETURN(false);
8037OPGEN_RETURN(true);
8038#endif
8039break;
8040break;
8041default:
8042break;
8043}
8044break;
8045default:
8046break;
8047}
8048break;
8049default:
8050break;
8051}
8052break;
8053case 2:
8054switch (this->args[0].kind()) {
8055case Arg::Tmp:
8056switch (this->args[1].kind()) {
8057case Arg::Tmp:
8058#if CPU(X86_64)
8059if (!args[0].tmp().isGP())
8060OPGEN_RETURN(false);
8061if (!args[1].tmp().isGP())
8062OPGEN_RETURN(false);
8063if (!isUrshift64Valid(*this))
8064OPGEN_RETURN(false);
8065OPGEN_RETURN(true);
8066#endif
8067break;
8068break;
8069default:
8070break;
8071}
8072break;
8073case Arg::Imm:
8074switch (this->args[1].kind()) {
8075case Arg::Tmp:
8076#if CPU(X86_64)
8077if (!Arg::isValidImmForm(args[0].value()))
8078OPGEN_RETURN(false);
8079if (!args[1].tmp().isGP())
8080OPGEN_RETURN(false);
8081OPGEN_RETURN(true);
8082#endif
8083break;
8084break;
8085default:
8086break;
8087}
8088break;
8089default:
8090break;
8091}
8092break;
8093default:
8094break;
8095}
8096break;
8097case Opcode::RotateRight32:
8098switch (this->args.size()) {
8099case 2:
8100switch (this->args[0].kind()) {
8101case Arg::Tmp:
8102switch (this->args[1].kind()) {
8103case Arg::Tmp:
8104#if CPU(X86_64)
8105if (!args[0].tmp().isGP())
8106OPGEN_RETURN(false);
8107if (!args[1].tmp().isGP())
8108OPGEN_RETURN(false);
8109if (!isRotateRight32Valid(*this))
8110OPGEN_RETURN(false);
8111OPGEN_RETURN(true);
8112#endif
8113break;
8114break;
8115default:
8116break;
8117}
8118break;
8119case Arg::Imm:
8120switch (this->args[1].kind()) {
8121case Arg::Tmp:
8122#if CPU(X86_64)
8123if (!Arg::isValidImmForm(args[0].value()))
8124OPGEN_RETURN(false);
8125if (!args[1].tmp().isGP())
8126OPGEN_RETURN(false);
8127OPGEN_RETURN(true);
8128#endif
8129break;
8130break;
8131default:
8132break;
8133}
8134break;
8135default:
8136break;
8137}
8138break;
8139case 3:
8140switch (this->args[0].kind()) {
8141case Arg::Tmp:
8142switch (this->args[1].kind()) {
8143case Arg::Tmp:
8144switch (this->args[2].kind()) {
8145case Arg::Tmp:
8146#if CPU(ARM64)
8147if (!args[0].tmp().isGP())
8148OPGEN_RETURN(false);
8149if (!args[1].tmp().isGP())
8150OPGEN_RETURN(false);
8151if (!args[2].tmp().isGP())
8152OPGEN_RETURN(false);
8153OPGEN_RETURN(true);
8154#endif
8155break;
8156break;
8157default:
8158break;
8159}
8160break;
8161case Arg::Imm:
8162switch (this->args[2].kind()) {
8163case Arg::Tmp:
8164#if CPU(ARM64)
8165if (!args[0].tmp().isGP())
8166OPGEN_RETURN(false);
8167if (!Arg::isValidImmForm(args[1].value()))
8168OPGEN_RETURN(false);
8169if (!args[2].tmp().isGP())
8170OPGEN_RETURN(false);
8171OPGEN_RETURN(true);
8172#endif
8173break;
8174break;
8175default:
8176break;
8177}
8178break;
8179default:
8180break;
8181}
8182break;
8183default:
8184break;
8185}
8186break;
8187default:
8188break;
8189}
8190break;
8191case Opcode::RotateRight64:
8192switch (this->args.size()) {
8193case 2:
8194switch (this->args[0].kind()) {
8195case Arg::Tmp:
8196switch (this->args[1].kind()) {
8197case Arg::Tmp:
8198#if CPU(X86_64)
8199if (!args[0].tmp().isGP())
8200OPGEN_RETURN(false);
8201if (!args[1].tmp().isGP())
8202OPGEN_RETURN(false);
8203if (!isRotateRight64Valid(*this))
8204OPGEN_RETURN(false);
8205OPGEN_RETURN(true);
8206#endif
8207break;
8208break;
8209default:
8210break;
8211}
8212break;
8213case Arg::Imm:
8214switch (this->args[1].kind()) {
8215case Arg::Tmp:
8216#if CPU(X86_64)
8217if (!Arg::isValidImmForm(args[0].value()))
8218OPGEN_RETURN(false);
8219if (!args[1].tmp().isGP())
8220OPGEN_RETURN(false);
8221OPGEN_RETURN(true);
8222#endif
8223break;
8224break;
8225default:
8226break;
8227}
8228break;
8229default:
8230break;
8231}
8232break;
8233case 3:
8234switch (this->args[0].kind()) {
8235case Arg::Tmp:
8236switch (this->args[1].kind()) {
8237case Arg::Tmp:
8238switch (this->args[2].kind()) {
8239case Arg::Tmp:
8240#if CPU(ARM64)
8241if (!args[0].tmp().isGP())
8242OPGEN_RETURN(false);
8243if (!args[1].tmp().isGP())
8244OPGEN_RETURN(false);
8245if (!args[2].tmp().isGP())
8246OPGEN_RETURN(false);
8247OPGEN_RETURN(true);
8248#endif
8249break;
8250break;
8251default:
8252break;
8253}
8254break;
8255case Arg::Imm:
8256switch (this->args[2].kind()) {
8257case Arg::Tmp:
8258#if CPU(ARM64)
8259if (!args[0].tmp().isGP())
8260OPGEN_RETURN(false);
8261if (!Arg::isValidImmForm(args[1].value()))
8262OPGEN_RETURN(false);
8263if (!args[2].tmp().isGP())
8264OPGEN_RETURN(false);
8265OPGEN_RETURN(true);
8266#endif
8267break;
8268break;
8269default:
8270break;
8271}
8272break;
8273default:
8274break;
8275}
8276break;
8277default:
8278break;
8279}
8280break;
8281default:
8282break;
8283}
8284break;
8285case Opcode::RotateLeft32:
8286switch (this->args.size()) {
8287case 2:
8288switch (this->args[0].kind()) {
8289case Arg::Tmp:
8290switch (this->args[1].kind()) {
8291case Arg::Tmp:
8292#if CPU(X86_64)
8293if (!args[0].tmp().isGP())
8294OPGEN_RETURN(false);
8295if (!args[1].tmp().isGP())
8296OPGEN_RETURN(false);
8297if (!isRotateLeft32Valid(*this))
8298OPGEN_RETURN(false);
8299OPGEN_RETURN(true);
8300#endif
8301break;
8302break;
8303default:
8304break;
8305}
8306break;
8307case Arg::Imm:
8308switch (this->args[1].kind()) {
8309case Arg::Tmp:
8310#if CPU(X86_64)
8311if (!Arg::isValidImmForm(args[0].value()))
8312OPGEN_RETURN(false);
8313if (!args[1].tmp().isGP())
8314OPGEN_RETURN(false);
8315OPGEN_RETURN(true);
8316#endif
8317break;
8318break;
8319default:
8320break;
8321}
8322break;
8323default:
8324break;
8325}
8326break;
8327default:
8328break;
8329}
8330break;
8331case Opcode::RotateLeft64:
8332switch (this->args.size()) {
8333case 2:
8334switch (this->args[0].kind()) {
8335case Arg::Tmp:
8336switch (this->args[1].kind()) {
8337case Arg::Tmp:
8338#if CPU(X86_64)
8339if (!args[0].tmp().isGP())
8340OPGEN_RETURN(false);
8341if (!args[1].tmp().isGP())
8342OPGEN_RETURN(false);
8343if (!isRotateLeft64Valid(*this))
8344OPGEN_RETURN(false);
8345OPGEN_RETURN(true);
8346#endif
8347break;
8348break;
8349default:
8350break;
8351}
8352break;
8353case Arg::Imm:
8354switch (this->args[1].kind()) {
8355case Arg::Tmp:
8356#if CPU(X86_64)
8357if (!Arg::isValidImmForm(args[0].value()))
8358OPGEN_RETURN(false);
8359if (!args[1].tmp().isGP())
8360OPGEN_RETURN(false);
8361OPGEN_RETURN(true);
8362#endif
8363break;
8364break;
8365default:
8366break;
8367}
8368break;
8369default:
8370break;
8371}
8372break;
8373default:
8374break;
8375}
8376break;
8377case Opcode::Or32:
8378switch (this->args.size()) {
8379case 3:
8380switch (this->args[0].kind()) {
8381case Arg::Tmp:
8382switch (this->args[1].kind()) {
8383case Arg::Tmp:
8384switch (this->args[2].kind()) {
8385case Arg::Tmp:
8386if (!args[0].tmp().isGP())
8387OPGEN_RETURN(false);
8388if (!args[1].tmp().isGP())
8389OPGEN_RETURN(false);
8390if (!args[2].tmp().isGP())
8391OPGEN_RETURN(false);
8392OPGEN_RETURN(true);
8393break;
8394break;
8395default:
8396break;
8397}
8398break;
8399case Arg::Addr:
8400case Arg::Stack:
8401case Arg::CallArg:
8402switch (this->args[2].kind()) {
8403case Arg::Tmp:
8404#if CPU(X86) || CPU(X86_64)
8405if (!args[0].tmp().isGP())
8406OPGEN_RETURN(false);
8407if (!Arg::isValidAddrForm(args[1].offset()))
8408OPGEN_RETURN(false);
8409if (!args[2].tmp().isGP())
8410OPGEN_RETURN(false);
8411OPGEN_RETURN(true);
8412#endif
8413break;
8414break;
8415default:
8416break;
8417}
8418break;
8419default:
8420break;
8421}
8422break;
8423case Arg::BitImm:
8424switch (this->args[1].kind()) {
8425case Arg::Tmp:
8426switch (this->args[2].kind()) {
8427case Arg::Tmp:
8428#if CPU(ARM64)
8429if (!Arg::isValidBitImmForm(args[0].value()))
8430OPGEN_RETURN(false);
8431if (!args[1].tmp().isGP())
8432OPGEN_RETURN(false);
8433if (!args[2].tmp().isGP())
8434OPGEN_RETURN(false);
8435OPGEN_RETURN(true);
8436#endif
8437break;
8438break;
8439default:
8440break;
8441}
8442break;
8443default:
8444break;
8445}
8446break;
8447case Arg::Addr:
8448case Arg::Stack:
8449case Arg::CallArg:
8450switch (this->args[1].kind()) {
8451case Arg::Tmp:
8452switch (this->args[2].kind()) {
8453case Arg::Tmp:
8454#if CPU(X86) || CPU(X86_64)
8455if (!Arg::isValidAddrForm(args[0].offset()))
8456OPGEN_RETURN(false);
8457if (!args[1].tmp().isGP())
8458OPGEN_RETURN(false);
8459if (!args[2].tmp().isGP())
8460OPGEN_RETURN(false);
8461OPGEN_RETURN(true);
8462#endif
8463break;
8464break;
8465default:
8466break;
8467}
8468break;
8469default:
8470break;
8471}
8472break;
8473default:
8474break;
8475}
8476break;
8477case 2:
8478switch (this->args[0].kind()) {
8479case Arg::Tmp:
8480switch (this->args[1].kind()) {
8481case Arg::Tmp:
8482if (!args[0].tmp().isGP())
8483OPGEN_RETURN(false);
8484if (!args[1].tmp().isGP())
8485OPGEN_RETURN(false);
8486OPGEN_RETURN(true);
8487break;
8488break;
8489case Arg::Addr:
8490case Arg::Stack:
8491case Arg::CallArg:
8492#if CPU(X86) || CPU(X86_64)
8493if (!args[0].tmp().isGP())
8494OPGEN_RETURN(false);
8495if (!Arg::isValidAddrForm(args[1].offset()))
8496OPGEN_RETURN(false);
8497OPGEN_RETURN(true);
8498#endif
8499break;
8500break;
8501case Arg::Index:
8502#if CPU(X86) || CPU(X86_64)
8503if (!args[0].tmp().isGP())
8504OPGEN_RETURN(false);
8505if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8506OPGEN_RETURN(false);
8507OPGEN_RETURN(true);
8508#endif
8509break;
8510break;
8511default:
8512break;
8513}
8514break;
8515case Arg::Imm:
8516switch (this->args[1].kind()) {
8517case Arg::Tmp:
8518#if CPU(X86) || CPU(X86_64)
8519if (!Arg::isValidImmForm(args[0].value()))
8520OPGEN_RETURN(false);
8521if (!args[1].tmp().isGP())
8522OPGEN_RETURN(false);
8523OPGEN_RETURN(true);
8524#endif
8525break;
8526break;
8527case Arg::Addr:
8528case Arg::Stack:
8529case Arg::CallArg:
8530#if CPU(X86) || CPU(X86_64)
8531if (!Arg::isValidImmForm(args[0].value()))
8532OPGEN_RETURN(false);
8533if (!Arg::isValidAddrForm(args[1].offset()))
8534OPGEN_RETURN(false);
8535OPGEN_RETURN(true);
8536#endif
8537break;
8538break;
8539case Arg::Index:
8540#if CPU(X86) || CPU(X86_64)
8541if (!Arg::isValidImmForm(args[0].value()))
8542OPGEN_RETURN(false);
8543if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8544OPGEN_RETURN(false);
8545OPGEN_RETURN(true);
8546#endif
8547break;
8548break;
8549default:
8550break;
8551}
8552break;
8553case Arg::Addr:
8554case Arg::Stack:
8555case Arg::CallArg:
8556switch (this->args[1].kind()) {
8557case Arg::Tmp:
8558#if CPU(X86) || CPU(X86_64)
8559if (!Arg::isValidAddrForm(args[0].offset()))
8560OPGEN_RETURN(false);
8561if (!args[1].tmp().isGP())
8562OPGEN_RETURN(false);
8563OPGEN_RETURN(true);
8564#endif
8565break;
8566break;
8567default:
8568break;
8569}
8570break;
8571case Arg::Index:
8572switch (this->args[1].kind()) {
8573case Arg::Tmp:
8574#if CPU(X86) || CPU(X86_64)
8575if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
8576OPGEN_RETURN(false);
8577if (!args[1].tmp().isGP())
8578OPGEN_RETURN(false);
8579OPGEN_RETURN(true);
8580#endif
8581break;
8582break;
8583default:
8584break;
8585}
8586break;
8587default:
8588break;
8589}
8590break;
8591default:
8592break;
8593}
8594break;
8595case Opcode::Or64:
8596switch (this->args.size()) {
8597case 3:
8598switch (this->args[0].kind()) {
8599case Arg::Tmp:
8600switch (this->args[1].kind()) {
8601case Arg::Tmp:
8602switch (this->args[2].kind()) {
8603case Arg::Tmp:
8604#if CPU(X86_64) || CPU(ARM64)
8605if (!args[0].tmp().isGP())
8606OPGEN_RETURN(false);
8607if (!args[1].tmp().isGP())
8608OPGEN_RETURN(false);
8609if (!args[2].tmp().isGP())
8610OPGEN_RETURN(false);
8611OPGEN_RETURN(true);
8612#endif
8613break;
8614break;
8615default:
8616break;
8617}
8618break;
8619default:
8620break;
8621}
8622break;
8623#if USE(JSVALUE64)
8624case Arg::BitImm64:
8625switch (this->args[1].kind()) {
8626case Arg::Tmp:
8627switch (this->args[2].kind()) {
8628case Arg::Tmp:
8629#if CPU(ARM64)
8630if (!Arg::isValidBitImm64Form(args[0].value()))
8631OPGEN_RETURN(false);
8632if (!args[1].tmp().isGP())
8633OPGEN_RETURN(false);
8634if (!args[2].tmp().isGP())
8635OPGEN_RETURN(false);
8636OPGEN_RETURN(true);
8637#endif
8638break;
8639break;
8640default:
8641break;
8642}
8643break;
8644default:
8645break;
8646}
8647break;
8648#endif // USE(JSVALUE64)
8649default:
8650break;
8651}
8652break;
8653case 2:
8654switch (this->args[0].kind()) {
8655case Arg::Tmp:
8656switch (this->args[1].kind()) {
8657case Arg::Tmp:
8658#if CPU(X86_64) || CPU(ARM64)
8659if (!args[0].tmp().isGP())
8660OPGEN_RETURN(false);
8661if (!args[1].tmp().isGP())
8662OPGEN_RETURN(false);
8663OPGEN_RETURN(true);
8664#endif
8665break;
8666break;
8667case Arg::Addr:
8668case Arg::Stack:
8669case Arg::CallArg:
8670#if CPU(X86_64)
8671if (!args[0].tmp().isGP())
8672OPGEN_RETURN(false);
8673if (!Arg::isValidAddrForm(args[1].offset()))
8674OPGEN_RETURN(false);
8675OPGEN_RETURN(true);
8676#endif
8677break;
8678break;
8679case Arg::Index:
8680#if CPU(X86_64)
8681if (!args[0].tmp().isGP())
8682OPGEN_RETURN(false);
8683if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
8684OPGEN_RETURN(false);
8685OPGEN_RETURN(true);
8686#endif
8687break;
8688break;
8689default:
8690break;
8691}
8692break;
8693case Arg::Imm:
8694switch (this->args[1].kind()) {
8695case Arg::Tmp:
8696#if CPU(X86_64)
8697if (!Arg::isValidImmForm(args[0].value()))
8698OPGEN_RETURN(false);
8699if (!args[1].tmp().isGP())
8700OPGEN_RETURN(false);
8701OPGEN_RETURN(true);
8702#endif
8703break;
8704break;
8705case Arg::Addr:
8706case Arg::Stack:
8707case Arg::CallArg:
8708#if CPU(X86_64)
8709if (!Arg::isValidImmForm(args[0].value()))
8710OPGEN_RETURN(false);
8711if (!Arg::isValidAddrForm(args[1].offset()))
8712OPGEN_RETURN(false);
8713OPGEN_RETURN(true);
8714#endif
8715break;
8716break;
8717case Arg::Index:
8718#if CPU(X86_64)
8719if (!Arg::isValidImmForm(args[0].value()))
8720OPGEN_RETURN(false);
8721if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
8722OPGEN_RETURN(false);
8723OPGEN_RETURN(true);
8724#endif
8725break;
8726break;
8727default:
8728break;
8729}
8730break;
8731case Arg::Addr:
8732case Arg::Stack:
8733case Arg::CallArg:
8734switch (this->args[1].kind()) {
8735case Arg::Tmp:
8736#if CPU(X86_64)
8737if (!Arg::isValidAddrForm(args[0].offset()))
8738OPGEN_RETURN(false);
8739if (!args[1].tmp().isGP())
8740OPGEN_RETURN(false);
8741OPGEN_RETURN(true);
8742#endif
8743break;
8744break;
8745default:
8746break;
8747}
8748break;
8749case Arg::Index:
8750switch (this->args[1].kind()) {
8751case Arg::Tmp:
8752#if CPU(X86_64)
8753if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
8754OPGEN_RETURN(false);
8755if (!args[1].tmp().isGP())
8756OPGEN_RETURN(false);
8757OPGEN_RETURN(true);
8758#endif
8759break;
8760break;
8761default:
8762break;
8763}
8764break;
8765default:
8766break;
8767}
8768break;
8769default:
8770break;
8771}
8772break;
8773case Opcode::Xor32:
8774switch (this->args.size()) {
8775case 3:
8776switch (this->args[0].kind()) {
8777case Arg::Tmp:
8778switch (this->args[1].kind()) {
8779case Arg::Tmp:
8780switch (this->args[2].kind()) {
8781case Arg::Tmp:
8782if (!args[0].tmp().isGP())
8783OPGEN_RETURN(false);
8784if (!args[1].tmp().isGP())
8785OPGEN_RETURN(false);
8786if (!args[2].tmp().isGP())
8787OPGEN_RETURN(false);
8788OPGEN_RETURN(true);
8789break;
8790break;
8791default:
8792break;
8793}
8794break;
8795case Arg::Addr:
8796case Arg::Stack:
8797case Arg::CallArg:
8798switch (this->args[2].kind()) {
8799case Arg::Tmp:
8800#if CPU(X86) || CPU(X86_64)
8801if (!args[0].tmp().isGP())
8802OPGEN_RETURN(false);
8803if (!Arg::isValidAddrForm(args[1].offset()))
8804OPGEN_RETURN(false);
8805if (!args[2].tmp().isGP())
8806OPGEN_RETURN(false);
8807OPGEN_RETURN(true);
8808#endif
8809break;
8810break;
8811default:
8812break;
8813}
8814break;
8815default:
8816break;
8817}
8818break;
8819case Arg::BitImm:
8820switch (this->args[1].kind()) {
8821case Arg::Tmp:
8822switch (this->args[2].kind()) {
8823case Arg::Tmp:
8824#if CPU(ARM64)
8825if (!Arg::isValidBitImmForm(args[0].value()))
8826OPGEN_RETURN(false);
8827if (!args[1].tmp().isGP())
8828OPGEN_RETURN(false);
8829if (!args[2].tmp().isGP())
8830OPGEN_RETURN(false);
8831OPGEN_RETURN(true);
8832#endif
8833break;
8834break;
8835default:
8836break;
8837}
8838break;
8839default:
8840break;
8841}
8842break;
8843case Arg::Addr:
8844case Arg::Stack:
8845case Arg::CallArg:
8846switch (this->args[1].kind()) {
8847case Arg::Tmp:
8848switch (this->args[2].kind()) {
8849case Arg::Tmp:
8850#if CPU(X86) || CPU(X86_64)
8851if (!Arg::isValidAddrForm(args[0].offset()))
8852OPGEN_RETURN(false);
8853if (!args[1].tmp().isGP())
8854OPGEN_RETURN(false);
8855if (!args[2].tmp().isGP())
8856OPGEN_RETURN(false);
8857OPGEN_RETURN(true);
8858#endif
8859break;
8860break;
8861default:
8862break;
8863}
8864break;
8865default:
8866break;
8867}
8868break;
8869default:
8870break;
8871}
8872break;
8873case 2:
8874switch (this->args[0].kind()) {
8875case Arg::Tmp:
8876switch (this->args[1].kind()) {
8877case Arg::Tmp:
8878if (!args[0].tmp().isGP())
8879OPGEN_RETURN(false);
8880if (!args[1].tmp().isGP())
8881OPGEN_RETURN(false);
8882OPGEN_RETURN(true);
8883break;
8884break;
8885case Arg::Addr:
8886case Arg::Stack:
8887case Arg::CallArg:
8888#if CPU(X86) || CPU(X86_64)
8889if (!args[0].tmp().isGP())
8890OPGEN_RETURN(false);
8891if (!Arg::isValidAddrForm(args[1].offset()))
8892OPGEN_RETURN(false);
8893OPGEN_RETURN(true);
8894#endif
8895break;
8896break;
8897case Arg::Index:
8898#if CPU(X86) || CPU(X86_64)
8899if (!args[0].tmp().isGP())
8900OPGEN_RETURN(false);
8901if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8902OPGEN_RETURN(false);
8903OPGEN_RETURN(true);
8904#endif
8905break;
8906break;
8907default:
8908break;
8909}
8910break;
8911case Arg::Imm:
8912switch (this->args[1].kind()) {
8913case Arg::Tmp:
8914#if CPU(X86) || CPU(X86_64)
8915if (!Arg::isValidImmForm(args[0].value()))
8916OPGEN_RETURN(false);
8917if (!args[1].tmp().isGP())
8918OPGEN_RETURN(false);
8919OPGEN_RETURN(true);
8920#endif
8921break;
8922break;
8923case Arg::Addr:
8924case Arg::Stack:
8925case Arg::CallArg:
8926#if CPU(X86) || CPU(X86_64)
8927if (!Arg::isValidImmForm(args[0].value()))
8928OPGEN_RETURN(false);
8929if (!Arg::isValidAddrForm(args[1].offset()))
8930OPGEN_RETURN(false);
8931OPGEN_RETURN(true);
8932#endif
8933break;
8934break;
8935case Arg::Index:
8936#if CPU(X86) || CPU(X86_64)
8937if (!Arg::isValidImmForm(args[0].value()))
8938OPGEN_RETURN(false);
8939if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8940OPGEN_RETURN(false);
8941OPGEN_RETURN(true);
8942#endif
8943break;
8944break;
8945default:
8946break;
8947}
8948break;
8949case Arg::Addr:
8950case Arg::Stack:
8951case Arg::CallArg:
8952switch (this->args[1].kind()) {
8953case Arg::Tmp:
8954#if CPU(X86) || CPU(X86_64)
8955if (!Arg::isValidAddrForm(args[0].offset()))
8956OPGEN_RETURN(false);
8957if (!args[1].tmp().isGP())
8958OPGEN_RETURN(false);
8959OPGEN_RETURN(true);
8960#endif
8961break;
8962break;
8963default:
8964break;
8965}
8966break;
8967case Arg::Index:
8968switch (this->args[1].kind()) {
8969case Arg::Tmp:
8970#if CPU(X86) || CPU(X86_64)
8971if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
8972OPGEN_RETURN(false);
8973if (!args[1].tmp().isGP())
8974OPGEN_RETURN(false);
8975OPGEN_RETURN(true);
8976#endif
8977break;
8978break;
8979default:
8980break;
8981}
8982break;
8983default:
8984break;
8985}
8986break;
8987default:
8988break;
8989}
8990break;
8991case Opcode::Xor64:
8992switch (this->args.size()) {
8993case 3:
8994switch (this->args[0].kind()) {
8995case Arg::Tmp:
8996switch (this->args[1].kind()) {
8997case Arg::Tmp:
8998switch (this->args[2].kind()) {
8999case Arg::Tmp:
9000#if CPU(X86_64) || CPU(ARM64)
9001if (!args[0].tmp().isGP())
9002OPGEN_RETURN(false);
9003if (!args[1].tmp().isGP())
9004OPGEN_RETURN(false);
9005if (!args[2].tmp().isGP())
9006OPGEN_RETURN(false);
9007OPGEN_RETURN(true);
9008#endif
9009break;
9010break;
9011default:
9012break;
9013}
9014break;
9015default:
9016break;
9017}
9018break;
9019#if USE(JSVALUE64)
9020case Arg::BitImm64:
9021switch (this->args[1].kind()) {
9022case Arg::Tmp:
9023switch (this->args[2].kind()) {
9024case Arg::Tmp:
9025#if CPU(ARM64)
9026if (!Arg::isValidBitImm64Form(args[0].value()))
9027OPGEN_RETURN(false);
9028if (!args[1].tmp().isGP())
9029OPGEN_RETURN(false);
9030if (!args[2].tmp().isGP())
9031OPGEN_RETURN(false);
9032OPGEN_RETURN(true);
9033#endif
9034break;
9035break;
9036default:
9037break;
9038}
9039break;
9040default:
9041break;
9042}
9043break;
9044#endif // USE(JSVALUE64)
9045default:
9046break;
9047}
9048break;
9049case 2:
9050switch (this->args[0].kind()) {
9051case Arg::Tmp:
9052switch (this->args[1].kind()) {
9053case Arg::Tmp:
9054#if CPU(X86_64) || CPU(ARM64)
9055if (!args[0].tmp().isGP())
9056OPGEN_RETURN(false);
9057if (!args[1].tmp().isGP())
9058OPGEN_RETURN(false);
9059OPGEN_RETURN(true);
9060#endif
9061break;
9062break;
9063case Arg::Addr:
9064case Arg::Stack:
9065case Arg::CallArg:
9066#if CPU(X86_64)
9067if (!args[0].tmp().isGP())
9068OPGEN_RETURN(false);
9069if (!Arg::isValidAddrForm(args[1].offset()))
9070OPGEN_RETURN(false);
9071OPGEN_RETURN(true);
9072#endif
9073break;
9074break;
9075case Arg::Index:
9076#if CPU(X86_64)
9077if (!args[0].tmp().isGP())
9078OPGEN_RETURN(false);
9079if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
9080OPGEN_RETURN(false);
9081OPGEN_RETURN(true);
9082#endif
9083break;
9084break;
9085default:
9086break;
9087}
9088break;
9089case Arg::Addr:
9090case Arg::Stack:
9091case Arg::CallArg:
9092switch (this->args[1].kind()) {
9093case Arg::Tmp:
9094#if CPU(X86_64)
9095if (!Arg::isValidAddrForm(args[0].offset()))
9096OPGEN_RETURN(false);
9097if (!args[1].tmp().isGP())
9098OPGEN_RETURN(false);
9099OPGEN_RETURN(true);
9100#endif
9101break;
9102break;
9103default:
9104break;
9105}
9106break;
9107case Arg::Index:
9108switch (this->args[1].kind()) {
9109case Arg::Tmp:
9110#if CPU(X86_64)
9111if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
9112OPGEN_RETURN(false);
9113if (!args[1].tmp().isGP())
9114OPGEN_RETURN(false);
9115OPGEN_RETURN(true);
9116#endif
9117break;
9118break;
9119default:
9120break;
9121}
9122break;
9123case Arg::Imm:
9124switch (this->args[1].kind()) {
9125case Arg::Addr:
9126case Arg::Stack:
9127case Arg::CallArg:
9128#if CPU(X86_64)
9129if (!Arg::isValidImmForm(args[0].value()))
9130OPGEN_RETURN(false);
9131if (!Arg::isValidAddrForm(args[1].offset()))
9132OPGEN_RETURN(false);
9133OPGEN_RETURN(true);
9134#endif
9135break;
9136break;
9137case Arg::Index:
9138#if CPU(X86_64)
9139if (!Arg::isValidImmForm(args[0].value()))
9140OPGEN_RETURN(false);
9141if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
9142OPGEN_RETURN(false);
9143OPGEN_RETURN(true);
9144#endif
9145break;
9146break;
9147case Arg::Tmp:
9148#if CPU(X86_64)
9149if (!Arg::isValidImmForm(args[0].value()))
9150OPGEN_RETURN(false);
9151if (!args[1].tmp().isGP())
9152OPGEN_RETURN(false);
9153OPGEN_RETURN(true);
9154#endif
9155break;
9156break;
9157default:
9158break;
9159}
9160break;
9161default:
9162break;
9163}
9164break;
9165default:
9166break;
9167}
9168break;
9169case Opcode::Not32:
9170switch (this->args.size()) {
9171case 2:
9172switch (this->args[0].kind()) {
9173case Arg::Tmp:
9174switch (this->args[1].kind()) {
9175case Arg::Tmp:
9176#if CPU(ARM64)
9177if (!args[0].tmp().isGP())
9178OPGEN_RETURN(false);
9179if (!args[1].tmp().isGP())
9180OPGEN_RETURN(false);
9181OPGEN_RETURN(true);
9182#endif
9183break;
9184break;
9185default:
9186break;
9187}
9188break;
9189default:
9190break;
9191}
9192break;
9193case 1:
9194switch (this->args[0].kind()) {
9195case Arg::Tmp:
9196#if CPU(X86) || CPU(X86_64)
9197if (!args[0].tmp().isGP())
9198OPGEN_RETURN(false);
9199OPGEN_RETURN(true);
9200#endif
9201break;
9202break;
9203case Arg::Addr:
9204case Arg::Stack:
9205case Arg::CallArg:
9206#if CPU(X86) || CPU(X86_64)
9207if (!Arg::isValidAddrForm(args[0].offset()))
9208OPGEN_RETURN(false);
9209OPGEN_RETURN(true);
9210#endif
9211break;
9212break;
9213case Arg::Index:
9214#if CPU(X86) || CPU(X86_64)
9215if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
9216OPGEN_RETURN(false);
9217OPGEN_RETURN(true);
9218#endif
9219break;
9220break;
9221default:
9222break;
9223}
9224break;
9225default:
9226break;
9227}
9228break;
9229case Opcode::Not64:
9230switch (this->args.size()) {
9231case 2:
9232switch (this->args[0].kind()) {
9233case Arg::Tmp:
9234switch (this->args[1].kind()) {
9235case Arg::Tmp:
9236#if CPU(ARM64)
9237if (!args[0].tmp().isGP())
9238OPGEN_RETURN(false);
9239if (!args[1].tmp().isGP())
9240OPGEN_RETURN(false);
9241OPGEN_RETURN(true);
9242#endif
9243break;
9244break;
9245default:
9246break;
9247}
9248break;
9249default:
9250break;
9251}
9252break;
9253case 1:
9254switch (this->args[0].kind()) {
9255case Arg::Tmp:
9256#if CPU(X86_64)
9257if (!args[0].tmp().isGP())
9258OPGEN_RETURN(false);
9259OPGEN_RETURN(true);
9260#endif
9261break;
9262break;
9263case Arg::Addr:
9264case Arg::Stack:
9265case Arg::CallArg:
9266#if CPU(X86_64)
9267if (!Arg::isValidAddrForm(args[0].offset()))
9268OPGEN_RETURN(false);
9269OPGEN_RETURN(true);
9270#endif
9271break;
9272break;
9273case Arg::Index:
9274#if CPU(X86_64)
9275if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
9276OPGEN_RETURN(false);
9277OPGEN_RETURN(true);
9278#endif
9279break;
9280break;
9281default:
9282break;
9283}
9284break;
9285default:
9286break;
9287}
9288break;
9289case Opcode::AbsDouble:
9290switch (this->args.size()) {
9291case 2:
9292switch (this->args[0].kind()) {
9293case Arg::Tmp:
9294switch (this->args[1].kind()) {
9295case Arg::Tmp:
9296#if CPU(ARM64)
9297if (!args[0].tmp().isFP())
9298OPGEN_RETURN(false);
9299if (!args[1].tmp().isFP())
9300OPGEN_RETURN(false);
9301OPGEN_RETURN(true);
9302#endif
9303break;
9304break;
9305default:
9306break;
9307}
9308break;
9309default:
9310break;
9311}
9312break;
9313default:
9314break;
9315}
9316break;
9317case Opcode::AbsFloat:
9318switch (this->args.size()) {
9319case 2:
9320switch (this->args[0].kind()) {
9321case Arg::Tmp:
9322switch (this->args[1].kind()) {
9323case Arg::Tmp:
9324#if CPU(ARM64)
9325if (!args[0].tmp().isFP())
9326OPGEN_RETURN(false);
9327if (!args[1].tmp().isFP())
9328OPGEN_RETURN(false);
9329OPGEN_RETURN(true);
9330#endif
9331break;
9332break;
9333default:
9334break;
9335}
9336break;
9337default:
9338break;
9339}
9340break;
9341default:
9342break;
9343}
9344break;
9345case Opcode::CeilDouble:
9346switch (this->args.size()) {
9347case 2:
9348switch (this->args[0].kind()) {
9349case Arg::Tmp:
9350switch (this->args[1].kind()) {
9351case Arg::Tmp:
9352if (!args[0].tmp().isFP())
9353OPGEN_RETURN(false);
9354if (!args[1].tmp().isFP())
9355OPGEN_RETURN(false);
9356OPGEN_RETURN(true);
9357break;
9358break;
9359default:
9360break;
9361}
9362break;
9363case Arg::Addr:
9364case Arg::Stack:
9365case Arg::CallArg:
9366switch (this->args[1].kind()) {
9367case Arg::Tmp:
9368#if CPU(X86) || CPU(X86_64)
9369if (!Arg::isValidAddrForm(args[0].offset()))
9370OPGEN_RETURN(false);
9371if (!args[1].tmp().isFP())
9372OPGEN_RETURN(false);
9373OPGEN_RETURN(true);
9374#endif
9375break;
9376break;
9377default:
9378break;
9379}
9380break;
9381default:
9382break;
9383}
9384break;
9385default:
9386break;
9387}
9388break;
9389case Opcode::CeilFloat:
9390switch (this->args.size()) {
9391case 2:
9392switch (this->args[0].kind()) {
9393case Arg::Tmp:
9394switch (this->args[1].kind()) {
9395case Arg::Tmp:
9396if (!args[0].tmp().isFP())
9397OPGEN_RETURN(false);
9398if (!args[1].tmp().isFP())
9399OPGEN_RETURN(false);
9400OPGEN_RETURN(true);
9401break;
9402break;
9403default:
9404break;
9405}
9406break;
9407case Arg::Addr:
9408case Arg::Stack:
9409case Arg::CallArg:
9410switch (this->args[1].kind()) {
9411case Arg::Tmp:
9412#if CPU(X86) || CPU(X86_64)
9413if (!Arg::isValidAddrForm(args[0].offset()))
9414OPGEN_RETURN(false);
9415if (!args[1].tmp().isFP())
9416OPGEN_RETURN(false);
9417OPGEN_RETURN(true);
9418#endif
9419break;
9420break;
9421default:
9422break;
9423}
9424break;
9425default:
9426break;
9427}
9428break;
9429default:
9430break;
9431}
9432break;
9433case Opcode::FloorDouble:
9434switch (this->args.size()) {
9435case 2:
9436switch (this->args[0].kind()) {
9437case Arg::Tmp:
9438switch (this->args[1].kind()) {
9439case Arg::Tmp:
9440if (!args[0].tmp().isFP())
9441OPGEN_RETURN(false);
9442if (!args[1].tmp().isFP())
9443OPGEN_RETURN(false);
9444OPGEN_RETURN(true);
9445break;
9446break;
9447default:
9448break;
9449}
9450break;
9451case Arg::Addr:
9452case Arg::Stack:
9453case Arg::CallArg:
9454switch (this->args[1].kind()) {
9455case Arg::Tmp:
9456#if CPU(X86) || CPU(X86_64)
9457if (!Arg::isValidAddrForm(args[0].offset()))
9458OPGEN_RETURN(false);
9459if (!args[1].tmp().isFP())
9460OPGEN_RETURN(false);
9461OPGEN_RETURN(true);
9462#endif
9463break;
9464break;
9465default:
9466break;
9467}
9468break;
9469default:
9470break;
9471}
9472break;
9473default:
9474break;
9475}
9476break;
9477case Opcode::FloorFloat:
9478switch (this->args.size()) {
9479case 2:
9480switch (this->args[0].kind()) {
9481case Arg::Tmp:
9482switch (this->args[1].kind()) {
9483case Arg::Tmp:
9484if (!args[0].tmp().isFP())
9485OPGEN_RETURN(false);
9486if (!args[1].tmp().isFP())
9487OPGEN_RETURN(false);
9488OPGEN_RETURN(true);
9489break;
9490break;
9491default:
9492break;
9493}
9494break;
9495case Arg::Addr:
9496case Arg::Stack:
9497case Arg::CallArg:
9498switch (this->args[1].kind()) {
9499case Arg::Tmp:
9500#if CPU(X86) || CPU(X86_64)
9501if (!Arg::isValidAddrForm(args[0].offset()))
9502OPGEN_RETURN(false);
9503if (!args[1].tmp().isFP())
9504OPGEN_RETURN(false);
9505OPGEN_RETURN(true);
9506#endif
9507break;
9508break;
9509default:
9510break;
9511}
9512break;
9513default:
9514break;
9515}
9516break;
9517default:
9518break;
9519}
9520break;
9521case Opcode::SqrtDouble:
9522switch (this->args.size()) {
9523case 2:
9524switch (this->args[0].kind()) {
9525case Arg::Tmp:
9526switch (this->args[1].kind()) {
9527case Arg::Tmp:
9528if (!args[0].tmp().isFP())
9529OPGEN_RETURN(false);
9530if (!args[1].tmp().isFP())
9531OPGEN_RETURN(false);
9532OPGEN_RETURN(true);
9533break;
9534break;
9535default:
9536break;
9537}
9538break;
9539case Arg::Addr:
9540case Arg::Stack:
9541case Arg::CallArg:
9542switch (this->args[1].kind()) {
9543case Arg::Tmp:
9544#if CPU(X86) || CPU(X86_64)
9545if (!Arg::isValidAddrForm(args[0].offset()))
9546OPGEN_RETURN(false);
9547if (!args[1].tmp().isFP())
9548OPGEN_RETURN(false);
9549OPGEN_RETURN(true);
9550#endif
9551break;
9552break;
9553default:
9554break;
9555}
9556break;
9557default:
9558break;
9559}
9560break;
9561default:
9562break;
9563}
9564break;
9565case Opcode::SqrtFloat:
9566switch (this->args.size()) {
9567case 2:
9568switch (this->args[0].kind()) {
9569case Arg::Tmp:
9570switch (this->args[1].kind()) {
9571case Arg::Tmp:
9572if (!args[0].tmp().isFP())
9573OPGEN_RETURN(false);
9574if (!args[1].tmp().isFP())
9575OPGEN_RETURN(false);
9576OPGEN_RETURN(true);
9577break;
9578break;
9579default:
9580break;
9581}
9582break;
9583case Arg::Addr:
9584case Arg::Stack:
9585case Arg::CallArg:
9586switch (this->args[1].kind()) {
9587case Arg::Tmp:
9588#if CPU(X86) || CPU(X86_64)
9589if (!Arg::isValidAddrForm(args[0].offset()))
9590OPGEN_RETURN(false);
9591if (!args[1].tmp().isFP())
9592OPGEN_RETURN(false);
9593OPGEN_RETURN(true);
9594#endif
9595break;
9596break;
9597default:
9598break;
9599}
9600break;
9601default:
9602break;
9603}
9604break;
9605default:
9606break;
9607}
9608break;
9609case Opcode::ConvertInt32ToDouble:
9610switch (this->args.size()) {
9611case 2:
9612switch (this->args[0].kind()) {
9613case Arg::Tmp:
9614switch (this->args[1].kind()) {
9615case Arg::Tmp:
9616if (!args[0].tmp().isGP())
9617OPGEN_RETURN(false);
9618if (!args[1].tmp().isFP())
9619OPGEN_RETURN(false);
9620OPGEN_RETURN(true);
9621break;
9622break;
9623default:
9624break;
9625}
9626break;
9627case Arg::Addr:
9628case Arg::Stack:
9629case Arg::CallArg:
9630switch (this->args[1].kind()) {
9631case Arg::Tmp:
9632#if CPU(X86) || CPU(X86_64)
9633if (!Arg::isValidAddrForm(args[0].offset()))
9634OPGEN_RETURN(false);
9635if (!args[1].tmp().isFP())
9636OPGEN_RETURN(false);
9637OPGEN_RETURN(true);
9638#endif
9639break;
9640break;
9641default:
9642break;
9643}
9644break;
9645default:
9646break;
9647}
9648break;
9649default:
9650break;
9651}
9652break;
9653case Opcode::ConvertInt64ToDouble:
9654switch (this->args.size()) {
9655case 2:
9656switch (this->args[0].kind()) {
9657case Arg::Tmp:
9658switch (this->args[1].kind()) {
9659case Arg::Tmp:
9660#if CPU(X86_64) || CPU(ARM64)
9661if (!args[0].tmp().isGP())
9662OPGEN_RETURN(false);
9663if (!args[1].tmp().isFP())
9664OPGEN_RETURN(false);
9665OPGEN_RETURN(true);
9666#endif
9667break;
9668break;
9669default:
9670break;
9671}
9672break;
9673case Arg::Addr:
9674case Arg::Stack:
9675case Arg::CallArg:
9676switch (this->args[1].kind()) {
9677case Arg::Tmp:
9678#if CPU(X86_64)
9679if (!Arg::isValidAddrForm(args[0].offset()))
9680OPGEN_RETURN(false);
9681if (!args[1].tmp().isFP())
9682OPGEN_RETURN(false);
9683OPGEN_RETURN(true);
9684#endif
9685break;
9686break;
9687default:
9688break;
9689}
9690break;
9691default:
9692break;
9693}
9694break;
9695default:
9696break;
9697}
9698break;
9699case Opcode::ConvertInt32ToFloat:
9700switch (this->args.size()) {
9701case 2:
9702switch (this->args[0].kind()) {
9703case Arg::Tmp:
9704switch (this->args[1].kind()) {
9705case Arg::Tmp:
9706if (!args[0].tmp().isGP())
9707OPGEN_RETURN(false);
9708if (!args[1].tmp().isFP())
9709OPGEN_RETURN(false);
9710OPGEN_RETURN(true);
9711break;
9712break;
9713default:
9714break;
9715}
9716break;
9717case Arg::Addr:
9718case Arg::Stack:
9719case Arg::CallArg:
9720switch (this->args[1].kind()) {
9721case Arg::Tmp:
9722#if CPU(X86) || CPU(X86_64)
9723if (!Arg::isValidAddrForm(args[0].offset()))
9724OPGEN_RETURN(false);
9725if (!args[1].tmp().isFP())
9726OPGEN_RETURN(false);
9727OPGEN_RETURN(true);
9728#endif
9729break;
9730break;
9731default:
9732break;
9733}
9734break;
9735default:
9736break;
9737}
9738break;
9739default:
9740break;
9741}
9742break;
9743case Opcode::ConvertInt64ToFloat:
9744switch (this->args.size()) {
9745case 2:
9746switch (this->args[0].kind()) {
9747case Arg::Tmp:
9748switch (this->args[1].kind()) {
9749case Arg::Tmp:
9750#if CPU(X86_64) || CPU(ARM64)
9751if (!args[0].tmp().isGP())
9752OPGEN_RETURN(false);
9753if (!args[1].tmp().isFP())
9754OPGEN_RETURN(false);
9755OPGEN_RETURN(true);
9756#endif
9757break;
9758break;
9759default:
9760break;
9761}
9762break;
9763case Arg::Addr:
9764case Arg::Stack:
9765case Arg::CallArg:
9766switch (this->args[1].kind()) {
9767case Arg::Tmp:
9768#if CPU(X86_64)
9769if (!Arg::isValidAddrForm(args[0].offset()))
9770OPGEN_RETURN(false);
9771if (!args[1].tmp().isFP())
9772OPGEN_RETURN(false);
9773OPGEN_RETURN(true);
9774#endif
9775break;
9776break;
9777default:
9778break;
9779}
9780break;
9781default:
9782break;
9783}
9784break;
9785default:
9786break;
9787}
9788break;
9789case Opcode::CountLeadingZeros32:
9790switch (this->args.size()) {
9791case 2:
9792switch (this->args[0].kind()) {
9793case Arg::Tmp:
9794switch (this->args[1].kind()) {
9795case Arg::Tmp:
9796if (!args[0].tmp().isGP())
9797OPGEN_RETURN(false);
9798if (!args[1].tmp().isGP())
9799OPGEN_RETURN(false);
9800OPGEN_RETURN(true);
9801break;
9802break;
9803default:
9804break;
9805}
9806break;
9807case Arg::Addr:
9808case Arg::Stack:
9809case Arg::CallArg:
9810switch (this->args[1].kind()) {
9811case Arg::Tmp:
9812#if CPU(X86) || CPU(X86_64)
9813if (!Arg::isValidAddrForm(args[0].offset()))
9814OPGEN_RETURN(false);
9815if (!args[1].tmp().isGP())
9816OPGEN_RETURN(false);
9817OPGEN_RETURN(true);
9818#endif
9819break;
9820break;
9821default:
9822break;
9823}
9824break;
9825default:
9826break;
9827}
9828break;
9829default:
9830break;
9831}
9832break;
9833case Opcode::CountLeadingZeros64:
9834switch (this->args.size()) {
9835case 2:
9836switch (this->args[0].kind()) {
9837case Arg::Tmp:
9838switch (this->args[1].kind()) {
9839case Arg::Tmp:
9840#if CPU(X86_64) || CPU(ARM64)
9841if (!args[0].tmp().isGP())
9842OPGEN_RETURN(false);
9843if (!args[1].tmp().isGP())
9844OPGEN_RETURN(false);
9845OPGEN_RETURN(true);
9846#endif
9847break;
9848break;
9849default:
9850break;
9851}
9852break;
9853case Arg::Addr:
9854case Arg::Stack:
9855case Arg::CallArg:
9856switch (this->args[1].kind()) {
9857case Arg::Tmp:
9858#if CPU(X86_64)
9859if (!Arg::isValidAddrForm(args[0].offset()))
9860OPGEN_RETURN(false);
9861if (!args[1].tmp().isGP())
9862OPGEN_RETURN(false);
9863OPGEN_RETURN(true);
9864#endif
9865break;
9866break;
9867default:
9868break;
9869}
9870break;
9871default:
9872break;
9873}
9874break;
9875default:
9876break;
9877}
9878break;
9879case Opcode::ConvertDoubleToFloat:
9880switch (this->args.size()) {
9881case 2:
9882switch (this->args[0].kind()) {
9883case Arg::Tmp:
9884switch (this->args[1].kind()) {
9885case Arg::Tmp:
9886if (!args[0].tmp().isFP())
9887OPGEN_RETURN(false);
9888if (!args[1].tmp().isFP())
9889OPGEN_RETURN(false);
9890OPGEN_RETURN(true);
9891break;
9892break;
9893default:
9894break;
9895}
9896break;
9897case Arg::Addr:
9898case Arg::Stack:
9899case Arg::CallArg:
9900switch (this->args[1].kind()) {
9901case Arg::Tmp:
9902#if CPU(X86) || CPU(X86_64)
9903if (!Arg::isValidAddrForm(args[0].offset()))
9904OPGEN_RETURN(false);
9905if (!args[1].tmp().isFP())
9906OPGEN_RETURN(false);
9907OPGEN_RETURN(true);
9908#endif
9909break;
9910break;
9911default:
9912break;
9913}
9914break;
9915default:
9916break;
9917}
9918break;
9919default:
9920break;
9921}
9922break;
9923case Opcode::ConvertFloatToDouble:
9924switch (this->args.size()) {
9925case 2:
9926switch (this->args[0].kind()) {
9927case Arg::Tmp:
9928switch (this->args[1].kind()) {
9929case Arg::Tmp:
9930if (!args[0].tmp().isFP())
9931OPGEN_RETURN(false);
9932if (!args[1].tmp().isFP())
9933OPGEN_RETURN(false);
9934OPGEN_RETURN(true);
9935break;
9936break;
9937default:
9938break;
9939}
9940break;
9941case Arg::Addr:
9942case Arg::Stack:
9943case Arg::CallArg:
9944switch (this->args[1].kind()) {
9945case Arg::Tmp:
9946#if CPU(X86) || CPU(X86_64)
9947if (!Arg::isValidAddrForm(args[0].offset()))
9948OPGEN_RETURN(false);
9949if (!args[1].tmp().isFP())
9950OPGEN_RETURN(false);
9951OPGEN_RETURN(true);
9952#endif
9953break;
9954break;
9955default:
9956break;
9957}
9958break;
9959default:
9960break;
9961}
9962break;
9963default:
9964break;
9965}
9966break;
9967case Opcode::Move:
9968switch (this->args.size()) {
9969case 2:
9970switch (this->args[0].kind()) {
9971case Arg::Tmp:
9972switch (this->args[1].kind()) {
9973case Arg::Tmp:
9974if (!args[0].tmp().isGP())
9975OPGEN_RETURN(false);
9976if (!args[1].tmp().isGP())
9977OPGEN_RETURN(false);
9978OPGEN_RETURN(true);
9979break;
9980break;
9981case Arg::Addr:
9982case Arg::Stack:
9983case Arg::CallArg:
9984if (!args[0].tmp().isGP())
9985OPGEN_RETURN(false);
9986if (!Arg::isValidAddrForm(args[1].offset()))
9987OPGEN_RETURN(false);
9988OPGEN_RETURN(true);
9989break;
9990break;
9991case Arg::Index:
9992if (!args[0].tmp().isGP())
9993OPGEN_RETURN(false);
9994if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), POINTER_WIDTH))
9995OPGEN_RETURN(false);
9996OPGEN_RETURN(true);
9997break;
9998break;
9999default:
10000break;
10001}
10002break;
10003case Arg::Imm:
10004switch (this->args[1].kind()) {
10005case Arg::Tmp:
10006if (!Arg::isValidImmForm(args[0].value()))
10007OPGEN_RETURN(false);
10008if (!args[1].tmp().isGP())
10009OPGEN_RETURN(false);
10010OPGEN_RETURN(true);
10011break;
10012break;
10013case Arg::Addr:
10014case Arg::Stack:
10015case Arg::CallArg:
10016#if CPU(X86) || CPU(X86_64)
10017if (!Arg::isValidImmForm(args[0].value()))
10018OPGEN_RETURN(false);
10019if (!Arg::isValidAddrForm(args[1].offset()))
10020OPGEN_RETURN(false);
10021OPGEN_RETURN(true);
10022#endif
10023break;
10024break;
10025default:
10026break;
10027}
10028break;
10029#if USE(JSVALUE64)
10030case Arg::BigImm:
10031switch (this->args[1].kind()) {
10032case Arg::Tmp:
10033if (!args[1].tmp().isGP())
10034OPGEN_RETURN(false);
10035OPGEN_RETURN(true);
10036break;
10037break;
10038default:
10039break;
10040}
10041break;
10042#endif // USE(JSVALUE64)
10043case Arg::Addr:
10044case Arg::Stack:
10045case Arg::CallArg:
10046switch (this->args[1].kind()) {
10047case Arg::Tmp:
10048if (!Arg::isValidAddrForm(args[0].offset()))
10049OPGEN_RETURN(false);
10050if (!args[1].tmp().isGP())
10051OPGEN_RETURN(false);
10052OPGEN_RETURN(true);
10053break;
10054break;
10055default:
10056break;
10057}
10058break;
10059case Arg::Index:
10060switch (this->args[1].kind()) {
10061case Arg::Tmp:
10062if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), POINTER_WIDTH))
10063OPGEN_RETURN(false);
10064if (!args[1].tmp().isGP())
10065OPGEN_RETURN(false);
10066OPGEN_RETURN(true);
10067break;
10068break;
10069default:
10070break;
10071}
10072break;
10073default:
10074break;
10075}
10076break;
10077case 3:
10078switch (this->args[0].kind()) {
10079case Arg::Addr:
10080case Arg::Stack:
10081case Arg::CallArg:
10082switch (this->args[1].kind()) {
10083case Arg::Addr:
10084case Arg::Stack:
10085case Arg::CallArg:
10086switch (this->args[2].kind()) {
10087case Arg::Tmp:
10088if (!Arg::isValidAddrForm(args[0].offset()))
10089OPGEN_RETURN(false);
10090if (!Arg::isValidAddrForm(args[1].offset()))
10091OPGEN_RETURN(false);
10092if (!args[2].tmp().isGP())
10093OPGEN_RETURN(false);
10094OPGEN_RETURN(true);
10095break;
10096break;
10097default:
10098break;
10099}
10100break;
10101default:
10102break;
10103}
10104break;
10105default:
10106break;
10107}
10108break;
10109default:
10110break;
10111}
10112break;
10113case Opcode::Swap32:
10114switch (this->args.size()) {
10115case 2:
10116switch (this->args[0].kind()) {
10117case Arg::Tmp:
10118switch (this->args[1].kind()) {
10119case Arg::Tmp:
10120#if CPU(X86) || CPU(X86_64)
10121if (!args[0].tmp().isGP())
10122OPGEN_RETURN(false);
10123if (!args[1].tmp().isGP())
10124OPGEN_RETURN(false);
10125OPGEN_RETURN(true);
10126#endif
10127break;
10128break;
10129case Arg::Addr:
10130case Arg::Stack:
10131case Arg::CallArg:
10132#if CPU(X86) || CPU(X86_64)
10133if (!args[0].tmp().isGP())
10134OPGEN_RETURN(false);
10135if (!Arg::isValidAddrForm(args[1].offset()))
10136OPGEN_RETURN(false);
10137OPGEN_RETURN(true);
10138#endif
10139break;
10140break;
10141default:
10142break;
10143}
10144break;
10145default:
10146break;
10147}
10148break;
10149default:
10150break;
10151}
10152break;
10153case Opcode::Swap64:
10154switch (this->args.size()) {
10155case 2:
10156switch (this->args[0].kind()) {
10157case Arg::Tmp:
10158switch (this->args[1].kind()) {
10159case Arg::Tmp:
10160#if CPU(X86_64)
10161if (!args[0].tmp().isGP())
10162OPGEN_RETURN(false);
10163if (!args[1].tmp().isGP())
10164OPGEN_RETURN(false);
10165OPGEN_RETURN(true);
10166#endif
10167break;
10168break;
10169case Arg::Addr:
10170case Arg::Stack:
10171case Arg::CallArg:
10172#if CPU(X86_64)
10173if (!args[0].tmp().isGP())
10174OPGEN_RETURN(false);
10175if (!Arg::isValidAddrForm(args[1].offset()))
10176OPGEN_RETURN(false);
10177OPGEN_RETURN(true);
10178#endif
10179break;
10180break;
10181default:
10182break;
10183}
10184break;
10185default:
10186break;
10187}
10188break;
10189default:
10190break;
10191}
10192break;
10193case Opcode::Move32:
10194switch (this->args.size()) {
10195case 2:
10196switch (this->args[0].kind()) {
10197case Arg::Tmp:
10198switch (this->args[1].kind()) {
10199case Arg::Tmp:
10200if (!args[0].tmp().isGP())
10201OPGEN_RETURN(false);
10202if (!args[1].tmp().isGP())
10203OPGEN_RETURN(false);
10204OPGEN_RETURN(true);
10205break;
10206break;
10207case Arg::Addr:
10208case Arg::Stack:
10209case Arg::CallArg:
10210if (!args[0].tmp().isGP())
10211OPGEN_RETURN(false);
10212if (!Arg::isValidAddrForm(args[1].offset()))
10213OPGEN_RETURN(false);
10214OPGEN_RETURN(true);
10215break;
10216break;
10217case Arg::Index:
10218if (!args[0].tmp().isGP())
10219OPGEN_RETURN(false);
10220if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10221OPGEN_RETURN(false);
10222OPGEN_RETURN(true);
10223break;
10224break;
10225default:
10226break;
10227}
10228break;
10229case Arg::Addr:
10230case Arg::Stack:
10231case Arg::CallArg:
10232switch (this->args[1].kind()) {
10233case Arg::Tmp:
10234if (!Arg::isValidAddrForm(args[0].offset()))
10235OPGEN_RETURN(false);
10236if (!args[1].tmp().isGP())
10237OPGEN_RETURN(false);
10238OPGEN_RETURN(true);
10239break;
10240break;
10241default:
10242break;
10243}
10244break;
10245case Arg::Index:
10246switch (this->args[1].kind()) {
10247case Arg::Tmp:
10248if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10249OPGEN_RETURN(false);
10250if (!args[1].tmp().isGP())
10251OPGEN_RETURN(false);
10252OPGEN_RETURN(true);
10253break;
10254break;
10255default:
10256break;
10257}
10258break;
10259case Arg::Imm:
10260switch (this->args[1].kind()) {
10261case Arg::Tmp:
10262#if CPU(X86) || CPU(X86_64)
10263if (!Arg::isValidImmForm(args[0].value()))
10264OPGEN_RETURN(false);
10265if (!args[1].tmp().isGP())
10266OPGEN_RETURN(false);
10267OPGEN_RETURN(true);
10268#endif
10269break;
10270break;
10271case Arg::Addr:
10272case Arg::Stack:
10273case Arg::CallArg:
10274#if CPU(X86) || CPU(X86_64)
10275if (!Arg::isValidImmForm(args[0].value()))
10276OPGEN_RETURN(false);
10277if (!Arg::isValidAddrForm(args[1].offset()))
10278OPGEN_RETURN(false);
10279OPGEN_RETURN(true);
10280#endif
10281break;
10282break;
10283case Arg::Index:
10284#if CPU(X86) || CPU(X86_64)
10285if (!Arg::isValidImmForm(args[0].value()))
10286OPGEN_RETURN(false);
10287if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10288OPGEN_RETURN(false);
10289OPGEN_RETURN(true);
10290#endif
10291break;
10292break;
10293default:
10294break;
10295}
10296break;
10297default:
10298break;
10299}
10300break;
10301case 3:
10302switch (this->args[0].kind()) {
10303case Arg::Addr:
10304case Arg::Stack:
10305case Arg::CallArg:
10306switch (this->args[1].kind()) {
10307case Arg::Addr:
10308case Arg::Stack:
10309case Arg::CallArg:
10310switch (this->args[2].kind()) {
10311case Arg::Tmp:
10312if (!Arg::isValidAddrForm(args[0].offset()))
10313OPGEN_RETURN(false);
10314if (!Arg::isValidAddrForm(args[1].offset()))
10315OPGEN_RETURN(false);
10316if (!args[2].tmp().isGP())
10317OPGEN_RETURN(false);
10318OPGEN_RETURN(true);
10319break;
10320break;
10321default:
10322break;
10323}
10324break;
10325default:
10326break;
10327}
10328break;
10329default:
10330break;
10331}
10332break;
10333default:
10334break;
10335}
10336break;
10337case Opcode::StoreZero32:
10338switch (this->args.size()) {
10339case 1:
10340switch (this->args[0].kind()) {
10341case Arg::Addr:
10342case Arg::Stack:
10343case Arg::CallArg:
10344if (!Arg::isValidAddrForm(args[0].offset()))
10345OPGEN_RETURN(false);
10346OPGEN_RETURN(true);
10347break;
10348break;
10349case Arg::Index:
10350if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10351OPGEN_RETURN(false);
10352OPGEN_RETURN(true);
10353break;
10354break;
10355default:
10356break;
10357}
10358break;
10359default:
10360break;
10361}
10362break;
10363case Opcode::StoreZero64:
10364switch (this->args.size()) {
10365case 1:
10366switch (this->args[0].kind()) {
10367case Arg::Addr:
10368case Arg::Stack:
10369case Arg::CallArg:
10370#if CPU(X86_64) || CPU(ARM64)
10371if (!Arg::isValidAddrForm(args[0].offset()))
10372OPGEN_RETURN(false);
10373OPGEN_RETURN(true);
10374#endif
10375break;
10376break;
10377case Arg::Index:
10378#if CPU(X86_64) || CPU(ARM64)
10379if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10380OPGEN_RETURN(false);
10381OPGEN_RETURN(true);
10382#endif
10383break;
10384break;
10385default:
10386break;
10387}
10388break;
10389default:
10390break;
10391}
10392break;
10393case Opcode::SignExtend32ToPtr:
10394switch (this->args.size()) {
10395case 2:
10396switch (this->args[0].kind()) {
10397case Arg::Tmp:
10398switch (this->args[1].kind()) {
10399case Arg::Tmp:
10400if (!args[0].tmp().isGP())
10401OPGEN_RETURN(false);
10402if (!args[1].tmp().isGP())
10403OPGEN_RETURN(false);
10404OPGEN_RETURN(true);
10405break;
10406break;
10407default:
10408break;
10409}
10410break;
10411default:
10412break;
10413}
10414break;
10415default:
10416break;
10417}
10418break;
10419case Opcode::ZeroExtend8To32:
10420switch (this->args.size()) {
10421case 2:
10422switch (this->args[0].kind()) {
10423case Arg::Tmp:
10424switch (this->args[1].kind()) {
10425case Arg::Tmp:
10426if (!args[0].tmp().isGP())
10427OPGEN_RETURN(false);
10428if (!args[1].tmp().isGP())
10429OPGEN_RETURN(false);
10430OPGEN_RETURN(true);
10431break;
10432break;
10433default:
10434break;
10435}
10436break;
10437case Arg::Addr:
10438case Arg::Stack:
10439case Arg::CallArg:
10440switch (this->args[1].kind()) {
10441case Arg::Tmp:
10442#if CPU(X86) || CPU(X86_64)
10443if (!Arg::isValidAddrForm(args[0].offset()))
10444OPGEN_RETURN(false);
10445if (!args[1].tmp().isGP())
10446OPGEN_RETURN(false);
10447OPGEN_RETURN(true);
10448#endif
10449break;
10450break;
10451default:
10452break;
10453}
10454break;
10455case Arg::Index:
10456switch (this->args[1].kind()) {
10457case Arg::Tmp:
10458#if CPU(X86) || CPU(X86_64)
10459if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
10460OPGEN_RETURN(false);
10461if (!args[1].tmp().isGP())
10462OPGEN_RETURN(false);
10463OPGEN_RETURN(true);
10464#endif
10465break;
10466break;
10467default:
10468break;
10469}
10470break;
10471default:
10472break;
10473}
10474break;
10475default:
10476break;
10477}
10478break;
10479case Opcode::SignExtend8To32:
10480switch (this->args.size()) {
10481case 2:
10482switch (this->args[0].kind()) {
10483case Arg::Tmp:
10484switch (this->args[1].kind()) {
10485case Arg::Tmp:
10486if (!args[0].tmp().isGP())
10487OPGEN_RETURN(false);
10488if (!args[1].tmp().isGP())
10489OPGEN_RETURN(false);
10490OPGEN_RETURN(true);
10491break;
10492break;
10493default:
10494break;
10495}
10496break;
10497case Arg::Addr:
10498case Arg::Stack:
10499case Arg::CallArg:
10500switch (this->args[1].kind()) {
10501case Arg::Tmp:
10502#if CPU(X86) || CPU(X86_64)
10503if (!Arg::isValidAddrForm(args[0].offset()))
10504OPGEN_RETURN(false);
10505if (!args[1].tmp().isGP())
10506OPGEN_RETURN(false);
10507OPGEN_RETURN(true);
10508#endif
10509break;
10510break;
10511default:
10512break;
10513}
10514break;
10515case Arg::Index:
10516switch (this->args[1].kind()) {
10517case Arg::Tmp:
10518#if CPU(X86) || CPU(X86_64)
10519if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
10520OPGEN_RETURN(false);
10521if (!args[1].tmp().isGP())
10522OPGEN_RETURN(false);
10523OPGEN_RETURN(true);
10524#endif
10525break;
10526break;
10527default:
10528break;
10529}
10530break;
10531default:
10532break;
10533}
10534break;
10535default:
10536break;
10537}
10538break;
10539case Opcode::ZeroExtend16To32:
10540switch (this->args.size()) {
10541case 2:
10542switch (this->args[0].kind()) {
10543case Arg::Tmp:
10544switch (this->args[1].kind()) {
10545case Arg::Tmp:
10546if (!args[0].tmp().isGP())
10547OPGEN_RETURN(false);
10548if (!args[1].tmp().isGP())
10549OPGEN_RETURN(false);
10550OPGEN_RETURN(true);
10551break;
10552break;
10553default:
10554break;
10555}
10556break;
10557case Arg::Addr:
10558case Arg::Stack:
10559case Arg::CallArg:
10560switch (this->args[1].kind()) {
10561case Arg::Tmp:
10562#if CPU(X86) || CPU(X86_64)
10563if (!Arg::isValidAddrForm(args[0].offset()))
10564OPGEN_RETURN(false);
10565if (!args[1].tmp().isGP())
10566OPGEN_RETURN(false);
10567OPGEN_RETURN(true);
10568#endif
10569break;
10570break;
10571default:
10572break;
10573}
10574break;
10575case Arg::Index:
10576switch (this->args[1].kind()) {
10577case Arg::Tmp:
10578#if CPU(X86) || CPU(X86_64)
10579if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
10580OPGEN_RETURN(false);
10581if (!args[1].tmp().isGP())
10582OPGEN_RETURN(false);
10583OPGEN_RETURN(true);
10584#endif
10585break;
10586break;
10587default:
10588break;
10589}
10590break;
10591default:
10592break;
10593}
10594break;
10595default:
10596break;
10597}
10598break;
10599case Opcode::SignExtend16To32:
10600switch (this->args.size()) {
10601case 2:
10602switch (this->args[0].kind()) {
10603case Arg::Tmp:
10604switch (this->args[1].kind()) {
10605case Arg::Tmp:
10606if (!args[0].tmp().isGP())
10607OPGEN_RETURN(false);
10608if (!args[1].tmp().isGP())
10609OPGEN_RETURN(false);
10610OPGEN_RETURN(true);
10611break;
10612break;
10613default:
10614break;
10615}
10616break;
10617case Arg::Addr:
10618case Arg::Stack:
10619case Arg::CallArg:
10620switch (this->args[1].kind()) {
10621case Arg::Tmp:
10622#if CPU(X86) || CPU(X86_64)
10623if (!Arg::isValidAddrForm(args[0].offset()))
10624OPGEN_RETURN(false);
10625if (!args[1].tmp().isGP())
10626OPGEN_RETURN(false);
10627OPGEN_RETURN(true);
10628#endif
10629break;
10630break;
10631default:
10632break;
10633}
10634break;
10635case Arg::Index:
10636switch (this->args[1].kind()) {
10637case Arg::Tmp:
10638#if CPU(X86) || CPU(X86_64)
10639if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
10640OPGEN_RETURN(false);
10641if (!args[1].tmp().isGP())
10642OPGEN_RETURN(false);
10643OPGEN_RETURN(true);
10644#endif
10645break;
10646break;
10647default:
10648break;
10649}
10650break;
10651default:
10652break;
10653}
10654break;
10655default:
10656break;
10657}
10658break;
10659case Opcode::MoveFloat:
10660switch (this->args.size()) {
10661case 2:
10662switch (this->args[0].kind()) {
10663case Arg::Tmp:
10664switch (this->args[1].kind()) {
10665case Arg::Tmp:
10666if (!args[0].tmp().isFP())
10667OPGEN_RETURN(false);
10668if (!args[1].tmp().isFP())
10669OPGEN_RETURN(false);
10670OPGEN_RETURN(true);
10671break;
10672break;
10673case Arg::Addr:
10674case Arg::Stack:
10675case Arg::CallArg:
10676if (!args[0].tmp().isFP())
10677OPGEN_RETURN(false);
10678if (!Arg::isValidAddrForm(args[1].offset()))
10679OPGEN_RETURN(false);
10680OPGEN_RETURN(true);
10681break;
10682break;
10683case Arg::Index:
10684if (!args[0].tmp().isFP())
10685OPGEN_RETURN(false);
10686if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10687OPGEN_RETURN(false);
10688OPGEN_RETURN(true);
10689break;
10690break;
10691default:
10692break;
10693}
10694break;
10695case Arg::Addr:
10696case Arg::Stack:
10697case Arg::CallArg:
10698switch (this->args[1].kind()) {
10699case Arg::Tmp:
10700if (!Arg::isValidAddrForm(args[0].offset()))
10701OPGEN_RETURN(false);
10702if (!args[1].tmp().isFP())
10703OPGEN_RETURN(false);
10704OPGEN_RETURN(true);
10705break;
10706break;
10707default:
10708break;
10709}
10710break;
10711case Arg::Index:
10712switch (this->args[1].kind()) {
10713case Arg::Tmp:
10714if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10715OPGEN_RETURN(false);
10716if (!args[1].tmp().isFP())
10717OPGEN_RETURN(false);
10718OPGEN_RETURN(true);
10719break;
10720break;
10721default:
10722break;
10723}
10724break;
10725default:
10726break;
10727}
10728break;
10729case 3:
10730switch (this->args[0].kind()) {
10731case Arg::Addr:
10732case Arg::Stack:
10733case Arg::CallArg:
10734switch (this->args[1].kind()) {
10735case Arg::Addr:
10736case Arg::Stack:
10737case Arg::CallArg:
10738switch (this->args[2].kind()) {
10739case Arg::Tmp:
10740if (!Arg::isValidAddrForm(args[0].offset()))
10741OPGEN_RETURN(false);
10742if (!Arg::isValidAddrForm(args[1].offset()))
10743OPGEN_RETURN(false);
10744if (!args[2].tmp().isFP())
10745OPGEN_RETURN(false);
10746OPGEN_RETURN(true);
10747break;
10748break;
10749default:
10750break;
10751}
10752break;
10753default:
10754break;
10755}
10756break;
10757default:
10758break;
10759}
10760break;
10761default:
10762break;
10763}
10764break;
10765case Opcode::MoveDouble:
10766switch (this->args.size()) {
10767case 2:
10768switch (this->args[0].kind()) {
10769case Arg::Tmp:
10770switch (this->args[1].kind()) {
10771case Arg::Tmp:
10772if (!args[0].tmp().isFP())
10773OPGEN_RETURN(false);
10774if (!args[1].tmp().isFP())
10775OPGEN_RETURN(false);
10776OPGEN_RETURN(true);
10777break;
10778break;
10779case Arg::Addr:
10780case Arg::Stack:
10781case Arg::CallArg:
10782if (!args[0].tmp().isFP())
10783OPGEN_RETURN(false);
10784if (!Arg::isValidAddrForm(args[1].offset()))
10785OPGEN_RETURN(false);
10786OPGEN_RETURN(true);
10787break;
10788break;
10789case Arg::Index:
10790if (!args[0].tmp().isFP())
10791OPGEN_RETURN(false);
10792if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
10793OPGEN_RETURN(false);
10794OPGEN_RETURN(true);
10795break;
10796break;
10797default:
10798break;
10799}
10800break;
10801case Arg::Addr:
10802case Arg::Stack:
10803case Arg::CallArg:
10804switch (this->args[1].kind()) {
10805case Arg::Tmp:
10806if (!Arg::isValidAddrForm(args[0].offset()))
10807OPGEN_RETURN(false);
10808if (!args[1].tmp().isFP())
10809OPGEN_RETURN(false);
10810OPGEN_RETURN(true);
10811break;
10812break;
10813default:
10814break;
10815}
10816break;
10817case Arg::Index:
10818switch (this->args[1].kind()) {
10819case Arg::Tmp:
10820if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10821OPGEN_RETURN(false);
10822if (!args[1].tmp().isFP())
10823OPGEN_RETURN(false);
10824OPGEN_RETURN(true);
10825break;
10826break;
10827default:
10828break;
10829}
10830break;
10831default:
10832break;
10833}
10834break;
10835case 3:
10836switch (this->args[0].kind()) {
10837case Arg::Addr:
10838case Arg::Stack:
10839case Arg::CallArg:
10840switch (this->args[1].kind()) {
10841case Arg::Addr:
10842case Arg::Stack:
10843case Arg::CallArg:
10844switch (this->args[2].kind()) {
10845case Arg::Tmp:
10846if (!Arg::isValidAddrForm(args[0].offset()))
10847OPGEN_RETURN(false);
10848if (!Arg::isValidAddrForm(args[1].offset()))
10849OPGEN_RETURN(false);
10850if (!args[2].tmp().isFP())
10851OPGEN_RETURN(false);
10852OPGEN_RETURN(true);
10853break;
10854break;
10855default:
10856break;
10857}
10858break;
10859default:
10860break;
10861}
10862break;
10863default:
10864break;
10865}
10866break;
10867default:
10868break;
10869}
10870break;
10871case Opcode::MoveZeroToDouble:
10872switch (this->args.size()) {
10873case 1:
10874switch (this->args[0].kind()) {
10875case Arg::Tmp:
10876if (!args[0].tmp().isFP())
10877OPGEN_RETURN(false);
10878OPGEN_RETURN(true);
10879break;
10880break;
10881default:
10882break;
10883}
10884break;
10885default:
10886break;
10887}
10888break;
10889case Opcode::Move64ToDouble:
10890switch (this->args.size()) {
10891case 2:
10892switch (this->args[0].kind()) {
10893case Arg::Tmp:
10894switch (this->args[1].kind()) {
10895case Arg::Tmp:
10896#if CPU(X86_64) || CPU(ARM64)
10897if (!args[0].tmp().isGP())
10898OPGEN_RETURN(false);
10899if (!args[1].tmp().isFP())
10900OPGEN_RETURN(false);
10901OPGEN_RETURN(true);
10902#endif
10903break;
10904break;
10905default:
10906break;
10907}
10908break;
10909case Arg::Addr:
10910case Arg::Stack:
10911case Arg::CallArg:
10912switch (this->args[1].kind()) {
10913case Arg::Tmp:
10914#if CPU(X86_64)
10915if (!Arg::isValidAddrForm(args[0].offset()))
10916OPGEN_RETURN(false);
10917if (!args[1].tmp().isFP())
10918OPGEN_RETURN(false);
10919OPGEN_RETURN(true);
10920#endif
10921break;
10922break;
10923default:
10924break;
10925}
10926break;
10927case Arg::Index:
10928switch (this->args[1].kind()) {
10929case Arg::Tmp:
10930#if CPU(X86_64) || CPU(ARM64)
10931if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10932OPGEN_RETURN(false);
10933if (!args[1].tmp().isFP())
10934OPGEN_RETURN(false);
10935OPGEN_RETURN(true);
10936#endif
10937break;
10938break;
10939default:
10940break;
10941}
10942break;
10943default:
10944break;
10945}
10946break;
10947default:
10948break;
10949}
10950break;
10951case Opcode::Move32ToFloat:
10952switch (this->args.size()) {
10953case 2:
10954switch (this->args[0].kind()) {
10955case Arg::Tmp:
10956switch (this->args[1].kind()) {
10957case Arg::Tmp:
10958if (!args[0].tmp().isGP())
10959OPGEN_RETURN(false);
10960if (!args[1].tmp().isFP())
10961OPGEN_RETURN(false);
10962OPGEN_RETURN(true);
10963break;
10964break;
10965default:
10966break;
10967}
10968break;
10969case Arg::Addr:
10970case Arg::Stack:
10971case Arg::CallArg:
10972switch (this->args[1].kind()) {
10973case Arg::Tmp:
10974#if CPU(X86) || CPU(X86_64)
10975if (!Arg::isValidAddrForm(args[0].offset()))
10976OPGEN_RETURN(false);
10977if (!args[1].tmp().isFP())
10978OPGEN_RETURN(false);
10979OPGEN_RETURN(true);
10980#endif
10981break;
10982break;
10983default:
10984break;
10985}
10986break;
10987case Arg::Index:
10988switch (this->args[1].kind()) {
10989case Arg::Tmp:
10990if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10991OPGEN_RETURN(false);
10992if (!args[1].tmp().isFP())
10993OPGEN_RETURN(false);
10994OPGEN_RETURN(true);
10995break;
10996break;
10997default:
10998break;
10999}
11000break;
11001default:
11002break;
11003}
11004break;
11005default:
11006break;
11007}
11008break;
11009case Opcode::MoveDoubleTo64:
11010switch (this->args.size()) {
11011case 2:
11012switch (this->args[0].kind()) {
11013case Arg::Tmp:
11014switch (this->args[1].kind()) {
11015case Arg::Tmp:
11016#if CPU(X86_64) || CPU(ARM64)
11017if (!args[0].tmp().isFP())
11018OPGEN_RETURN(false);
11019if (!args[1].tmp().isGP())
11020OPGEN_RETURN(false);
11021OPGEN_RETURN(true);
11022#endif
11023break;
11024break;
11025default:
11026break;
11027}
11028break;
11029case Arg::Addr:
11030case Arg::Stack:
11031case Arg::CallArg:
11032switch (this->args[1].kind()) {
11033case Arg::Tmp:
11034#if CPU(X86_64) || CPU(ARM64)
11035if (!Arg::isValidAddrForm(args[0].offset()))
11036OPGEN_RETURN(false);
11037if (!args[1].tmp().isGP())
11038OPGEN_RETURN(false);
11039OPGEN_RETURN(true);
11040#endif
11041break;
11042break;
11043default:
11044break;
11045}
11046break;
11047case Arg::Index:
11048switch (this->args[1].kind()) {
11049case Arg::Tmp:
11050#if CPU(X86_64) || CPU(ARM64)
11051if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
11052OPGEN_RETURN(false);
11053if (!args[1].tmp().isGP())
11054OPGEN_RETURN(false);
11055OPGEN_RETURN(true);
11056#endif
11057break;
11058break;
11059default:
11060break;
11061}
11062break;
11063default:
11064break;
11065}
11066break;
11067default:
11068break;
11069}
11070break;
11071case Opcode::MoveFloatTo32:
11072switch (this->args.size()) {
11073case 2:
11074switch (this->args[0].kind()) {
11075case Arg::Tmp:
11076switch (this->args[1].kind()) {
11077case Arg::Tmp:
11078if (!args[0].tmp().isFP())
11079OPGEN_RETURN(false);
11080if (!args[1].tmp().isGP())
11081OPGEN_RETURN(false);
11082OPGEN_RETURN(true);
11083break;
11084break;
11085default:
11086break;
11087}
11088break;
11089case Arg::Addr:
11090case Arg::Stack:
11091case Arg::CallArg:
11092switch (this->args[1].kind()) {
11093case Arg::Tmp:
11094if (!Arg::isValidAddrForm(args[0].offset()))
11095OPGEN_RETURN(false);
11096if (!args[1].tmp().isGP())
11097OPGEN_RETURN(false);
11098OPGEN_RETURN(true);
11099break;
11100break;
11101default:
11102break;
11103}
11104break;
11105case Arg::Index:
11106switch (this->args[1].kind()) {
11107case Arg::Tmp:
11108if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
11109OPGEN_RETURN(false);
11110if (!args[1].tmp().isGP())
11111OPGEN_RETURN(false);
11112OPGEN_RETURN(true);
11113break;
11114break;
11115default:
11116break;
11117}
11118break;
11119default:
11120break;
11121}
11122break;
11123default:
11124break;
11125}
11126break;
11127case Opcode::Load8:
11128switch (this->args.size()) {
11129case 2:
11130switch (this->args[0].kind()) {
11131case Arg::Addr:
11132case Arg::Stack:
11133case Arg::CallArg:
11134switch (this->args[1].kind()) {
11135case Arg::Tmp:
11136if (!Arg::isValidAddrForm(args[0].offset()))
11137OPGEN_RETURN(false);
11138if (!args[1].tmp().isGP())
11139OPGEN_RETURN(false);
11140OPGEN_RETURN(true);
11141break;
11142break;
11143default:
11144break;
11145}
11146break;
11147case Arg::Index:
11148switch (this->args[1].kind()) {
11149case Arg::Tmp:
11150if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
11151OPGEN_RETURN(false);
11152if (!args[1].tmp().isGP())
11153OPGEN_RETURN(false);
11154OPGEN_RETURN(true);
11155break;
11156break;
11157default:
11158break;
11159}
11160break;
11161default:
11162break;
11163}
11164break;
11165default:
11166break;
11167}
11168break;
11169case Opcode::LoadAcq8:
11170switch (this->args.size()) {
11171case 2:
11172switch (this->args[0].kind()) {
11173case Arg::SimpleAddr:
11174switch (this->args[1].kind()) {
11175case Arg::Tmp:
11176#if CPU(ARMv7) || CPU(ARM64)
11177if (!args[0].ptr().isGP())
11178OPGEN_RETURN(false);
11179if (!args[1].tmp().isGP())
11180OPGEN_RETURN(false);
11181OPGEN_RETURN(true);
11182#endif
11183break;
11184break;
11185default:
11186break;
11187}
11188break;
11189default:
11190break;
11191}
11192break;
11193default:
11194break;
11195}
11196break;
11197case Opcode::Store8:
11198switch (this->args.size()) {
11199case 2:
11200switch (this->args[0].kind()) {
11201case Arg::Tmp:
11202switch (this->args[1].kind()) {
11203case Arg::Index:
11204if (!args[0].tmp().isGP())
11205OPGEN_RETURN(false);
11206if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11207OPGEN_RETURN(false);
11208OPGEN_RETURN(true);
11209break;
11210break;
11211case Arg::Addr:
11212case Arg::Stack:
11213case Arg::CallArg:
11214if (!args[0].tmp().isGP())
11215OPGEN_RETURN(false);
11216if (!Arg::isValidAddrForm(args[1].offset()))
11217OPGEN_RETURN(false);
11218OPGEN_RETURN(true);
11219break;
11220break;
11221default:
11222break;
11223}
11224break;
11225case Arg::Imm:
11226switch (this->args[1].kind()) {
11227case Arg::Index:
11228#if CPU(X86) || CPU(X86_64)
11229if (!Arg::isValidImmForm(args[0].value()))
11230OPGEN_RETURN(false);
11231if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11232OPGEN_RETURN(false);
11233OPGEN_RETURN(true);
11234#endif
11235break;
11236break;
11237case Arg::Addr:
11238case Arg::Stack:
11239case Arg::CallArg:
11240#if CPU(X86) || CPU(X86_64)
11241if (!Arg::isValidImmForm(args[0].value()))
11242OPGEN_RETURN(false);
11243if (!Arg::isValidAddrForm(args[1].offset()))
11244OPGEN_RETURN(false);
11245OPGEN_RETURN(true);
11246#endif
11247break;
11248break;
11249default:
11250break;
11251}
11252break;
11253default:
11254break;
11255}
11256break;
11257default:
11258break;
11259}
11260break;
11261case Opcode::StoreRel8:
11262switch (this->args.size()) {
11263case 2:
11264switch (this->args[0].kind()) {
11265case Arg::Tmp:
11266switch (this->args[1].kind()) {
11267case Arg::SimpleAddr:
11268#if CPU(ARMv7) || CPU(ARM64)
11269if (!args[0].tmp().isGP())
11270OPGEN_RETURN(false);
11271if (!args[1].ptr().isGP())
11272OPGEN_RETURN(false);
11273OPGEN_RETURN(true);
11274#endif
11275break;
11276break;
11277default:
11278break;
11279}
11280break;
11281default:
11282break;
11283}
11284break;
11285default:
11286break;
11287}
11288break;
11289case Opcode::Load8SignedExtendTo32:
11290switch (this->args.size()) {
11291case 2:
11292switch (this->args[0].kind()) {
11293case Arg::Addr:
11294case Arg::Stack:
11295case Arg::CallArg:
11296switch (this->args[1].kind()) {
11297case Arg::Tmp:
11298if (!Arg::isValidAddrForm(args[0].offset()))
11299OPGEN_RETURN(false);
11300if (!args[1].tmp().isGP())
11301OPGEN_RETURN(false);
11302OPGEN_RETURN(true);
11303break;
11304break;
11305default:
11306break;
11307}
11308break;
11309case Arg::Index:
11310switch (this->args[1].kind()) {
11311case Arg::Tmp:
11312if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
11313OPGEN_RETURN(false);
11314if (!args[1].tmp().isGP())
11315OPGEN_RETURN(false);
11316OPGEN_RETURN(true);
11317break;
11318break;
11319default:
11320break;
11321}
11322break;
11323default:
11324break;
11325}
11326break;
11327default:
11328break;
11329}
11330break;
11331case Opcode::LoadAcq8SignedExtendTo32:
11332switch (this->args.size()) {
11333case 2:
11334switch (this->args[0].kind()) {
11335case Arg::SimpleAddr:
11336switch (this->args[1].kind()) {
11337case Arg::Tmp:
11338#if CPU(ARMv7) || CPU(ARM64)
11339if (!args[0].ptr().isGP())
11340OPGEN_RETURN(false);
11341if (!args[1].tmp().isGP())
11342OPGEN_RETURN(false);
11343OPGEN_RETURN(true);
11344#endif
11345break;
11346break;
11347default:
11348break;
11349}
11350break;
11351default:
11352break;
11353}
11354break;
11355default:
11356break;
11357}
11358break;
11359case Opcode::Load16:
11360switch (this->args.size()) {
11361case 2:
11362switch (this->args[0].kind()) {
11363case Arg::Addr:
11364case Arg::Stack:
11365case Arg::CallArg:
11366switch (this->args[1].kind()) {
11367case Arg::Tmp:
11368if (!Arg::isValidAddrForm(args[0].offset()))
11369OPGEN_RETURN(false);
11370if (!args[1].tmp().isGP())
11371OPGEN_RETURN(false);
11372OPGEN_RETURN(true);
11373break;
11374break;
11375default:
11376break;
11377}
11378break;
11379case Arg::Index:
11380switch (this->args[1].kind()) {
11381case Arg::Tmp:
11382if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
11383OPGEN_RETURN(false);
11384if (!args[1].tmp().isGP())
11385OPGEN_RETURN(false);
11386OPGEN_RETURN(true);
11387break;
11388break;
11389default:
11390break;
11391}
11392break;
11393default:
11394break;
11395}
11396break;
11397default:
11398break;
11399}
11400break;
11401case Opcode::LoadAcq16:
11402switch (this->args.size()) {
11403case 2:
11404switch (this->args[0].kind()) {
11405case Arg::SimpleAddr:
11406switch (this->args[1].kind()) {
11407case Arg::Tmp:
11408#if CPU(ARMv7) || CPU(ARM64)
11409if (!args[0].ptr().isGP())
11410OPGEN_RETURN(false);
11411if (!args[1].tmp().isGP())
11412OPGEN_RETURN(false);
11413OPGEN_RETURN(true);
11414#endif
11415break;
11416break;
11417default:
11418break;
11419}
11420break;
11421default:
11422break;
11423}
11424break;
11425default:
11426break;
11427}
11428break;
11429case Opcode::Load16SignedExtendTo32:
11430switch (this->args.size()) {
11431case 2:
11432switch (this->args[0].kind()) {
11433case Arg::Addr:
11434case Arg::Stack:
11435case Arg::CallArg:
11436switch (this->args[1].kind()) {
11437case Arg::Tmp:
11438if (!Arg::isValidAddrForm(args[0].offset()))
11439OPGEN_RETURN(false);
11440if (!args[1].tmp().isGP())
11441OPGEN_RETURN(false);
11442OPGEN_RETURN(true);
11443break;
11444break;
11445default:
11446break;
11447}
11448break;
11449case Arg::Index:
11450switch (this->args[1].kind()) {
11451case Arg::Tmp:
11452if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
11453OPGEN_RETURN(false);
11454if (!args[1].tmp().isGP())
11455OPGEN_RETURN(false);
11456OPGEN_RETURN(true);
11457break;
11458break;
11459default:
11460break;
11461}
11462break;
11463default:
11464break;
11465}
11466break;
11467default:
11468break;
11469}
11470break;
11471case Opcode::LoadAcq16SignedExtendTo32:
11472switch (this->args.size()) {
11473case 2:
11474switch (this->args[0].kind()) {
11475case Arg::SimpleAddr:
11476switch (this->args[1].kind()) {
11477case Arg::Tmp:
11478#if CPU(ARMv7) || CPU(ARM64)
11479if (!args[0].ptr().isGP())
11480OPGEN_RETURN(false);
11481if (!args[1].tmp().isGP())
11482OPGEN_RETURN(false);
11483OPGEN_RETURN(true);
11484#endif
11485break;
11486break;
11487default:
11488break;
11489}
11490break;
11491default:
11492break;
11493}
11494break;
11495default:
11496break;
11497}
11498break;
11499case Opcode::Store16:
11500switch (this->args.size()) {
11501case 2:
11502switch (this->args[0].kind()) {
11503case Arg::Tmp:
11504switch (this->args[1].kind()) {
11505case Arg::Index:
11506if (!args[0].tmp().isGP())
11507OPGEN_RETURN(false);
11508if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11509OPGEN_RETURN(false);
11510OPGEN_RETURN(true);
11511break;
11512break;
11513case Arg::Addr:
11514case Arg::Stack:
11515case Arg::CallArg:
11516if (!args[0].tmp().isGP())
11517OPGEN_RETURN(false);
11518if (!Arg::isValidAddrForm(args[1].offset()))
11519OPGEN_RETURN(false);
11520OPGEN_RETURN(true);
11521break;
11522break;
11523default:
11524break;
11525}
11526break;
11527case Arg::Imm:
11528switch (this->args[1].kind()) {
11529case Arg::Index:
11530#if CPU(X86) || CPU(X86_64)
11531if (!Arg::isValidImmForm(args[0].value()))
11532OPGEN_RETURN(false);
11533if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11534OPGEN_RETURN(false);
11535OPGEN_RETURN(true);
11536#endif
11537break;
11538break;
11539case Arg::Addr:
11540case Arg::Stack:
11541case Arg::CallArg:
11542#if CPU(X86) || CPU(X86_64)
11543if (!Arg::isValidImmForm(args[0].value()))
11544OPGEN_RETURN(false);
11545if (!Arg::isValidAddrForm(args[1].offset()))
11546OPGEN_RETURN(false);
11547OPGEN_RETURN(true);
11548#endif
11549break;
11550break;
11551default:
11552break;
11553}
11554break;
11555default:
11556break;
11557}
11558break;
11559default:
11560break;
11561}
11562break;
11563case Opcode::StoreRel16:
11564switch (this->args.size()) {
11565case 2:
11566switch (this->args[0].kind()) {
11567case Arg::Tmp:
11568switch (this->args[1].kind()) {
11569case Arg::SimpleAddr:
11570#if CPU(ARMv7) || CPU(ARM64)
11571if (!args[0].tmp().isGP())
11572OPGEN_RETURN(false);
11573if (!args[1].ptr().isGP())
11574OPGEN_RETURN(false);
11575OPGEN_RETURN(true);
11576#endif
11577break;
11578break;
11579default:
11580break;
11581}
11582break;
11583default:
11584break;
11585}
11586break;
11587default:
11588break;
11589}
11590break;
11591case Opcode::LoadAcq32:
11592switch (this->args.size()) {
11593case 2:
11594switch (this->args[0].kind()) {
11595case Arg::SimpleAddr:
11596switch (this->args[1].kind()) {
11597case Arg::Tmp:
11598#if CPU(ARMv7) || CPU(ARM64)
11599if (!args[0].ptr().isGP())
11600OPGEN_RETURN(false);
11601if (!args[1].tmp().isGP())
11602OPGEN_RETURN(false);
11603OPGEN_RETURN(true);
11604#endif
11605break;
11606break;
11607default:
11608break;
11609}
11610break;
11611default:
11612break;
11613}
11614break;
11615default:
11616break;
11617}
11618break;
11619case Opcode::StoreRel32:
11620switch (this->args.size()) {
11621case 2:
11622switch (this->args[0].kind()) {
11623case Arg::Tmp:
11624switch (this->args[1].kind()) {
11625case Arg::SimpleAddr:
11626#if CPU(ARMv7) || CPU(ARM64)
11627if (!args[0].tmp().isGP())
11628OPGEN_RETURN(false);
11629if (!args[1].ptr().isGP())
11630OPGEN_RETURN(false);
11631OPGEN_RETURN(true);
11632#endif
11633break;
11634break;
11635default:
11636break;
11637}
11638break;
11639default:
11640break;
11641}
11642break;
11643default:
11644break;
11645}
11646break;
11647case Opcode::LoadAcq64:
11648switch (this->args.size()) {
11649case 2:
11650switch (this->args[0].kind()) {
11651case Arg::SimpleAddr:
11652switch (this->args[1].kind()) {
11653case Arg::Tmp:
11654#if CPU(ARM64)
11655if (!args[0].ptr().isGP())
11656OPGEN_RETURN(false);
11657if (!args[1].tmp().isGP())
11658OPGEN_RETURN(false);
11659OPGEN_RETURN(true);
11660#endif
11661break;
11662break;
11663default:
11664break;
11665}
11666break;
11667default:
11668break;
11669}
11670break;
11671default:
11672break;
11673}
11674break;
11675case Opcode::StoreRel64:
11676switch (this->args.size()) {
11677case 2:
11678switch (this->args[0].kind()) {
11679case Arg::Tmp:
11680switch (this->args[1].kind()) {
11681case Arg::SimpleAddr:
11682#if CPU(ARM64)
11683if (!args[0].tmp().isGP())
11684OPGEN_RETURN(false);
11685if (!args[1].ptr().isGP())
11686OPGEN_RETURN(false);
11687OPGEN_RETURN(true);
11688#endif
11689break;
11690break;
11691default:
11692break;
11693}
11694break;
11695default:
11696break;
11697}
11698break;
11699default:
11700break;
11701}
11702break;
11703case Opcode::Xchg8:
11704switch (this->args.size()) {
11705case 2:
11706switch (this->args[0].kind()) {
11707case Arg::Tmp:
11708switch (this->args[1].kind()) {
11709case Arg::Addr:
11710case Arg::Stack:
11711case Arg::CallArg:
11712#if CPU(X86) || CPU(X86_64)
11713if (!args[0].tmp().isGP())
11714OPGEN_RETURN(false);
11715if (!Arg::isValidAddrForm(args[1].offset()))
11716OPGEN_RETURN(false);
11717OPGEN_RETURN(true);
11718#endif
11719break;
11720break;
11721case Arg::Index:
11722#if CPU(X86) || CPU(X86_64)
11723if (!args[0].tmp().isGP())
11724OPGEN_RETURN(false);
11725if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11726OPGEN_RETURN(false);
11727OPGEN_RETURN(true);
11728#endif
11729break;
11730break;
11731default:
11732break;
11733}
11734break;
11735default:
11736break;
11737}
11738break;
11739default:
11740break;
11741}
11742break;
11743case Opcode::Xchg16:
11744switch (this->args.size()) {
11745case 2:
11746switch (this->args[0].kind()) {
11747case Arg::Tmp:
11748switch (this->args[1].kind()) {
11749case Arg::Addr:
11750case Arg::Stack:
11751case Arg::CallArg:
11752#if CPU(X86) || CPU(X86_64)
11753if (!args[0].tmp().isGP())
11754OPGEN_RETURN(false);
11755if (!Arg::isValidAddrForm(args[1].offset()))
11756OPGEN_RETURN(false);
11757OPGEN_RETURN(true);
11758#endif
11759break;
11760break;
11761case Arg::Index:
11762#if CPU(X86) || CPU(X86_64)
11763if (!args[0].tmp().isGP())
11764OPGEN_RETURN(false);
11765if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11766OPGEN_RETURN(false);
11767OPGEN_RETURN(true);
11768#endif
11769break;
11770break;
11771default:
11772break;
11773}
11774break;
11775default:
11776break;
11777}
11778break;
11779default:
11780break;
11781}
11782break;
11783case Opcode::Xchg32:
11784switch (this->args.size()) {
11785case 2:
11786switch (this->args[0].kind()) {
11787case Arg::Tmp:
11788switch (this->args[1].kind()) {
11789case Arg::Addr:
11790case Arg::Stack:
11791case Arg::CallArg:
11792#if CPU(X86) || CPU(X86_64)
11793if (!args[0].tmp().isGP())
11794OPGEN_RETURN(false);
11795if (!Arg::isValidAddrForm(args[1].offset()))
11796OPGEN_RETURN(false);
11797OPGEN_RETURN(true);
11798#endif
11799break;
11800break;
11801case Arg::Index:
11802#if CPU(X86) || CPU(X86_64)
11803if (!args[0].tmp().isGP())
11804OPGEN_RETURN(false);
11805if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
11806OPGEN_RETURN(false);
11807OPGEN_RETURN(true);
11808#endif
11809break;
11810break;
11811default:
11812break;
11813}
11814break;
11815default:
11816break;
11817}
11818break;
11819default:
11820break;
11821}
11822break;
11823case Opcode::Xchg64:
11824switch (this->args.size()) {
11825case 2:
11826switch (this->args[0].kind()) {
11827case Arg::Tmp:
11828switch (this->args[1].kind()) {
11829case Arg::Addr:
11830case Arg::Stack:
11831case Arg::CallArg:
11832#if CPU(X86_64)
11833if (!args[0].tmp().isGP())
11834OPGEN_RETURN(false);
11835if (!Arg::isValidAddrForm(args[1].offset()))
11836OPGEN_RETURN(false);
11837OPGEN_RETURN(true);
11838#endif
11839break;
11840break;
11841case Arg::Index:
11842#if CPU(X86_64)
11843if (!args[0].tmp().isGP())
11844OPGEN_RETURN(false);
11845if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
11846OPGEN_RETURN(false);
11847OPGEN_RETURN(true);
11848#endif
11849break;
11850break;
11851default:
11852break;
11853}
11854break;
11855default:
11856break;
11857}
11858break;
11859default:
11860break;
11861}
11862break;
11863case Opcode::AtomicStrongCAS8:
11864switch (this->args.size()) {
11865case 5:
11866switch (this->args[0].kind()) {
11867case Arg::StatusCond:
11868switch (this->args[1].kind()) {
11869case Arg::Tmp:
11870switch (this->args[2].kind()) {
11871case Arg::Tmp:
11872switch (this->args[3].kind()) {
11873case Arg::Addr:
11874case Arg::Stack:
11875case Arg::CallArg:
11876switch (this->args[4].kind()) {
11877case Arg::Tmp:
11878#if CPU(X86) || CPU(X86_64)
11879if (!args[1].tmp().isGP())
11880OPGEN_RETURN(false);
11881if (!args[2].tmp().isGP())
11882OPGEN_RETURN(false);
11883if (!Arg::isValidAddrForm(args[3].offset()))
11884OPGEN_RETURN(false);
11885if (!args[4].tmp().isGP())
11886OPGEN_RETURN(false);
11887if (!isAtomicStrongCAS8Valid(*this))
11888OPGEN_RETURN(false);
11889OPGEN_RETURN(true);
11890#endif
11891break;
11892break;
11893default:
11894break;
11895}
11896break;
11897case Arg::Index:
11898switch (this->args[4].kind()) {
11899case Arg::Tmp:
11900#if CPU(X86) || CPU(X86_64)
11901if (!args[1].tmp().isGP())
11902OPGEN_RETURN(false);
11903if (!args[2].tmp().isGP())
11904OPGEN_RETURN(false);
11905if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width8))
11906OPGEN_RETURN(false);
11907if (!args[4].tmp().isGP())
11908OPGEN_RETURN(false);
11909if (!isAtomicStrongCAS8Valid(*this))
11910OPGEN_RETURN(false);
11911OPGEN_RETURN(true);
11912#endif
11913break;
11914break;
11915default:
11916break;
11917}
11918break;
11919default:
11920break;
11921}
11922break;
11923default:
11924break;
11925}
11926break;
11927default:
11928break;
11929}
11930break;
11931default:
11932break;
11933}
11934break;
11935case 3:
11936switch (this->args[0].kind()) {
11937case Arg::Tmp:
11938switch (this->args[1].kind()) {
11939case Arg::Tmp:
11940switch (this->args[2].kind()) {
11941case Arg::Addr:
11942case Arg::Stack:
11943case Arg::CallArg:
11944#if CPU(X86) || CPU(X86_64)
11945if (!args[0].tmp().isGP())
11946OPGEN_RETURN(false);
11947if (!args[1].tmp().isGP())
11948OPGEN_RETURN(false);
11949if (!Arg::isValidAddrForm(args[2].offset()))
11950OPGEN_RETURN(false);
11951if (!isAtomicStrongCAS8Valid(*this))
11952OPGEN_RETURN(false);
11953OPGEN_RETURN(true);
11954#endif
11955break;
11956break;
11957case Arg::Index:
11958#if CPU(X86) || CPU(X86_64)
11959if (!args[0].tmp().isGP())
11960OPGEN_RETURN(false);
11961if (!args[1].tmp().isGP())
11962OPGEN_RETURN(false);
11963if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width8))
11964OPGEN_RETURN(false);
11965if (!isAtomicStrongCAS8Valid(*this))
11966OPGEN_RETURN(false);
11967OPGEN_RETURN(true);
11968#endif
11969break;
11970break;
11971default:
11972break;
11973}
11974break;
11975default:
11976break;
11977}
11978break;
11979default:
11980break;
11981}
11982break;
11983default:
11984break;
11985}
11986break;
11987case Opcode::AtomicStrongCAS16:
11988switch (this->args.size()) {
11989case 5:
11990switch (this->args[0].kind()) {
11991case Arg::StatusCond:
11992switch (this->args[1].kind()) {
11993case Arg::Tmp:
11994switch (this->args[2].kind()) {
11995case Arg::Tmp:
11996switch (this->args[3].kind()) {
11997case Arg::Addr:
11998case Arg::Stack:
11999case Arg::CallArg:
12000switch (this->args[4].kind()) {
12001case Arg::Tmp:
12002#if CPU(X86) || CPU(X86_64)
12003if (!args[1].tmp().isGP())
12004OPGEN_RETURN(false);
12005if (!args[2].tmp().isGP())
12006OPGEN_RETURN(false);
12007if (!Arg::isValidAddrForm(args[3].offset()))
12008OPGEN_RETURN(false);
12009if (!args[4].tmp().isGP())
12010OPGEN_RETURN(false);
12011if (!isAtomicStrongCAS16Valid(*this))
12012OPGEN_RETURN(false);
12013OPGEN_RETURN(true);
12014#endif
12015break;
12016break;
12017default:
12018break;
12019}
12020break;
12021case Arg::Index:
12022switch (this->args[4].kind()) {
12023case Arg::Tmp:
12024#if CPU(X86) || CPU(X86_64)
12025if (!args[1].tmp().isGP())
12026OPGEN_RETURN(false);
12027if (!args[2].tmp().isGP())
12028OPGEN_RETURN(false);
12029if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width16))
12030OPGEN_RETURN(false);
12031if (!args[4].tmp().isGP())
12032OPGEN_RETURN(false);
12033if (!isAtomicStrongCAS16Valid(*this))
12034OPGEN_RETURN(false);
12035OPGEN_RETURN(true);
12036#endif
12037break;
12038break;
12039default:
12040break;
12041}
12042break;
12043default:
12044break;
12045}
12046break;
12047default:
12048break;
12049}
12050break;
12051default:
12052break;
12053}
12054break;
12055default:
12056break;
12057}
12058break;
12059case 3:
12060switch (this->args[0].kind()) {
12061case Arg::Tmp:
12062switch (this->args[1].kind()) {
12063case Arg::Tmp:
12064switch (this->args[2].kind()) {
12065case Arg::Addr:
12066case Arg::Stack:
12067case Arg::CallArg:
12068#if CPU(X86) || CPU(X86_64)
12069if (!args[0].tmp().isGP())
12070OPGEN_RETURN(false);
12071if (!args[1].tmp().isGP())
12072OPGEN_RETURN(false);
12073if (!Arg::isValidAddrForm(args[2].offset()))
12074OPGEN_RETURN(false);
12075if (!isAtomicStrongCAS16Valid(*this))
12076OPGEN_RETURN(false);
12077OPGEN_RETURN(true);
12078#endif
12079break;
12080break;
12081case Arg::Index:
12082#if CPU(X86) || CPU(X86_64)
12083if (!args[0].tmp().isGP())
12084OPGEN_RETURN(false);
12085if (!args[1].tmp().isGP())
12086OPGEN_RETURN(false);
12087if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width16))
12088OPGEN_RETURN(false);
12089if (!isAtomicStrongCAS16Valid(*this))
12090OPGEN_RETURN(false);
12091OPGEN_RETURN(true);
12092#endif
12093break;
12094break;
12095default:
12096break;
12097}
12098break;
12099default:
12100break;
12101}
12102break;
12103default:
12104break;
12105}
12106break;
12107default:
12108break;
12109}
12110break;
12111case Opcode::AtomicStrongCAS32:
12112switch (this->args.size()) {
12113case 5:
12114switch (this->args[0].kind()) {
12115case Arg::StatusCond:
12116switch (this->args[1].kind()) {
12117case Arg::Tmp:
12118switch (this->args[2].kind()) {
12119case Arg::Tmp:
12120switch (this->args[3].kind()) {
12121case Arg::Addr:
12122case Arg::Stack:
12123case Arg::CallArg:
12124switch (this->args[4].kind()) {
12125case Arg::Tmp:
12126#if CPU(X86) || CPU(X86_64)
12127if (!args[1].tmp().isGP())
12128OPGEN_RETURN(false);
12129if (!args[2].tmp().isGP())
12130OPGEN_RETURN(false);
12131if (!Arg::isValidAddrForm(args[3].offset()))
12132OPGEN_RETURN(false);
12133if (!args[4].tmp().isGP())
12134OPGEN_RETURN(false);
12135if (!isAtomicStrongCAS32Valid(*this))
12136OPGEN_RETURN(false);
12137OPGEN_RETURN(true);
12138#endif
12139break;
12140break;
12141default:
12142break;
12143}
12144break;
12145case Arg::Index:
12146switch (this->args[4].kind()) {
12147case Arg::Tmp:
12148#if CPU(X86) || CPU(X86_64)
12149if (!args[1].tmp().isGP())
12150OPGEN_RETURN(false);
12151if (!args[2].tmp().isGP())
12152OPGEN_RETURN(false);
12153if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width32))
12154OPGEN_RETURN(false);
12155if (!args[4].tmp().isGP())
12156OPGEN_RETURN(false);
12157if (!isAtomicStrongCAS32Valid(*this))
12158OPGEN_RETURN(false);
12159OPGEN_RETURN(true);
12160#endif
12161break;
12162break;
12163default:
12164break;
12165}
12166break;
12167default:
12168break;
12169}
12170break;
12171default:
12172break;
12173}
12174break;
12175default:
12176break;
12177}
12178break;
12179default:
12180break;
12181}
12182break;
12183case 3:
12184switch (this->args[0].kind()) {
12185case Arg::Tmp:
12186switch (this->args[1].kind()) {
12187case Arg::Tmp:
12188switch (this->args[2].kind()) {
12189case Arg::Addr:
12190case Arg::Stack:
12191case Arg::CallArg:
12192#if CPU(X86) || CPU(X86_64)
12193if (!args[0].tmp().isGP())
12194OPGEN_RETURN(false);
12195if (!args[1].tmp().isGP())
12196OPGEN_RETURN(false);
12197if (!Arg::isValidAddrForm(args[2].offset()))
12198OPGEN_RETURN(false);
12199if (!isAtomicStrongCAS32Valid(*this))
12200OPGEN_RETURN(false);
12201OPGEN_RETURN(true);
12202#endif
12203break;
12204break;
12205case Arg::Index:
12206#if CPU(X86) || CPU(X86_64)
12207if (!args[0].tmp().isGP())
12208OPGEN_RETURN(false);
12209if (!args[1].tmp().isGP())
12210OPGEN_RETURN(false);
12211if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width32))
12212OPGEN_RETURN(false);
12213if (!isAtomicStrongCAS32Valid(*this))
12214OPGEN_RETURN(false);
12215OPGEN_RETURN(true);
12216#endif
12217break;
12218break;
12219default:
12220break;
12221}
12222break;
12223default:
12224break;
12225}
12226break;
12227default:
12228break;
12229}
12230break;
12231default:
12232break;
12233}
12234break;
12235case Opcode::AtomicStrongCAS64:
12236switch (this->args.size()) {
12237case 5:
12238switch (this->args[0].kind()) {
12239case Arg::StatusCond:
12240switch (this->args[1].kind()) {
12241case Arg::Tmp:
12242switch (this->args[2].kind()) {
12243case Arg::Tmp:
12244switch (this->args[3].kind()) {
12245case Arg::Addr:
12246case Arg::Stack:
12247case Arg::CallArg:
12248switch (this->args[4].kind()) {
12249case Arg::Tmp:
12250#if CPU(X86_64)
12251if (!args[1].tmp().isGP())
12252OPGEN_RETURN(false);
12253if (!args[2].tmp().isGP())
12254OPGEN_RETURN(false);
12255if (!Arg::isValidAddrForm(args[3].offset()))
12256OPGEN_RETURN(false);
12257if (!args[4].tmp().isGP())
12258OPGEN_RETURN(false);
12259if (!isAtomicStrongCAS64Valid(*this))
12260OPGEN_RETURN(false);
12261OPGEN_RETURN(true);
12262#endif
12263break;
12264break;
12265default:
12266break;
12267}
12268break;
12269case Arg::Index:
12270switch (this->args[4].kind()) {
12271case Arg::Tmp:
12272#if CPU(X86_64)
12273if (!args[1].tmp().isGP())
12274OPGEN_RETURN(false);
12275if (!args[2].tmp().isGP())
12276OPGEN_RETURN(false);
12277if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width64))
12278OPGEN_RETURN(false);
12279if (!args[4].tmp().isGP())
12280OPGEN_RETURN(false);
12281if (!isAtomicStrongCAS64Valid(*this))
12282OPGEN_RETURN(false);
12283OPGEN_RETURN(true);
12284#endif
12285break;
12286break;
12287default:
12288break;
12289}
12290break;
12291default:
12292break;
12293}
12294break;
12295default:
12296break;
12297}
12298break;
12299default:
12300break;
12301}
12302break;
12303default:
12304break;
12305}
12306break;
12307case 3:
12308switch (this->args[0].kind()) {
12309case Arg::Tmp:
12310switch (this->args[1].kind()) {
12311case Arg::Tmp:
12312switch (this->args[2].kind()) {
12313case Arg::Addr:
12314case Arg::Stack:
12315case Arg::CallArg:
12316#if CPU(X86_64)
12317if (!args[0].tmp().isGP())
12318OPGEN_RETURN(false);
12319if (!args[1].tmp().isGP())
12320OPGEN_RETURN(false);
12321if (!Arg::isValidAddrForm(args[2].offset()))
12322OPGEN_RETURN(false);
12323if (!isAtomicStrongCAS64Valid(*this))
12324OPGEN_RETURN(false);
12325OPGEN_RETURN(true);
12326#endif
12327break;
12328break;
12329case Arg::Index:
12330#if CPU(X86_64)
12331if (!args[0].tmp().isGP())
12332OPGEN_RETURN(false);
12333if (!args[1].tmp().isGP())
12334OPGEN_RETURN(false);
12335if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width64))
12336OPGEN_RETURN(false);
12337if (!isAtomicStrongCAS64Valid(*this))
12338OPGEN_RETURN(false);
12339OPGEN_RETURN(true);
12340#endif
12341break;
12342break;
12343default:
12344break;
12345}
12346break;
12347default:
12348break;
12349}
12350break;
12351default:
12352break;
12353}
12354break;
12355default:
12356break;
12357}
12358break;
12359case Opcode::BranchAtomicStrongCAS8:
12360switch (this->args.size()) {
12361case 4:
12362switch (this->args[0].kind()) {
12363case Arg::StatusCond:
12364switch (this->args[1].kind()) {
12365case Arg::Tmp:
12366switch (this->args[2].kind()) {
12367case Arg::Tmp:
12368switch (this->args[3].kind()) {
12369case Arg::Addr:
12370case Arg::Stack:
12371case Arg::CallArg:
12372#if CPU(X86) || CPU(X86_64)
12373if (!args[1].tmp().isGP())
12374OPGEN_RETURN(false);
12375if (!args[2].tmp().isGP())
12376OPGEN_RETURN(false);
12377if (!Arg::isValidAddrForm(args[3].offset()))
12378OPGEN_RETURN(false);
12379if (!isBranchAtomicStrongCAS8Valid(*this))
12380OPGEN_RETURN(false);
12381OPGEN_RETURN(true);
12382#endif
12383break;
12384break;
12385case Arg::Index:
12386#if CPU(X86) || CPU(X86_64)
12387if (!args[1].tmp().isGP())
12388OPGEN_RETURN(false);
12389if (!args[2].tmp().isGP())
12390OPGEN_RETURN(false);
12391if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width8))
12392OPGEN_RETURN(false);
12393if (!isBranchAtomicStrongCAS8Valid(*this))
12394OPGEN_RETURN(false);
12395OPGEN_RETURN(true);
12396#endif
12397break;
12398break;
12399default:
12400break;
12401}
12402break;
12403default:
12404break;
12405}
12406break;
12407default:
12408break;
12409}
12410break;
12411default:
12412break;
12413}
12414break;
12415default:
12416break;
12417}
12418break;
12419case Opcode::BranchAtomicStrongCAS16:
12420switch (this->args.size()) {
12421case 4:
12422switch (this->args[0].kind()) {
12423case Arg::StatusCond:
12424switch (this->args[1].kind()) {
12425case Arg::Tmp:
12426switch (this->args[2].kind()) {
12427case Arg::Tmp:
12428switch (this->args[3].kind()) {
12429case Arg::Addr:
12430case Arg::Stack:
12431case Arg::CallArg:
12432#if CPU(X86) || CPU(X86_64)
12433if (!args[1].tmp().isGP())
12434OPGEN_RETURN(false);
12435if (!args[2].tmp().isGP())
12436OPGEN_RETURN(false);
12437if (!Arg::isValidAddrForm(args[3].offset()))
12438OPGEN_RETURN(false);
12439if (!isBranchAtomicStrongCAS16Valid(*this))
12440OPGEN_RETURN(false);
12441OPGEN_RETURN(true);
12442#endif
12443break;
12444break;
12445case Arg::Index:
12446#if CPU(X86) || CPU(X86_64)
12447if (!args[1].tmp().isGP())
12448OPGEN_RETURN(false);
12449if (!args[2].tmp().isGP())
12450OPGEN_RETURN(false);
12451if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width16))
12452OPGEN_RETURN(false);
12453if (!isBranchAtomicStrongCAS16Valid(*this))
12454OPGEN_RETURN(false);
12455OPGEN_RETURN(true);
12456#endif
12457break;
12458break;
12459default:
12460break;
12461}
12462break;
12463default:
12464break;
12465}
12466break;
12467default:
12468break;
12469}
12470break;
12471default:
12472break;
12473}
12474break;
12475default:
12476break;
12477}
12478break;
12479case Opcode::BranchAtomicStrongCAS32:
12480switch (this->args.size()) {
12481case 4:
12482switch (this->args[0].kind()) {
12483case Arg::StatusCond:
12484switch (this->args[1].kind()) {
12485case Arg::Tmp:
12486switch (this->args[2].kind()) {
12487case Arg::Tmp:
12488switch (this->args[3].kind()) {
12489case Arg::Addr:
12490case Arg::Stack:
12491case Arg::CallArg:
12492#if CPU(X86) || CPU(X86_64)
12493if (!args[1].tmp().isGP())
12494OPGEN_RETURN(false);
12495if (!args[2].tmp().isGP())
12496OPGEN_RETURN(false);
12497if (!Arg::isValidAddrForm(args[3].offset()))
12498OPGEN_RETURN(false);
12499if (!isBranchAtomicStrongCAS32Valid(*this))
12500OPGEN_RETURN(false);
12501OPGEN_RETURN(true);
12502#endif
12503break;
12504break;
12505case Arg::Index:
12506#if CPU(X86) || CPU(X86_64)
12507if (!args[1].tmp().isGP())
12508OPGEN_RETURN(false);
12509if (!args[2].tmp().isGP())
12510OPGEN_RETURN(false);
12511if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width32))
12512OPGEN_RETURN(false);
12513if (!isBranchAtomicStrongCAS32Valid(*this))
12514OPGEN_RETURN(false);
12515OPGEN_RETURN(true);
12516#endif
12517break;
12518break;
12519default:
12520break;
12521}
12522break;
12523default:
12524break;
12525}
12526break;
12527default:
12528break;
12529}
12530break;
12531default:
12532break;
12533}
12534break;
12535default:
12536break;
12537}
12538break;
12539case Opcode::BranchAtomicStrongCAS64:
12540switch (this->args.size()) {
12541case 4:
12542switch (this->args[0].kind()) {
12543case Arg::StatusCond:
12544switch (this->args[1].kind()) {
12545case Arg::Tmp:
12546switch (this->args[2].kind()) {
12547case Arg::Tmp:
12548switch (this->args[3].kind()) {
12549case Arg::Addr:
12550case Arg::Stack:
12551case Arg::CallArg:
12552#if CPU(X86_64)
12553if (!args[1].tmp().isGP())
12554OPGEN_RETURN(false);
12555if (!args[2].tmp().isGP())
12556OPGEN_RETURN(false);
12557if (!Arg::isValidAddrForm(args[3].offset()))
12558OPGEN_RETURN(false);
12559if (!isBranchAtomicStrongCAS64Valid(*this))
12560OPGEN_RETURN(false);
12561OPGEN_RETURN(true);
12562#endif
12563break;
12564break;
12565case Arg::Index:
12566#if CPU(X86_64)
12567if (!args[1].tmp().isGP())
12568OPGEN_RETURN(false);
12569if (!args[2].tmp().isGP())
12570OPGEN_RETURN(false);
12571if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width64))
12572OPGEN_RETURN(false);
12573if (!isBranchAtomicStrongCAS64Valid(*this))
12574OPGEN_RETURN(false);
12575OPGEN_RETURN(true);
12576#endif
12577break;
12578break;
12579default:
12580break;
12581}
12582break;
12583default:
12584break;
12585}
12586break;
12587default:
12588break;
12589}
12590break;
12591default:
12592break;
12593}
12594break;
12595default:
12596break;
12597}
12598break;
12599case Opcode::AtomicAdd8:
12600switch (this->args.size()) {
12601case 2:
12602switch (this->args[0].kind()) {
12603case Arg::Imm:
12604switch (this->args[1].kind()) {
12605case Arg::Addr:
12606case Arg::Stack:
12607case Arg::CallArg:
12608#if CPU(X86) || CPU(X86_64)
12609if (!Arg::isValidImmForm(args[0].value()))
12610OPGEN_RETURN(false);
12611if (!Arg::isValidAddrForm(args[1].offset()))
12612OPGEN_RETURN(false);
12613OPGEN_RETURN(true);
12614#endif
12615break;
12616break;
12617case Arg::Index:
12618#if CPU(X86) || CPU(X86_64)
12619if (!Arg::isValidImmForm(args[0].value()))
12620OPGEN_RETURN(false);
12621if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12622OPGEN_RETURN(false);
12623OPGEN_RETURN(true);
12624#endif
12625break;
12626break;
12627default:
12628break;
12629}
12630break;
12631case Arg::Tmp:
12632switch (this->args[1].kind()) {
12633case Arg::Addr:
12634case Arg::Stack:
12635case Arg::CallArg:
12636#if CPU(X86) || CPU(X86_64)
12637if (!args[0].tmp().isGP())
12638OPGEN_RETURN(false);
12639if (!Arg::isValidAddrForm(args[1].offset()))
12640OPGEN_RETURN(false);
12641OPGEN_RETURN(true);
12642#endif
12643break;
12644break;
12645case Arg::Index:
12646#if CPU(X86) || CPU(X86_64)
12647if (!args[0].tmp().isGP())
12648OPGEN_RETURN(false);
12649if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12650OPGEN_RETURN(false);
12651OPGEN_RETURN(true);
12652#endif
12653break;
12654break;
12655default:
12656break;
12657}
12658break;
12659default:
12660break;
12661}
12662break;
12663default:
12664break;
12665}
12666break;
12667case Opcode::AtomicAdd16:
12668switch (this->args.size()) {
12669case 2:
12670switch (this->args[0].kind()) {
12671case Arg::Imm:
12672switch (this->args[1].kind()) {
12673case Arg::Addr:
12674case Arg::Stack:
12675case Arg::CallArg:
12676#if CPU(X86) || CPU(X86_64)
12677if (!Arg::isValidImmForm(args[0].value()))
12678OPGEN_RETURN(false);
12679if (!Arg::isValidAddrForm(args[1].offset()))
12680OPGEN_RETURN(false);
12681OPGEN_RETURN(true);
12682#endif
12683break;
12684break;
12685case Arg::Index:
12686#if CPU(X86) || CPU(X86_64)
12687if (!Arg::isValidImmForm(args[0].value()))
12688OPGEN_RETURN(false);
12689if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12690OPGEN_RETURN(false);
12691OPGEN_RETURN(true);
12692#endif
12693break;
12694break;
12695default:
12696break;
12697}
12698break;
12699case Arg::Tmp:
12700switch (this->args[1].kind()) {
12701case Arg::Addr:
12702case Arg::Stack:
12703case Arg::CallArg:
12704#if CPU(X86) || CPU(X86_64)
12705if (!args[0].tmp().isGP())
12706OPGEN_RETURN(false);
12707if (!Arg::isValidAddrForm(args[1].offset()))
12708OPGEN_RETURN(false);
12709OPGEN_RETURN(true);
12710#endif
12711break;
12712break;
12713case Arg::Index:
12714#if CPU(X86) || CPU(X86_64)
12715if (!args[0].tmp().isGP())
12716OPGEN_RETURN(false);
12717if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12718OPGEN_RETURN(false);
12719OPGEN_RETURN(true);
12720#endif
12721break;
12722break;
12723default:
12724break;
12725}
12726break;
12727default:
12728break;
12729}
12730break;
12731default:
12732break;
12733}
12734break;
12735case Opcode::AtomicAdd32:
12736switch (this->args.size()) {
12737case 2:
12738switch (this->args[0].kind()) {
12739case Arg::Imm:
12740switch (this->args[1].kind()) {
12741case Arg::Addr:
12742case Arg::Stack:
12743case Arg::CallArg:
12744#if CPU(X86) || CPU(X86_64)
12745if (!Arg::isValidImmForm(args[0].value()))
12746OPGEN_RETURN(false);
12747if (!Arg::isValidAddrForm(args[1].offset()))
12748OPGEN_RETURN(false);
12749OPGEN_RETURN(true);
12750#endif
12751break;
12752break;
12753case Arg::Index:
12754#if CPU(X86) || CPU(X86_64)
12755if (!Arg::isValidImmForm(args[0].value()))
12756OPGEN_RETURN(false);
12757if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12758OPGEN_RETURN(false);
12759OPGEN_RETURN(true);
12760#endif
12761break;
12762break;
12763default:
12764break;
12765}
12766break;
12767case Arg::Tmp:
12768switch (this->args[1].kind()) {
12769case Arg::Addr:
12770case Arg::Stack:
12771case Arg::CallArg:
12772#if CPU(X86) || CPU(X86_64)
12773if (!args[0].tmp().isGP())
12774OPGEN_RETURN(false);
12775if (!Arg::isValidAddrForm(args[1].offset()))
12776OPGEN_RETURN(false);
12777OPGEN_RETURN(true);
12778#endif
12779break;
12780break;
12781case Arg::Index:
12782#if CPU(X86) || CPU(X86_64)
12783if (!args[0].tmp().isGP())
12784OPGEN_RETURN(false);
12785if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12786OPGEN_RETURN(false);
12787OPGEN_RETURN(true);
12788#endif
12789break;
12790break;
12791default:
12792break;
12793}
12794break;
12795default:
12796break;
12797}
12798break;
12799default:
12800break;
12801}
12802break;
12803case Opcode::AtomicAdd64:
12804switch (this->args.size()) {
12805case 2:
12806switch (this->args[0].kind()) {
12807case Arg::Imm:
12808switch (this->args[1].kind()) {
12809case Arg::Addr:
12810case Arg::Stack:
12811case Arg::CallArg:
12812#if CPU(X86_64)
12813if (!Arg::isValidImmForm(args[0].value()))
12814OPGEN_RETURN(false);
12815if (!Arg::isValidAddrForm(args[1].offset()))
12816OPGEN_RETURN(false);
12817OPGEN_RETURN(true);
12818#endif
12819break;
12820break;
12821case Arg::Index:
12822#if CPU(X86_64)
12823if (!Arg::isValidImmForm(args[0].value()))
12824OPGEN_RETURN(false);
12825if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
12826OPGEN_RETURN(false);
12827OPGEN_RETURN(true);
12828#endif
12829break;
12830break;
12831default:
12832break;
12833}
12834break;
12835case Arg::Tmp:
12836switch (this->args[1].kind()) {
12837case Arg::Addr:
12838case Arg::Stack:
12839case Arg::CallArg:
12840#if CPU(X86_64)
12841if (!args[0].tmp().isGP())
12842OPGEN_RETURN(false);
12843if (!Arg::isValidAddrForm(args[1].offset()))
12844OPGEN_RETURN(false);
12845OPGEN_RETURN(true);
12846#endif
12847break;
12848break;
12849case Arg::Index:
12850#if CPU(X86_64)
12851if (!args[0].tmp().isGP())
12852OPGEN_RETURN(false);
12853if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
12854OPGEN_RETURN(false);
12855OPGEN_RETURN(true);
12856#endif
12857break;
12858break;
12859default:
12860break;
12861}
12862break;
12863default:
12864break;
12865}
12866break;
12867default:
12868break;
12869}
12870break;
12871case Opcode::AtomicSub8:
12872switch (this->args.size()) {
12873case 2:
12874switch (this->args[0].kind()) {
12875case Arg::Imm:
12876switch (this->args[1].kind()) {
12877case Arg::Addr:
12878case Arg::Stack:
12879case Arg::CallArg:
12880#if CPU(X86) || CPU(X86_64)
12881if (!Arg::isValidImmForm(args[0].value()))
12882OPGEN_RETURN(false);
12883if (!Arg::isValidAddrForm(args[1].offset()))
12884OPGEN_RETURN(false);
12885OPGEN_RETURN(true);
12886#endif
12887break;
12888break;
12889case Arg::Index:
12890#if CPU(X86) || CPU(X86_64)
12891if (!Arg::isValidImmForm(args[0].value()))
12892OPGEN_RETURN(false);
12893if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12894OPGEN_RETURN(false);
12895OPGEN_RETURN(true);
12896#endif
12897break;
12898break;
12899default:
12900break;
12901}
12902break;
12903case Arg::Tmp:
12904switch (this->args[1].kind()) {
12905case Arg::Addr:
12906case Arg::Stack:
12907case Arg::CallArg:
12908#if CPU(X86) || CPU(X86_64)
12909if (!args[0].tmp().isGP())
12910OPGEN_RETURN(false);
12911if (!Arg::isValidAddrForm(args[1].offset()))
12912OPGEN_RETURN(false);
12913OPGEN_RETURN(true);
12914#endif
12915break;
12916break;
12917case Arg::Index:
12918#if CPU(X86) || CPU(X86_64)
12919if (!args[0].tmp().isGP())
12920OPGEN_RETURN(false);
12921if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12922OPGEN_RETURN(false);
12923OPGEN_RETURN(true);
12924#endif
12925break;
12926break;
12927default:
12928break;
12929}
12930break;
12931default:
12932break;
12933}
12934break;
12935default:
12936break;
12937}
12938break;
12939case Opcode::AtomicSub16:
12940switch (this->args.size()) {
12941case 2:
12942switch (this->args[0].kind()) {
12943case Arg::Imm:
12944switch (this->args[1].kind()) {
12945case Arg::Addr:
12946case Arg::Stack:
12947case Arg::CallArg:
12948#if CPU(X86) || CPU(X86_64)
12949if (!Arg::isValidImmForm(args[0].value()))
12950OPGEN_RETURN(false);
12951if (!Arg::isValidAddrForm(args[1].offset()))
12952OPGEN_RETURN(false);
12953OPGEN_RETURN(true);
12954#endif
12955break;
12956break;
12957case Arg::Index:
12958#if CPU(X86) || CPU(X86_64)
12959if (!Arg::isValidImmForm(args[0].value()))
12960OPGEN_RETURN(false);
12961if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12962OPGEN_RETURN(false);
12963OPGEN_RETURN(true);
12964#endif
12965break;
12966break;
12967default:
12968break;
12969}
12970break;
12971case Arg::Tmp:
12972switch (this->args[1].kind()) {
12973case Arg::Addr:
12974case Arg::Stack:
12975case Arg::CallArg:
12976#if CPU(X86) || CPU(X86_64)
12977if (!args[0].tmp().isGP())
12978OPGEN_RETURN(false);
12979if (!Arg::isValidAddrForm(args[1].offset()))
12980OPGEN_RETURN(false);
12981OPGEN_RETURN(true);
12982#endif
12983break;
12984break;
12985case Arg::Index:
12986#if CPU(X86) || CPU(X86_64)
12987if (!args[0].tmp().isGP())
12988OPGEN_RETURN(false);
12989if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12990OPGEN_RETURN(false);
12991OPGEN_RETURN(true);
12992#endif
12993break;
12994break;
12995default:
12996break;
12997}
12998break;
12999default:
13000break;
13001}
13002break;
13003default:
13004break;
13005}
13006break;
13007case Opcode::AtomicSub32:
13008switch (this->args.size()) {
13009case 2:
13010switch (this->args[0].kind()) {
13011case Arg::Imm:
13012switch (this->args[1].kind()) {
13013case Arg::Addr:
13014case Arg::Stack:
13015case Arg::CallArg:
13016#if CPU(X86) || CPU(X86_64)
13017if (!Arg::isValidImmForm(args[0].value()))
13018OPGEN_RETURN(false);
13019if (!Arg::isValidAddrForm(args[1].offset()))
13020OPGEN_RETURN(false);
13021OPGEN_RETURN(true);
13022#endif
13023break;
13024break;
13025case Arg::Index:
13026#if CPU(X86) || CPU(X86_64)
13027if (!Arg::isValidImmForm(args[0].value()))
13028OPGEN_RETURN(false);
13029if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13030OPGEN_RETURN(false);
13031OPGEN_RETURN(true);
13032#endif
13033break;
13034break;
13035default:
13036break;
13037}
13038break;
13039case Arg::Tmp:
13040switch (this->args[1].kind()) {
13041case Arg::Addr:
13042case Arg::Stack:
13043case Arg::CallArg:
13044#if CPU(X86) || CPU(X86_64)
13045if (!args[0].tmp().isGP())
13046OPGEN_RETURN(false);
13047if (!Arg::isValidAddrForm(args[1].offset()))
13048OPGEN_RETURN(false);
13049OPGEN_RETURN(true);
13050#endif
13051break;
13052break;
13053case Arg::Index:
13054#if CPU(X86) || CPU(X86_64)
13055if (!args[0].tmp().isGP())
13056OPGEN_RETURN(false);
13057if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13058OPGEN_RETURN(false);
13059OPGEN_RETURN(true);
13060#endif
13061break;
13062break;
13063default:
13064break;
13065}
13066break;
13067default:
13068break;
13069}
13070break;
13071default:
13072break;
13073}
13074break;
13075case Opcode::AtomicSub64:
13076switch (this->args.size()) {
13077case 2:
13078switch (this->args[0].kind()) {
13079case Arg::Imm:
13080switch (this->args[1].kind()) {
13081case Arg::Addr:
13082case Arg::Stack:
13083case Arg::CallArg:
13084#if CPU(X86_64)
13085if (!Arg::isValidImmForm(args[0].value()))
13086OPGEN_RETURN(false);
13087if (!Arg::isValidAddrForm(args[1].offset()))
13088OPGEN_RETURN(false);
13089OPGEN_RETURN(true);
13090#endif
13091break;
13092break;
13093case Arg::Index:
13094#if CPU(X86_64)
13095if (!Arg::isValidImmForm(args[0].value()))
13096OPGEN_RETURN(false);
13097if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13098OPGEN_RETURN(false);
13099OPGEN_RETURN(true);
13100#endif
13101break;
13102break;
13103default:
13104break;
13105}
13106break;
13107case Arg::Tmp:
13108switch (this->args[1].kind()) {
13109case Arg::Addr:
13110case Arg::Stack:
13111case Arg::CallArg:
13112#if CPU(X86_64)
13113if (!args[0].tmp().isGP())
13114OPGEN_RETURN(false);
13115if (!Arg::isValidAddrForm(args[1].offset()))
13116OPGEN_RETURN(false);
13117OPGEN_RETURN(true);
13118#endif
13119break;
13120break;
13121case Arg::Index:
13122#if CPU(X86_64)
13123if (!args[0].tmp().isGP())
13124OPGEN_RETURN(false);
13125if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13126OPGEN_RETURN(false);
13127OPGEN_RETURN(true);
13128#endif
13129break;
13130break;
13131default:
13132break;
13133}
13134break;
13135default:
13136break;
13137}
13138break;
13139default:
13140break;
13141}
13142break;
13143case Opcode::AtomicAnd8:
13144switch (this->args.size()) {
13145case 2:
13146switch (this->args[0].kind()) {
13147case Arg::Imm:
13148switch (this->args[1].kind()) {
13149case Arg::Addr:
13150case Arg::Stack:
13151case Arg::CallArg:
13152#if CPU(X86) || CPU(X86_64)
13153if (!Arg::isValidImmForm(args[0].value()))
13154OPGEN_RETURN(false);
13155if (!Arg::isValidAddrForm(args[1].offset()))
13156OPGEN_RETURN(false);
13157OPGEN_RETURN(true);
13158#endif
13159break;
13160break;
13161case Arg::Index:
13162#if CPU(X86) || CPU(X86_64)
13163if (!Arg::isValidImmForm(args[0].value()))
13164OPGEN_RETURN(false);
13165if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13166OPGEN_RETURN(false);
13167OPGEN_RETURN(true);
13168#endif
13169break;
13170break;
13171default:
13172break;
13173}
13174break;
13175case Arg::Tmp:
13176switch (this->args[1].kind()) {
13177case Arg::Addr:
13178case Arg::Stack:
13179case Arg::CallArg:
13180#if CPU(X86) || CPU(X86_64)
13181if (!args[0].tmp().isGP())
13182OPGEN_RETURN(false);
13183if (!Arg::isValidAddrForm(args[1].offset()))
13184OPGEN_RETURN(false);
13185OPGEN_RETURN(true);
13186#endif
13187break;
13188break;
13189case Arg::Index:
13190#if CPU(X86) || CPU(X86_64)
13191if (!args[0].tmp().isGP())
13192OPGEN_RETURN(false);
13193if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13194OPGEN_RETURN(false);
13195OPGEN_RETURN(true);
13196#endif
13197break;
13198break;
13199default:
13200break;
13201}
13202break;
13203default:
13204break;
13205}
13206break;
13207default:
13208break;
13209}
13210break;
13211case Opcode::AtomicAnd16:
13212switch (this->args.size()) {
13213case 2:
13214switch (this->args[0].kind()) {
13215case Arg::Imm:
13216switch (this->args[1].kind()) {
13217case Arg::Addr:
13218case Arg::Stack:
13219case Arg::CallArg:
13220#if CPU(X86) || CPU(X86_64)
13221if (!Arg::isValidImmForm(args[0].value()))
13222OPGEN_RETURN(false);
13223if (!Arg::isValidAddrForm(args[1].offset()))
13224OPGEN_RETURN(false);
13225OPGEN_RETURN(true);
13226#endif
13227break;
13228break;
13229case Arg::Index:
13230#if CPU(X86) || CPU(X86_64)
13231if (!Arg::isValidImmForm(args[0].value()))
13232OPGEN_RETURN(false);
13233if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13234OPGEN_RETURN(false);
13235OPGEN_RETURN(true);
13236#endif
13237break;
13238break;
13239default:
13240break;
13241}
13242break;
13243case Arg::Tmp:
13244switch (this->args[1].kind()) {
13245case Arg::Addr:
13246case Arg::Stack:
13247case Arg::CallArg:
13248#if CPU(X86) || CPU(X86_64)
13249if (!args[0].tmp().isGP())
13250OPGEN_RETURN(false);
13251if (!Arg::isValidAddrForm(args[1].offset()))
13252OPGEN_RETURN(false);
13253OPGEN_RETURN(true);
13254#endif
13255break;
13256break;
13257case Arg::Index:
13258#if CPU(X86) || CPU(X86_64)
13259if (!args[0].tmp().isGP())
13260OPGEN_RETURN(false);
13261if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13262OPGEN_RETURN(false);
13263OPGEN_RETURN(true);
13264#endif
13265break;
13266break;
13267default:
13268break;
13269}
13270break;
13271default:
13272break;
13273}
13274break;
13275default:
13276break;
13277}
13278break;
13279case Opcode::AtomicAnd32:
13280switch (this->args.size()) {
13281case 2:
13282switch (this->args[0].kind()) {
13283case Arg::Imm:
13284switch (this->args[1].kind()) {
13285case Arg::Addr:
13286case Arg::Stack:
13287case Arg::CallArg:
13288#if CPU(X86) || CPU(X86_64)
13289if (!Arg::isValidImmForm(args[0].value()))
13290OPGEN_RETURN(false);
13291if (!Arg::isValidAddrForm(args[1].offset()))
13292OPGEN_RETURN(false);
13293OPGEN_RETURN(true);
13294#endif
13295break;
13296break;
13297case Arg::Index:
13298#if CPU(X86) || CPU(X86_64)
13299if (!Arg::isValidImmForm(args[0].value()))
13300OPGEN_RETURN(false);
13301if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13302OPGEN_RETURN(false);
13303OPGEN_RETURN(true);
13304#endif
13305break;
13306break;
13307default:
13308break;
13309}
13310break;
13311case Arg::Tmp:
13312switch (this->args[1].kind()) {
13313case Arg::Addr:
13314case Arg::Stack:
13315case Arg::CallArg:
13316#if CPU(X86) || CPU(X86_64)
13317if (!args[0].tmp().isGP())
13318OPGEN_RETURN(false);
13319if (!Arg::isValidAddrForm(args[1].offset()))
13320OPGEN_RETURN(false);
13321OPGEN_RETURN(true);
13322#endif
13323break;
13324break;
13325case Arg::Index:
13326#if CPU(X86) || CPU(X86_64)
13327if (!args[0].tmp().isGP())
13328OPGEN_RETURN(false);
13329if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13330OPGEN_RETURN(false);
13331OPGEN_RETURN(true);
13332#endif
13333break;
13334break;
13335default:
13336break;
13337}
13338break;
13339default:
13340break;
13341}
13342break;
13343default:
13344break;
13345}
13346break;
13347case Opcode::AtomicAnd64:
13348switch (this->args.size()) {
13349case 2:
13350switch (this->args[0].kind()) {
13351case Arg::Imm:
13352switch (this->args[1].kind()) {
13353case Arg::Addr:
13354case Arg::Stack:
13355case Arg::CallArg:
13356#if CPU(X86_64)
13357if (!Arg::isValidImmForm(args[0].value()))
13358OPGEN_RETURN(false);
13359if (!Arg::isValidAddrForm(args[1].offset()))
13360OPGEN_RETURN(false);
13361OPGEN_RETURN(true);
13362#endif
13363break;
13364break;
13365case Arg::Index:
13366#if CPU(X86_64)
13367if (!Arg::isValidImmForm(args[0].value()))
13368OPGEN_RETURN(false);
13369if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13370OPGEN_RETURN(false);
13371OPGEN_RETURN(true);
13372#endif
13373break;
13374break;
13375default:
13376break;
13377}
13378break;
13379case Arg::Tmp:
13380switch (this->args[1].kind()) {
13381case Arg::Addr:
13382case Arg::Stack:
13383case Arg::CallArg:
13384#if CPU(X86_64)
13385if (!args[0].tmp().isGP())
13386OPGEN_RETURN(false);
13387if (!Arg::isValidAddrForm(args[1].offset()))
13388OPGEN_RETURN(false);
13389OPGEN_RETURN(true);
13390#endif
13391break;
13392break;
13393case Arg::Index:
13394#if CPU(X86_64)
13395if (!args[0].tmp().isGP())
13396OPGEN_RETURN(false);
13397if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13398OPGEN_RETURN(false);
13399OPGEN_RETURN(true);
13400#endif
13401break;
13402break;
13403default:
13404break;
13405}
13406break;
13407default:
13408break;
13409}
13410break;
13411default:
13412break;
13413}
13414break;
13415case Opcode::AtomicOr8:
13416switch (this->args.size()) {
13417case 2:
13418switch (this->args[0].kind()) {
13419case Arg::Imm:
13420switch (this->args[1].kind()) {
13421case Arg::Addr:
13422case Arg::Stack:
13423case Arg::CallArg:
13424#if CPU(X86) || CPU(X86_64)
13425if (!Arg::isValidImmForm(args[0].value()))
13426OPGEN_RETURN(false);
13427if (!Arg::isValidAddrForm(args[1].offset()))
13428OPGEN_RETURN(false);
13429OPGEN_RETURN(true);
13430#endif
13431break;
13432break;
13433case Arg::Index:
13434#if CPU(X86) || CPU(X86_64)
13435if (!Arg::isValidImmForm(args[0].value()))
13436OPGEN_RETURN(false);
13437if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13438OPGEN_RETURN(false);
13439OPGEN_RETURN(true);
13440#endif
13441break;
13442break;
13443default:
13444break;
13445}
13446break;
13447case Arg::Tmp:
13448switch (this->args[1].kind()) {
13449case Arg::Addr:
13450case Arg::Stack:
13451case Arg::CallArg:
13452#if CPU(X86) || CPU(X86_64)
13453if (!args[0].tmp().isGP())
13454OPGEN_RETURN(false);
13455if (!Arg::isValidAddrForm(args[1].offset()))
13456OPGEN_RETURN(false);
13457OPGEN_RETURN(true);
13458#endif
13459break;
13460break;
13461case Arg::Index:
13462#if CPU(X86) || CPU(X86_64)
13463if (!args[0].tmp().isGP())
13464OPGEN_RETURN(false);
13465if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13466OPGEN_RETURN(false);
13467OPGEN_RETURN(true);
13468#endif
13469break;
13470break;
13471default:
13472break;
13473}
13474break;
13475default:
13476break;
13477}
13478break;
13479default:
13480break;
13481}
13482break;
13483case Opcode::AtomicOr16:
13484switch (this->args.size()) {
13485case 2:
13486switch (this->args[0].kind()) {
13487case Arg::Imm:
13488switch (this->args[1].kind()) {
13489case Arg::Addr:
13490case Arg::Stack:
13491case Arg::CallArg:
13492#if CPU(X86) || CPU(X86_64)
13493if (!Arg::isValidImmForm(args[0].value()))
13494OPGEN_RETURN(false);
13495if (!Arg::isValidAddrForm(args[1].offset()))
13496OPGEN_RETURN(false);
13497OPGEN_RETURN(true);
13498#endif
13499break;
13500break;
13501case Arg::Index:
13502#if CPU(X86) || CPU(X86_64)
13503if (!Arg::isValidImmForm(args[0].value()))
13504OPGEN_RETURN(false);
13505if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13506OPGEN_RETURN(false);
13507OPGEN_RETURN(true);
13508#endif
13509break;
13510break;
13511default:
13512break;
13513}
13514break;
13515case Arg::Tmp:
13516switch (this->args[1].kind()) {
13517case Arg::Addr:
13518case Arg::Stack:
13519case Arg::CallArg:
13520#if CPU(X86) || CPU(X86_64)
13521if (!args[0].tmp().isGP())
13522OPGEN_RETURN(false);
13523if (!Arg::isValidAddrForm(args[1].offset()))
13524OPGEN_RETURN(false);
13525OPGEN_RETURN(true);
13526#endif
13527break;
13528break;
13529case Arg::Index:
13530#if CPU(X86) || CPU(X86_64)
13531if (!args[0].tmp().isGP())
13532OPGEN_RETURN(false);
13533if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13534OPGEN_RETURN(false);
13535OPGEN_RETURN(true);
13536#endif
13537break;
13538break;
13539default:
13540break;
13541}
13542break;
13543default:
13544break;
13545}
13546break;
13547default:
13548break;
13549}
13550break;
13551case Opcode::AtomicOr32:
13552switch (this->args.size()) {
13553case 2:
13554switch (this->args[0].kind()) {
13555case Arg::Imm:
13556switch (this->args[1].kind()) {
13557case Arg::Addr:
13558case Arg::Stack:
13559case Arg::CallArg:
13560#if CPU(X86) || CPU(X86_64)
13561if (!Arg::isValidImmForm(args[0].value()))
13562OPGEN_RETURN(false);
13563if (!Arg::isValidAddrForm(args[1].offset()))
13564OPGEN_RETURN(false);
13565OPGEN_RETURN(true);
13566#endif
13567break;
13568break;
13569case Arg::Index:
13570#if CPU(X86) || CPU(X86_64)
13571if (!Arg::isValidImmForm(args[0].value()))
13572OPGEN_RETURN(false);
13573if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13574OPGEN_RETURN(false);
13575OPGEN_RETURN(true);
13576#endif
13577break;
13578break;
13579default:
13580break;
13581}
13582break;
13583case Arg::Tmp:
13584switch (this->args[1].kind()) {
13585case Arg::Addr:
13586case Arg::Stack:
13587case Arg::CallArg:
13588#if CPU(X86) || CPU(X86_64)
13589if (!args[0].tmp().isGP())
13590OPGEN_RETURN(false);
13591if (!Arg::isValidAddrForm(args[1].offset()))
13592OPGEN_RETURN(false);
13593OPGEN_RETURN(true);
13594#endif
13595break;
13596break;
13597case Arg::Index:
13598#if CPU(X86) || CPU(X86_64)
13599if (!args[0].tmp().isGP())
13600OPGEN_RETURN(false);
13601if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13602OPGEN_RETURN(false);
13603OPGEN_RETURN(true);
13604#endif
13605break;
13606break;
13607default:
13608break;
13609}
13610break;
13611default:
13612break;
13613}
13614break;
13615default:
13616break;
13617}
13618break;
13619case Opcode::AtomicOr64:
13620switch (this->args.size()) {
13621case 2:
13622switch (this->args[0].kind()) {
13623case Arg::Imm:
13624switch (this->args[1].kind()) {
13625case Arg::Addr:
13626case Arg::Stack:
13627case Arg::CallArg:
13628#if CPU(X86_64)
13629if (!Arg::isValidImmForm(args[0].value()))
13630OPGEN_RETURN(false);
13631if (!Arg::isValidAddrForm(args[1].offset()))
13632OPGEN_RETURN(false);
13633OPGEN_RETURN(true);
13634#endif
13635break;
13636break;
13637case Arg::Index:
13638#if CPU(X86_64)
13639if (!Arg::isValidImmForm(args[0].value()))
13640OPGEN_RETURN(false);
13641if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13642OPGEN_RETURN(false);
13643OPGEN_RETURN(true);
13644#endif
13645break;
13646break;
13647default:
13648break;
13649}
13650break;
13651case Arg::Tmp:
13652switch (this->args[1].kind()) {
13653case Arg::Addr:
13654case Arg::Stack:
13655case Arg::CallArg:
13656#if CPU(X86_64)
13657if (!args[0].tmp().isGP())
13658OPGEN_RETURN(false);
13659if (!Arg::isValidAddrForm(args[1].offset()))
13660OPGEN_RETURN(false);
13661OPGEN_RETURN(true);
13662#endif
13663break;
13664break;
13665case Arg::Index:
13666#if CPU(X86_64)
13667if (!args[0].tmp().isGP())
13668OPGEN_RETURN(false);
13669if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13670OPGEN_RETURN(false);
13671OPGEN_RETURN(true);
13672#endif
13673break;
13674break;
13675default:
13676break;
13677}
13678break;
13679default:
13680break;
13681}
13682break;
13683default:
13684break;
13685}
13686break;
13687case Opcode::AtomicXor8:
13688switch (this->args.size()) {
13689case 2:
13690switch (this->args[0].kind()) {
13691case Arg::Imm:
13692switch (this->args[1].kind()) {
13693case Arg::Addr:
13694case Arg::Stack:
13695case Arg::CallArg:
13696#if CPU(X86) || CPU(X86_64)
13697if (!Arg::isValidImmForm(args[0].value()))
13698OPGEN_RETURN(false);
13699if (!Arg::isValidAddrForm(args[1].offset()))
13700OPGEN_RETURN(false);
13701OPGEN_RETURN(true);
13702#endif
13703break;
13704break;
13705case Arg::Index:
13706#if CPU(X86) || CPU(X86_64)
13707if (!Arg::isValidImmForm(args[0].value()))
13708OPGEN_RETURN(false);
13709if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13710OPGEN_RETURN(false);
13711OPGEN_RETURN(true);
13712#endif
13713break;
13714break;
13715default:
13716break;
13717}
13718break;
13719case Arg::Tmp:
13720switch (this->args[1].kind()) {
13721case Arg::Addr:
13722case Arg::Stack:
13723case Arg::CallArg:
13724#if CPU(X86) || CPU(X86_64)
13725if (!args[0].tmp().isGP())
13726OPGEN_RETURN(false);
13727if (!Arg::isValidAddrForm(args[1].offset()))
13728OPGEN_RETURN(false);
13729OPGEN_RETURN(true);
13730#endif
13731break;
13732break;
13733case Arg::Index:
13734#if CPU(X86) || CPU(X86_64)
13735if (!args[0].tmp().isGP())
13736OPGEN_RETURN(false);
13737if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13738OPGEN_RETURN(false);
13739OPGEN_RETURN(true);
13740#endif
13741break;
13742break;
13743default:
13744break;
13745}
13746break;
13747default:
13748break;
13749}
13750break;
13751default:
13752break;
13753}
13754break;
13755case Opcode::AtomicXor16:
13756switch (this->args.size()) {
13757case 2:
13758switch (this->args[0].kind()) {
13759case Arg::Imm:
13760switch (this->args[1].kind()) {
13761case Arg::Addr:
13762case Arg::Stack:
13763case Arg::CallArg:
13764#if CPU(X86) || CPU(X86_64)
13765if (!Arg::isValidImmForm(args[0].value()))
13766OPGEN_RETURN(false);
13767if (!Arg::isValidAddrForm(args[1].offset()))
13768OPGEN_RETURN(false);
13769OPGEN_RETURN(true);
13770#endif
13771break;
13772break;
13773case Arg::Index:
13774#if CPU(X86) || CPU(X86_64)
13775if (!Arg::isValidImmForm(args[0].value()))
13776OPGEN_RETURN(false);
13777if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13778OPGEN_RETURN(false);
13779OPGEN_RETURN(true);
13780#endif
13781break;
13782break;
13783default:
13784break;
13785}
13786break;
13787case Arg::Tmp:
13788switch (this->args[1].kind()) {
13789case Arg::Addr:
13790case Arg::Stack:
13791case Arg::CallArg:
13792#if CPU(X86) || CPU(X86_64)
13793if (!args[0].tmp().isGP())
13794OPGEN_RETURN(false);
13795if (!Arg::isValidAddrForm(args[1].offset()))
13796OPGEN_RETURN(false);
13797OPGEN_RETURN(true);
13798#endif
13799break;
13800break;
13801case Arg::Index:
13802#if CPU(X86) || CPU(X86_64)
13803if (!args[0].tmp().isGP())
13804OPGEN_RETURN(false);
13805if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13806OPGEN_RETURN(false);
13807OPGEN_RETURN(true);
13808#endif
13809break;
13810break;
13811default:
13812break;
13813}
13814break;
13815default:
13816break;
13817}
13818break;
13819default:
13820break;
13821}
13822break;
13823case Opcode::AtomicXor32:
13824switch (this->args.size()) {
13825case 2:
13826switch (this->args[0].kind()) {
13827case Arg::Imm:
13828switch (this->args[1].kind()) {
13829case Arg::Addr:
13830case Arg::Stack:
13831case Arg::CallArg:
13832#if CPU(X86) || CPU(X86_64)
13833if (!Arg::isValidImmForm(args[0].value()))
13834OPGEN_RETURN(false);
13835if (!Arg::isValidAddrForm(args[1].offset()))
13836OPGEN_RETURN(false);
13837OPGEN_RETURN(true);
13838#endif
13839break;
13840break;
13841case Arg::Index:
13842#if CPU(X86) || CPU(X86_64)
13843if (!Arg::isValidImmForm(args[0].value()))
13844OPGEN_RETURN(false);
13845if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13846OPGEN_RETURN(false);
13847OPGEN_RETURN(true);
13848#endif
13849break;
13850break;
13851default:
13852break;
13853}
13854break;
13855case Arg::Tmp:
13856switch (this->args[1].kind()) {
13857case Arg::Addr:
13858case Arg::Stack:
13859case Arg::CallArg:
13860#if CPU(X86) || CPU(X86_64)
13861if (!args[0].tmp().isGP())
13862OPGEN_RETURN(false);
13863if (!Arg::isValidAddrForm(args[1].offset()))
13864OPGEN_RETURN(false);
13865OPGEN_RETURN(true);
13866#endif
13867break;
13868break;
13869case Arg::Index:
13870#if CPU(X86) || CPU(X86_64)
13871if (!args[0].tmp().isGP())
13872OPGEN_RETURN(false);
13873if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13874OPGEN_RETURN(false);
13875OPGEN_RETURN(true);
13876#endif
13877break;
13878break;
13879default:
13880break;
13881}
13882break;
13883default:
13884break;
13885}
13886break;
13887default:
13888break;
13889}
13890break;
13891case Opcode::AtomicXor64:
13892switch (this->args.size()) {
13893case 2:
13894switch (this->args[0].kind()) {
13895case Arg::Imm:
13896switch (this->args[1].kind()) {
13897case Arg::Addr:
13898case Arg::Stack:
13899case Arg::CallArg:
13900#if CPU(X86_64)
13901if (!Arg::isValidImmForm(args[0].value()))
13902OPGEN_RETURN(false);
13903if (!Arg::isValidAddrForm(args[1].offset()))
13904OPGEN_RETURN(false);
13905OPGEN_RETURN(true);
13906#endif
13907break;
13908break;
13909case Arg::Index:
13910#if CPU(X86_64)
13911if (!Arg::isValidImmForm(args[0].value()))
13912OPGEN_RETURN(false);
13913if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13914OPGEN_RETURN(false);
13915OPGEN_RETURN(true);
13916#endif
13917break;
13918break;
13919default:
13920break;
13921}
13922break;
13923case Arg::Tmp:
13924switch (this->args[1].kind()) {
13925case Arg::Addr:
13926case Arg::Stack:
13927case Arg::CallArg:
13928#if CPU(X86_64)
13929if (!args[0].tmp().isGP())
13930OPGEN_RETURN(false);
13931if (!Arg::isValidAddrForm(args[1].offset()))
13932OPGEN_RETURN(false);
13933OPGEN_RETURN(true);
13934#endif
13935break;
13936break;
13937case Arg::Index:
13938#if CPU(X86_64)
13939if (!args[0].tmp().isGP())
13940OPGEN_RETURN(false);
13941if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13942OPGEN_RETURN(false);
13943OPGEN_RETURN(true);
13944#endif
13945break;
13946break;
13947default:
13948break;
13949}
13950break;
13951default:
13952break;
13953}
13954break;
13955default:
13956break;
13957}
13958break;
13959case Opcode::AtomicNeg8:
13960switch (this->args.size()) {
13961case 1:
13962switch (this->args[0].kind()) {
13963case Arg::Addr:
13964case Arg::Stack:
13965case Arg::CallArg:
13966#if CPU(X86) || CPU(X86_64)
13967if (!Arg::isValidAddrForm(args[0].offset()))
13968OPGEN_RETURN(false);
13969OPGEN_RETURN(true);
13970#endif
13971break;
13972break;
13973case Arg::Index:
13974#if CPU(X86) || CPU(X86_64)
13975if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
13976OPGEN_RETURN(false);
13977OPGEN_RETURN(true);
13978#endif
13979break;
13980break;
13981default:
13982break;
13983}
13984break;
13985default:
13986break;
13987}
13988break;
13989case Opcode::AtomicNeg16:
13990switch (this->args.size()) {
13991case 1:
13992switch (this->args[0].kind()) {
13993case Arg::Addr:
13994case Arg::Stack:
13995case Arg::CallArg:
13996#if CPU(X86) || CPU(X86_64)
13997if (!Arg::isValidAddrForm(args[0].offset()))
13998OPGEN_RETURN(false);
13999OPGEN_RETURN(true);
14000#endif
14001break;
14002break;
14003case Arg::Index:
14004#if CPU(X86) || CPU(X86_64)
14005if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
14006OPGEN_RETURN(false);
14007OPGEN_RETURN(true);
14008#endif
14009break;
14010break;
14011default:
14012break;
14013}
14014break;
14015default:
14016break;
14017}
14018break;
14019case Opcode::AtomicNeg32:
14020switch (this->args.size()) {
14021case 1:
14022switch (this->args[0].kind()) {
14023case Arg::Addr:
14024case Arg::Stack:
14025case Arg::CallArg:
14026#if CPU(X86) || CPU(X86_64)
14027if (!Arg::isValidAddrForm(args[0].offset()))
14028OPGEN_RETURN(false);
14029OPGEN_RETURN(true);
14030#endif
14031break;
14032break;
14033case Arg::Index:
14034#if CPU(X86) || CPU(X86_64)
14035if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
14036OPGEN_RETURN(false);
14037OPGEN_RETURN(true);
14038#endif
14039break;
14040break;
14041default:
14042break;
14043}
14044break;
14045default:
14046break;
14047}
14048break;
14049case Opcode::AtomicNeg64:
14050switch (this->args.size()) {
14051case 1:
14052switch (this->args[0].kind()) {
14053case Arg::Addr:
14054case Arg::Stack:
14055case Arg::CallArg:
14056#if CPU(X86_64)
14057if (!Arg::isValidAddrForm(args[0].offset()))
14058OPGEN_RETURN(false);
14059OPGEN_RETURN(true);
14060#endif
14061break;
14062break;
14063case Arg::Index:
14064#if CPU(X86_64)
14065if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
14066OPGEN_RETURN(false);
14067OPGEN_RETURN(true);
14068#endif
14069break;
14070break;
14071default:
14072break;
14073}
14074break;
14075default:
14076break;
14077}
14078break;
14079case Opcode::AtomicNot8:
14080switch (this->args.size()) {
14081case 1:
14082switch (this->args[0].kind()) {
14083case Arg::Addr:
14084case Arg::Stack:
14085case Arg::CallArg:
14086#if CPU(X86) || CPU(X86_64)
14087if (!Arg::isValidAddrForm(args[0].offset()))
14088OPGEN_RETURN(false);
14089OPGEN_RETURN(true);
14090#endif
14091break;
14092break;
14093case Arg::Index:
14094#if CPU(X86) || CPU(X86_64)
14095if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
14096OPGEN_RETURN(false);
14097OPGEN_RETURN(true);
14098#endif
14099break;
14100break;
14101default:
14102break;
14103}
14104break;
14105default:
14106break;
14107}
14108break;
14109case Opcode::AtomicNot16:
14110switch (this->args.size()) {
14111case 1:
14112switch (this->args[0].kind()) {
14113case Arg::Addr:
14114case Arg::Stack:
14115case Arg::CallArg:
14116#if CPU(X86) || CPU(X86_64)
14117if (!Arg::isValidAddrForm(args[0].offset()))
14118OPGEN_RETURN(false);
14119OPGEN_RETURN(true);
14120#endif
14121break;
14122break;
14123case Arg::Index:
14124#if CPU(X86) || CPU(X86_64)
14125if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
14126OPGEN_RETURN(false);
14127OPGEN_RETURN(true);
14128#endif
14129break;
14130break;
14131default:
14132break;
14133}
14134break;
14135default:
14136break;
14137}
14138break;
14139case Opcode::AtomicNot32:
14140switch (this->args.size()) {
14141case 1:
14142switch (this->args[0].kind()) {
14143case Arg::Addr:
14144case Arg::Stack:
14145case Arg::CallArg:
14146#if CPU(X86) || CPU(X86_64)
14147if (!Arg::isValidAddrForm(args[0].offset()))
14148OPGEN_RETURN(false);
14149OPGEN_RETURN(true);
14150#endif
14151break;
14152break;
14153case Arg::Index:
14154#if CPU(X86) || CPU(X86_64)
14155if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
14156OPGEN_RETURN(false);
14157OPGEN_RETURN(true);
14158#endif
14159break;
14160break;
14161default:
14162break;
14163}
14164break;
14165default:
14166break;
14167}
14168break;
14169case Opcode::AtomicNot64:
14170switch (this->args.size()) {
14171case 1:
14172switch (this->args[0].kind()) {
14173case Arg::Addr:
14174case Arg::Stack:
14175case Arg::CallArg:
14176#if CPU(X86_64)
14177if (!Arg::isValidAddrForm(args[0].offset()))
14178OPGEN_RETURN(false);
14179OPGEN_RETURN(true);
14180#endif
14181break;
14182break;
14183case Arg::Index:
14184#if CPU(X86_64)
14185if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
14186OPGEN_RETURN(false);
14187OPGEN_RETURN(true);
14188#endif
14189break;
14190break;
14191default:
14192break;
14193}
14194break;
14195default:
14196break;
14197}
14198break;
14199case Opcode::AtomicXchgAdd8:
14200switch (this->args.size()) {
14201case 2:
14202switch (this->args[0].kind()) {
14203case Arg::Tmp:
14204switch (this->args[1].kind()) {
14205case Arg::Addr:
14206case Arg::Stack:
14207case Arg::CallArg:
14208#if CPU(X86) || CPU(X86_64)
14209if (!args[0].tmp().isGP())
14210OPGEN_RETURN(false);
14211if (!Arg::isValidAddrForm(args[1].offset()))
14212OPGEN_RETURN(false);
14213OPGEN_RETURN(true);
14214#endif
14215break;
14216break;
14217case Arg::Index:
14218#if CPU(X86) || CPU(X86_64)
14219if (!args[0].tmp().isGP())
14220OPGEN_RETURN(false);
14221if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
14222OPGEN_RETURN(false);
14223OPGEN_RETURN(true);
14224#endif
14225break;
14226break;
14227default:
14228break;
14229}
14230break;
14231default:
14232break;
14233}
14234break;
14235default:
14236break;
14237}
14238break;
14239case Opcode::AtomicXchgAdd16:
14240switch (this->args.size()) {
14241case 2:
14242switch (this->args[0].kind()) {
14243case Arg::Tmp:
14244switch (this->args[1].kind()) {
14245case Arg::Addr:
14246case Arg::Stack:
14247case Arg::CallArg:
14248#if CPU(X86) || CPU(X86_64)
14249if (!args[0].tmp().isGP())
14250OPGEN_RETURN(false);
14251if (!Arg::isValidAddrForm(args[1].offset()))
14252OPGEN_RETURN(false);
14253OPGEN_RETURN(true);
14254#endif
14255break;
14256break;
14257case Arg::Index:
14258#if CPU(X86) || CPU(X86_64)
14259if (!args[0].tmp().isGP())
14260OPGEN_RETURN(false);
14261if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
14262OPGEN_RETURN(false);
14263OPGEN_RETURN(true);
14264#endif
14265break;
14266break;
14267default:
14268break;
14269}
14270break;
14271default:
14272break;
14273}
14274break;
14275default:
14276break;
14277}
14278break;
14279case Opcode::AtomicXchgAdd32:
14280switch (this->args.size()) {
14281case 2:
14282switch (this->args[0].kind()) {
14283case Arg::Tmp:
14284switch (this->args[1].kind()) {
14285case Arg::Addr:
14286case Arg::Stack:
14287case Arg::CallArg:
14288#if CPU(X86) || CPU(X86_64)
14289if (!args[0].tmp().isGP())
14290OPGEN_RETURN(false);
14291if (!Arg::isValidAddrForm(args[1].offset()))
14292OPGEN_RETURN(false);
14293OPGEN_RETURN(true);
14294#endif
14295break;
14296break;
14297case Arg::Index:
14298#if CPU(X86) || CPU(X86_64)
14299if (!args[0].tmp().isGP())
14300OPGEN_RETURN(false);
14301if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
14302OPGEN_RETURN(false);
14303OPGEN_RETURN(true);
14304#endif
14305break;
14306break;
14307default:
14308break;
14309}
14310break;
14311default:
14312break;
14313}
14314break;
14315default:
14316break;
14317}
14318break;
14319case Opcode::AtomicXchgAdd64:
14320switch (this->args.size()) {
14321case 2:
14322switch (this->args[0].kind()) {
14323case Arg::Tmp:
14324switch (this->args[1].kind()) {
14325case Arg::Addr:
14326case Arg::Stack:
14327case Arg::CallArg:
14328#if CPU(X86_64)
14329if (!args[0].tmp().isGP())
14330OPGEN_RETURN(false);
14331if (!Arg::isValidAddrForm(args[1].offset()))
14332OPGEN_RETURN(false);
14333OPGEN_RETURN(true);
14334#endif
14335break;
14336break;
14337case Arg::Index:
14338#if CPU(X86_64)
14339if (!args[0].tmp().isGP())
14340OPGEN_RETURN(false);
14341if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
14342OPGEN_RETURN(false);
14343OPGEN_RETURN(true);
14344#endif
14345break;
14346break;
14347default:
14348break;
14349}
14350break;
14351default:
14352break;
14353}
14354break;
14355default:
14356break;
14357}
14358break;
14359case Opcode::AtomicXchg8:
14360switch (this->args.size()) {
14361case 2:
14362switch (this->args[0].kind()) {
14363case Arg::Tmp:
14364switch (this->args[1].kind()) {
14365case Arg::Addr:
14366case Arg::Stack:
14367case Arg::CallArg:
14368#if CPU(X86) || CPU(X86_64)
14369if (!args[0].tmp().isGP())
14370OPGEN_RETURN(false);
14371if (!Arg::isValidAddrForm(args[1].offset()))
14372OPGEN_RETURN(false);
14373OPGEN_RETURN(true);
14374#endif
14375break;
14376break;
14377case Arg::Index:
14378#if CPU(X86) || CPU(X86_64)
14379if (!args[0].tmp().isGP())
14380OPGEN_RETURN(false);
14381if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
14382OPGEN_RETURN(false);
14383OPGEN_RETURN(true);
14384#endif
14385break;
14386break;
14387default:
14388break;
14389}
14390break;
14391default:
14392break;
14393}
14394break;
14395default:
14396break;
14397}
14398break;
14399case Opcode::AtomicXchg16:
14400switch (this->args.size()) {
14401case 2:
14402switch (this->args[0].kind()) {
14403case Arg::Tmp:
14404switch (this->args[1].kind()) {
14405case Arg::Addr:
14406case Arg::Stack:
14407case Arg::CallArg:
14408#if CPU(X86) || CPU(X86_64)
14409if (!args[0].tmp().isGP())
14410OPGEN_RETURN(false);
14411if (!Arg::isValidAddrForm(args[1].offset()))
14412OPGEN_RETURN(false);
14413OPGEN_RETURN(true);
14414#endif
14415break;
14416break;
14417case Arg::Index:
14418#if CPU(X86) || CPU(X86_64)
14419if (!args[0].tmp().isGP())
14420OPGEN_RETURN(false);
14421if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
14422OPGEN_RETURN(false);
14423OPGEN_RETURN(true);
14424#endif
14425break;
14426break;
14427default:
14428break;
14429}
14430break;
14431default:
14432break;
14433}
14434break;
14435default:
14436break;
14437}
14438break;
14439case Opcode::AtomicXchg32:
14440switch (this->args.size()) {
14441case 2:
14442switch (this->args[0].kind()) {
14443case Arg::Tmp:
14444switch (this->args[1].kind()) {
14445case Arg::Addr:
14446case Arg::Stack:
14447case Arg::CallArg:
14448#if CPU(X86) || CPU(X86_64)
14449if (!args[0].tmp().isGP())
14450OPGEN_RETURN(false);
14451if (!Arg::isValidAddrForm(args[1].offset()))
14452OPGEN_RETURN(false);
14453OPGEN_RETURN(true);
14454#endif
14455break;
14456break;
14457case Arg::Index:
14458#if CPU(X86) || CPU(X86_64)
14459if (!args[0].tmp().isGP())
14460OPGEN_RETURN(false);
14461if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
14462OPGEN_RETURN(false);
14463OPGEN_RETURN(true);
14464#endif
14465break;
14466break;
14467default:
14468break;
14469}
14470break;
14471default:
14472break;
14473}
14474break;
14475default:
14476break;
14477}
14478break;
14479case Opcode::AtomicXchg64:
14480switch (this->args.size()) {
14481case 2:
14482switch (this->args[0].kind()) {
14483case Arg::Tmp:
14484switch (this->args[1].kind()) {
14485case Arg::Addr:
14486case Arg::Stack:
14487case Arg::CallArg:
14488#if CPU(X86_64)
14489if (!args[0].tmp().isGP())
14490OPGEN_RETURN(false);
14491if (!Arg::isValidAddrForm(args[1].offset()))
14492OPGEN_RETURN(false);
14493OPGEN_RETURN(true);
14494#endif
14495break;
14496break;
14497case Arg::Index:
14498#if CPU(X86_64)
14499if (!args[0].tmp().isGP())
14500OPGEN_RETURN(false);
14501if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
14502OPGEN_RETURN(false);
14503OPGEN_RETURN(true);
14504#endif
14505break;
14506break;
14507default:
14508break;
14509}
14510break;
14511default:
14512break;
14513}
14514break;
14515default:
14516break;
14517}
14518break;
14519case Opcode::LoadLink8:
14520switch (this->args.size()) {
14521case 2:
14522switch (this->args[0].kind()) {
14523case Arg::SimpleAddr:
14524switch (this->args[1].kind()) {
14525case Arg::Tmp:
14526#if CPU(ARM64)
14527if (!args[0].ptr().isGP())
14528OPGEN_RETURN(false);
14529if (!args[1].tmp().isGP())
14530OPGEN_RETURN(false);
14531OPGEN_RETURN(true);
14532#endif
14533break;
14534break;
14535default:
14536break;
14537}
14538break;
14539default:
14540break;
14541}
14542break;
14543default:
14544break;
14545}
14546break;
14547case Opcode::LoadLinkAcq8:
14548switch (this->args.size()) {
14549case 2:
14550switch (this->args[0].kind()) {
14551case Arg::SimpleAddr:
14552switch (this->args[1].kind()) {
14553case Arg::Tmp:
14554#if CPU(ARM64)
14555if (!args[0].ptr().isGP())
14556OPGEN_RETURN(false);
14557if (!args[1].tmp().isGP())
14558OPGEN_RETURN(false);
14559OPGEN_RETURN(true);
14560#endif
14561break;
14562break;
14563default:
14564break;
14565}
14566break;
14567default:
14568break;
14569}
14570break;
14571default:
14572break;
14573}
14574break;
14575case Opcode::StoreCond8:
14576switch (this->args.size()) {
14577case 3:
14578switch (this->args[0].kind()) {
14579case Arg::Tmp:
14580switch (this->args[1].kind()) {
14581case Arg::SimpleAddr:
14582switch (this->args[2].kind()) {
14583case Arg::Tmp:
14584#if CPU(ARM64)
14585if (!args[0].tmp().isGP())
14586OPGEN_RETURN(false);
14587if (!args[1].ptr().isGP())
14588OPGEN_RETURN(false);
14589if (!args[2].tmp().isGP())
14590OPGEN_RETURN(false);
14591OPGEN_RETURN(true);
14592#endif
14593break;
14594break;
14595default:
14596break;
14597}
14598break;
14599default:
14600break;
14601}
14602break;
14603default:
14604break;
14605}
14606break;
14607default:
14608break;
14609}
14610break;
14611case Opcode::StoreCondRel8:
14612switch (this->args.size()) {
14613case 3:
14614switch (this->args[0].kind()) {
14615case Arg::Tmp:
14616switch (this->args[1].kind()) {
14617case Arg::SimpleAddr:
14618switch (this->args[2].kind()) {
14619case Arg::Tmp:
14620#if CPU(ARM64)
14621if (!args[0].tmp().isGP())
14622OPGEN_RETURN(false);
14623if (!args[1].ptr().isGP())
14624OPGEN_RETURN(false);
14625if (!args[2].tmp().isGP())
14626OPGEN_RETURN(false);
14627OPGEN_RETURN(true);
14628#endif
14629break;
14630break;
14631default:
14632break;
14633}
14634break;
14635default:
14636break;
14637}
14638break;
14639default:
14640break;
14641}
14642break;
14643default:
14644break;
14645}
14646break;
14647case Opcode::LoadLink16:
14648switch (this->args.size()) {
14649case 2:
14650switch (this->args[0].kind()) {
14651case Arg::SimpleAddr:
14652switch (this->args[1].kind()) {
14653case Arg::Tmp:
14654#if CPU(ARM64)
14655if (!args[0].ptr().isGP())
14656OPGEN_RETURN(false);
14657if (!args[1].tmp().isGP())
14658OPGEN_RETURN(false);
14659OPGEN_RETURN(true);
14660#endif
14661break;
14662break;
14663default:
14664break;
14665}
14666break;
14667default:
14668break;
14669}
14670break;
14671default:
14672break;
14673}
14674break;
14675case Opcode::LoadLinkAcq16:
14676switch (this->args.size()) {
14677case 2:
14678switch (this->args[0].kind()) {
14679case Arg::SimpleAddr:
14680switch (this->args[1].kind()) {
14681case Arg::Tmp:
14682#if CPU(ARM64)
14683if (!args[0].ptr().isGP())
14684OPGEN_RETURN(false);
14685if (!args[1].tmp().isGP())
14686OPGEN_RETURN(false);
14687OPGEN_RETURN(true);
14688#endif
14689break;
14690break;
14691default:
14692break;
14693}
14694break;
14695default:
14696break;
14697}
14698break;
14699default:
14700break;
14701}
14702break;
14703case Opcode::StoreCond16:
14704switch (this->args.size()) {
14705case 3:
14706switch (this->args[0].kind()) {
14707case Arg::Tmp:
14708switch (this->args[1].kind()) {
14709case Arg::SimpleAddr:
14710switch (this->args[2].kind()) {
14711case Arg::Tmp:
14712#if CPU(ARM64)
14713if (!args[0].tmp().isGP())
14714OPGEN_RETURN(false);
14715if (!args[1].ptr().isGP())
14716OPGEN_RETURN(false);
14717if (!args[2].tmp().isGP())
14718OPGEN_RETURN(false);
14719OPGEN_RETURN(true);
14720#endif
14721break;
14722break;
14723default:
14724break;
14725}
14726break;
14727default:
14728break;
14729}
14730break;
14731default:
14732break;
14733}
14734break;
14735default:
14736break;
14737}
14738break;
14739case Opcode::StoreCondRel16:
14740switch (this->args.size()) {
14741case 3:
14742switch (this->args[0].kind()) {
14743case Arg::Tmp:
14744switch (this->args[1].kind()) {
14745case Arg::SimpleAddr:
14746switch (this->args[2].kind()) {
14747case Arg::Tmp:
14748#if CPU(ARM64)
14749if (!args[0].tmp().isGP())
14750OPGEN_RETURN(false);
14751if (!args[1].ptr().isGP())
14752OPGEN_RETURN(false);
14753if (!args[2].tmp().isGP())
14754OPGEN_RETURN(false);
14755OPGEN_RETURN(true);
14756#endif
14757break;
14758break;
14759default:
14760break;
14761}
14762break;
14763default:
14764break;
14765}
14766break;
14767default:
14768break;
14769}
14770break;
14771default:
14772break;
14773}
14774break;
14775case Opcode::LoadLink32:
14776switch (this->args.size()) {
14777case 2:
14778switch (this->args[0].kind()) {
14779case Arg::SimpleAddr:
14780switch (this->args[1].kind()) {
14781case Arg::Tmp:
14782#if CPU(ARM64)
14783if (!args[0].ptr().isGP())
14784OPGEN_RETURN(false);
14785if (!args[1].tmp().isGP())
14786OPGEN_RETURN(false);
14787OPGEN_RETURN(true);
14788#endif
14789break;
14790break;
14791default:
14792break;
14793}
14794break;
14795default:
14796break;
14797}
14798break;
14799default:
14800break;
14801}
14802break;
14803case Opcode::LoadLinkAcq32:
14804switch (this->args.size()) {
14805case 2:
14806switch (this->args[0].kind()) {
14807case Arg::SimpleAddr:
14808switch (this->args[1].kind()) {
14809case Arg::Tmp:
14810#if CPU(ARM64)
14811if (!args[0].ptr().isGP())
14812OPGEN_RETURN(false);
14813if (!args[1].tmp().isGP())
14814OPGEN_RETURN(false);
14815OPGEN_RETURN(true);
14816#endif
14817break;
14818break;
14819default:
14820break;
14821}
14822break;
14823default:
14824break;
14825}
14826break;
14827default:
14828break;
14829}
14830break;
14831case Opcode::StoreCond32:
14832switch (this->args.size()) {
14833case 3:
14834switch (this->args[0].kind()) {
14835case Arg::Tmp:
14836switch (this->args[1].kind()) {
14837case Arg::SimpleAddr:
14838switch (this->args[2].kind()) {
14839case Arg::Tmp:
14840#if CPU(ARM64)
14841if (!args[0].tmp().isGP())
14842OPGEN_RETURN(false);
14843if (!args[1].ptr().isGP())
14844OPGEN_RETURN(false);
14845if (!args[2].tmp().isGP())
14846OPGEN_RETURN(false);
14847OPGEN_RETURN(true);
14848#endif
14849break;
14850break;
14851default:
14852break;
14853}
14854break;
14855default:
14856break;
14857}
14858break;
14859default:
14860break;
14861}
14862break;
14863default:
14864break;
14865}
14866break;
14867case Opcode::StoreCondRel32:
14868switch (this->args.size()) {
14869case 3:
14870switch (this->args[0].kind()) {
14871case Arg::Tmp:
14872switch (this->args[1].kind()) {
14873case Arg::SimpleAddr:
14874switch (this->args[2].kind()) {
14875case Arg::Tmp:
14876#if CPU(ARM64)
14877if (!args[0].tmp().isGP())
14878OPGEN_RETURN(false);
14879if (!args[1].ptr().isGP())
14880OPGEN_RETURN(false);
14881if (!args[2].tmp().isGP())
14882OPGEN_RETURN(false);
14883OPGEN_RETURN(true);
14884#endif
14885break;
14886break;
14887default:
14888break;
14889}
14890break;
14891default:
14892break;
14893}
14894break;
14895default:
14896break;
14897}
14898break;
14899default:
14900break;
14901}
14902break;
14903case Opcode::LoadLink64:
14904switch (this->args.size()) {
14905case 2:
14906switch (this->args[0].kind()) {
14907case Arg::SimpleAddr:
14908switch (this->args[1].kind()) {
14909case Arg::Tmp:
14910#if CPU(ARM64)
14911if (!args[0].ptr().isGP())
14912OPGEN_RETURN(false);
14913if (!args[1].tmp().isGP())
14914OPGEN_RETURN(false);
14915OPGEN_RETURN(true);
14916#endif
14917break;
14918break;
14919default:
14920break;
14921}
14922break;
14923default:
14924break;
14925}
14926break;
14927default:
14928break;
14929}
14930break;
14931case Opcode::LoadLinkAcq64:
14932switch (this->args.size()) {
14933case 2:
14934switch (this->args[0].kind()) {
14935case Arg::SimpleAddr:
14936switch (this->args[1].kind()) {
14937case Arg::Tmp:
14938#if CPU(ARM64)
14939if (!args[0].ptr().isGP())
14940OPGEN_RETURN(false);
14941if (!args[1].tmp().isGP())
14942OPGEN_RETURN(false);
14943OPGEN_RETURN(true);
14944#endif
14945break;
14946break;
14947default:
14948break;
14949}
14950break;
14951default:
14952break;
14953}
14954break;
14955default:
14956break;
14957}
14958break;
14959case Opcode::StoreCond64:
14960switch (this->args.size()) {
14961case 3:
14962switch (this->args[0].kind()) {
14963case Arg::Tmp:
14964switch (this->args[1].kind()) {
14965case Arg::SimpleAddr:
14966switch (this->args[2].kind()) {
14967case Arg::Tmp:
14968#if CPU(ARM64)
14969if (!args[0].tmp().isGP())
14970OPGEN_RETURN(false);
14971if (!args[1].ptr().isGP())
14972OPGEN_RETURN(false);
14973if (!args[2].tmp().isGP())
14974OPGEN_RETURN(false);
14975OPGEN_RETURN(true);
14976#endif
14977break;
14978break;
14979default:
14980break;
14981}
14982break;
14983default:
14984break;
14985}
14986break;
14987default:
14988break;
14989}
14990break;
14991default:
14992break;
14993}
14994break;
14995case Opcode::StoreCondRel64:
14996switch (this->args.size()) {
14997case 3:
14998switch (this->args[0].kind()) {
14999case Arg::Tmp:
15000switch (this->args[1].kind()) {
15001case Arg::SimpleAddr:
15002switch (this->args[2].kind()) {
15003case Arg::Tmp:
15004#if CPU(ARM64)
15005if (!args[0].tmp().isGP())
15006OPGEN_RETURN(false);
15007if (!args[1].ptr().isGP())
15008OPGEN_RETURN(false);
15009if (!args[2].tmp().isGP())
15010OPGEN_RETURN(false);
15011OPGEN_RETURN(true);
15012#endif
15013break;
15014break;
15015default:
15016break;
15017}
15018break;
15019default:
15020break;
15021}
15022break;
15023default:
15024break;
15025}
15026break;
15027default:
15028break;
15029}
15030break;
15031case Opcode::Depend32:
15032switch (this->args.size()) {
15033case 2:
15034switch (this->args[0].kind()) {
15035case Arg::Tmp:
15036switch (this->args[1].kind()) {
15037case Arg::Tmp:
15038#if CPU(ARM64)
15039if (!args[0].tmp().isGP())
15040OPGEN_RETURN(false);
15041if (!args[1].tmp().isGP())
15042OPGEN_RETURN(false);
15043OPGEN_RETURN(true);
15044#endif
15045break;
15046break;
15047default:
15048break;
15049}
15050break;
15051default:
15052break;
15053}
15054break;
15055default:
15056break;
15057}
15058break;
15059case Opcode::Depend64:
15060switch (this->args.size()) {
15061case 2:
15062switch (this->args[0].kind()) {
15063case Arg::Tmp:
15064switch (this->args[1].kind()) {
15065case Arg::Tmp:
15066#if CPU(ARM64)
15067if (!args[0].tmp().isGP())
15068OPGEN_RETURN(false);
15069if (!args[1].tmp().isGP())
15070OPGEN_RETURN(false);
15071OPGEN_RETURN(true);
15072#endif
15073break;
15074break;
15075default:
15076break;
15077}
15078break;
15079default:
15080break;
15081}
15082break;
15083default:
15084break;
15085}
15086break;
15087case Opcode::Compare32:
15088switch (this->args.size()) {
15089case 4:
15090switch (this->args[0].kind()) {
15091case Arg::RelCond:
15092switch (this->args[1].kind()) {
15093case Arg::Tmp:
15094switch (this->args[2].kind()) {
15095case Arg::Tmp:
15096switch (this->args[3].kind()) {
15097case Arg::Tmp:
15098if (!args[1].tmp().isGP())
15099OPGEN_RETURN(false);
15100if (!args[2].tmp().isGP())
15101OPGEN_RETURN(false);
15102if (!args[3].tmp().isGP())
15103OPGEN_RETURN(false);
15104OPGEN_RETURN(true);
15105break;
15106break;
15107default:
15108break;
15109}
15110break;
15111case Arg::Imm:
15112switch (this->args[3].kind()) {
15113case Arg::Tmp:
15114if (!args[1].tmp().isGP())
15115OPGEN_RETURN(false);
15116if (!Arg::isValidImmForm(args[2].value()))
15117OPGEN_RETURN(false);
15118if (!args[3].tmp().isGP())
15119OPGEN_RETURN(false);
15120OPGEN_RETURN(true);
15121break;
15122break;
15123default:
15124break;
15125}
15126break;
15127default:
15128break;
15129}
15130break;
15131default:
15132break;
15133}
15134break;
15135default:
15136break;
15137}
15138break;
15139default:
15140break;
15141}
15142break;
15143case Opcode::Compare64:
15144switch (this->args.size()) {
15145case 4:
15146switch (this->args[0].kind()) {
15147case Arg::RelCond:
15148switch (this->args[1].kind()) {
15149case Arg::Tmp:
15150switch (this->args[2].kind()) {
15151case Arg::Tmp:
15152switch (this->args[3].kind()) {
15153case Arg::Tmp:
15154#if CPU(X86_64) || CPU(ARM64)
15155if (!args[1].tmp().isGP())
15156OPGEN_RETURN(false);
15157if (!args[2].tmp().isGP())
15158OPGEN_RETURN(false);
15159if (!args[3].tmp().isGP())
15160OPGEN_RETURN(false);
15161OPGEN_RETURN(true);
15162#endif
15163break;
15164break;
15165default:
15166break;
15167}
15168break;
15169case Arg::Imm:
15170switch (this->args[3].kind()) {
15171case Arg::Tmp:
15172#if CPU(X86_64)
15173if (!args[1].tmp().isGP())
15174OPGEN_RETURN(false);
15175if (!Arg::isValidImmForm(args[2].value()))
15176OPGEN_RETURN(false);
15177if (!args[3].tmp().isGP())
15178OPGEN_RETURN(false);
15179OPGEN_RETURN(true);
15180#endif
15181break;
15182break;
15183default:
15184break;
15185}
15186break;
15187default:
15188break;
15189}
15190break;
15191default:
15192break;
15193}
15194break;
15195default:
15196break;
15197}
15198break;
15199default:
15200break;
15201}
15202break;
15203case Opcode::Test32:
15204switch (this->args.size()) {
15205case 4:
15206switch (this->args[0].kind()) {
15207case Arg::ResCond:
15208switch (this->args[1].kind()) {
15209case Arg::Addr:
15210case Arg::Stack:
15211case Arg::CallArg:
15212switch (this->args[2].kind()) {
15213case Arg::Imm:
15214switch (this->args[3].kind()) {
15215case Arg::Tmp:
15216#if CPU(X86) || CPU(X86_64)
15217if (!Arg::isValidAddrForm(args[1].offset()))
15218OPGEN_RETURN(false);
15219if (!Arg::isValidImmForm(args[2].value()))
15220OPGEN_RETURN(false);
15221if (!args[3].tmp().isGP())
15222OPGEN_RETURN(false);
15223OPGEN_RETURN(true);
15224#endif
15225break;
15226break;
15227default:
15228break;
15229}
15230break;
15231default:
15232break;
15233}
15234break;
15235case Arg::Tmp:
15236switch (this->args[2].kind()) {
15237case Arg::Tmp:
15238switch (this->args[3].kind()) {
15239case Arg::Tmp:
15240if (!args[1].tmp().isGP())
15241OPGEN_RETURN(false);
15242if (!args[2].tmp().isGP())
15243OPGEN_RETURN(false);
15244if (!args[3].tmp().isGP())
15245OPGEN_RETURN(false);
15246OPGEN_RETURN(true);
15247break;
15248break;
15249default:
15250break;
15251}
15252break;
15253case Arg::BitImm:
15254switch (this->args[3].kind()) {
15255case Arg::Tmp:
15256if (!args[1].tmp().isGP())
15257OPGEN_RETURN(false);
15258if (!Arg::isValidBitImmForm(args[2].value()))
15259OPGEN_RETURN(false);
15260if (!args[3].tmp().isGP())
15261OPGEN_RETURN(false);
15262OPGEN_RETURN(true);
15263break;
15264break;
15265default:
15266break;
15267}
15268break;
15269default:
15270break;
15271}
15272break;
15273default:
15274break;
15275}
15276break;
15277default:
15278break;
15279}
15280break;
15281default:
15282break;
15283}
15284break;
15285case Opcode::Test64:
15286switch (this->args.size()) {
15287case 4:
15288switch (this->args[0].kind()) {
15289case Arg::ResCond:
15290switch (this->args[1].kind()) {
15291case Arg::Tmp:
15292switch (this->args[2].kind()) {
15293case Arg::Imm:
15294switch (this->args[3].kind()) {
15295case Arg::Tmp:
15296#if CPU(X86_64)
15297if (!args[1].tmp().isGP())
15298OPGEN_RETURN(false);
15299if (!Arg::isValidImmForm(args[2].value()))
15300OPGEN_RETURN(false);
15301if (!args[3].tmp().isGP())
15302OPGEN_RETURN(false);
15303OPGEN_RETURN(true);
15304#endif
15305break;
15306break;
15307default:
15308break;
15309}
15310break;
15311case Arg::Tmp:
15312switch (this->args[3].kind()) {
15313case Arg::Tmp:
15314#if CPU(X86_64) || CPU(ARM64)
15315if (!args[1].tmp().isGP())
15316OPGEN_RETURN(false);
15317if (!args[2].tmp().isGP())
15318OPGEN_RETURN(false);
15319if (!args[3].tmp().isGP())
15320OPGEN_RETURN(false);
15321OPGEN_RETURN(true);
15322#endif
15323break;
15324break;
15325default:
15326break;
15327}
15328break;
15329default:
15330break;
15331}
15332break;
15333default:
15334break;
15335}
15336break;
15337default:
15338break;
15339}
15340break;
15341default:
15342break;
15343}
15344break;
15345case Opcode::CompareDouble:
15346switch (this->args.size()) {
15347case 4:
15348switch (this->args[0].kind()) {
15349case Arg::DoubleCond:
15350switch (this->args[1].kind()) {
15351case Arg::Tmp:
15352switch (this->args[2].kind()) {
15353case Arg::Tmp:
15354switch (this->args[3].kind()) {
15355case Arg::Tmp:
15356if (!args[1].tmp().isFP())
15357OPGEN_RETURN(false);
15358if (!args[2].tmp().isFP())
15359OPGEN_RETURN(false);
15360if (!args[3].tmp().isGP())
15361OPGEN_RETURN(false);
15362OPGEN_RETURN(true);
15363break;
15364break;
15365default:
15366break;
15367}
15368break;
15369default:
15370break;
15371}
15372break;
15373default:
15374break;
15375}
15376break;
15377default:
15378break;
15379}
15380break;
15381default:
15382break;
15383}
15384break;
15385case Opcode::CompareFloat:
15386switch (this->args.size()) {
15387case 4:
15388switch (this->args[0].kind()) {
15389case Arg::DoubleCond:
15390switch (this->args[1].kind()) {
15391case Arg::Tmp:
15392switch (this->args[2].kind()) {
15393case Arg::Tmp:
15394switch (this->args[3].kind()) {
15395case Arg::Tmp:
15396if (!args[1].tmp().isFP())
15397OPGEN_RETURN(false);
15398if (!args[2].tmp().isFP())
15399OPGEN_RETURN(false);
15400if (!args[3].tmp().isGP())
15401OPGEN_RETURN(false);
15402OPGEN_RETURN(true);
15403break;
15404break;
15405default:
15406break;
15407}
15408break;
15409default:
15410break;
15411}
15412break;
15413default:
15414break;
15415}
15416break;
15417default:
15418break;
15419}
15420break;
15421default:
15422break;
15423}
15424break;
15425case Opcode::Branch8:
15426switch (this->args.size()) {
15427case 3:
15428switch (this->args[0].kind()) {
15429case Arg::RelCond:
15430switch (this->args[1].kind()) {
15431case Arg::Addr:
15432case Arg::Stack:
15433case Arg::CallArg:
15434switch (this->args[2].kind()) {
15435case Arg::Imm:
15436#if CPU(X86) || CPU(X86_64)
15437if (!Arg::isValidAddrForm(args[1].offset()))
15438OPGEN_RETURN(false);
15439if (!Arg::isValidImmForm(args[2].value()))
15440OPGEN_RETURN(false);
15441OPGEN_RETURN(true);
15442#endif
15443break;
15444break;
15445default:
15446break;
15447}
15448break;
15449case Arg::Index:
15450switch (this->args[2].kind()) {
15451case Arg::Imm:
15452#if CPU(X86) || CPU(X86_64)
15453if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
15454OPGEN_RETURN(false);
15455if (!Arg::isValidImmForm(args[2].value()))
15456OPGEN_RETURN(false);
15457OPGEN_RETURN(true);
15458#endif
15459break;
15460break;
15461default:
15462break;
15463}
15464break;
15465default:
15466break;
15467}
15468break;
15469default:
15470break;
15471}
15472break;
15473default:
15474break;
15475}
15476break;
15477case Opcode::Branch32:
15478switch (this->args.size()) {
15479case 3:
15480switch (this->args[0].kind()) {
15481case Arg::RelCond:
15482switch (this->args[1].kind()) {
15483case Arg::Addr:
15484case Arg::Stack:
15485case Arg::CallArg:
15486switch (this->args[2].kind()) {
15487case Arg::Imm:
15488#if CPU(X86) || CPU(X86_64)
15489if (!Arg::isValidAddrForm(args[1].offset()))
15490OPGEN_RETURN(false);
15491if (!Arg::isValidImmForm(args[2].value()))
15492OPGEN_RETURN(false);
15493OPGEN_RETURN(true);
15494#endif
15495break;
15496break;
15497case Arg::Tmp:
15498#if CPU(X86) || CPU(X86_64)
15499if (!Arg::isValidAddrForm(args[1].offset()))
15500OPGEN_RETURN(false);
15501if (!args[2].tmp().isGP())
15502OPGEN_RETURN(false);
15503OPGEN_RETURN(true);
15504#endif
15505break;
15506break;
15507default:
15508break;
15509}
15510break;
15511case Arg::Tmp:
15512switch (this->args[2].kind()) {
15513case Arg::Tmp:
15514if (!args[1].tmp().isGP())
15515OPGEN_RETURN(false);
15516if (!args[2].tmp().isGP())
15517OPGEN_RETURN(false);
15518OPGEN_RETURN(true);
15519break;
15520break;
15521case Arg::Imm:
15522if (!args[1].tmp().isGP())
15523OPGEN_RETURN(false);
15524if (!Arg::isValidImmForm(args[2].value()))
15525OPGEN_RETURN(false);
15526OPGEN_RETURN(true);
15527break;
15528break;
15529case Arg::Addr:
15530case Arg::Stack:
15531case Arg::CallArg:
15532#if CPU(X86) || CPU(X86_64)
15533if (!args[1].tmp().isGP())
15534OPGEN_RETURN(false);
15535if (!Arg::isValidAddrForm(args[2].offset()))
15536OPGEN_RETURN(false);
15537OPGEN_RETURN(true);
15538#endif
15539break;
15540break;
15541default:
15542break;
15543}
15544break;
15545case Arg::Index:
15546switch (this->args[2].kind()) {
15547case Arg::Imm:
15548#if CPU(X86) || CPU(X86_64)
15549if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
15550OPGEN_RETURN(false);
15551if (!Arg::isValidImmForm(args[2].value()))
15552OPGEN_RETURN(false);
15553OPGEN_RETURN(true);
15554#endif
15555break;
15556break;
15557default:
15558break;
15559}
15560break;
15561default:
15562break;
15563}
15564break;
15565default:
15566break;
15567}
15568break;
15569default:
15570break;
15571}
15572break;
15573case Opcode::Branch64:
15574switch (this->args.size()) {
15575case 3:
15576switch (this->args[0].kind()) {
15577case Arg::RelCond:
15578switch (this->args[1].kind()) {
15579case Arg::Tmp:
15580switch (this->args[2].kind()) {
15581case Arg::Tmp:
15582#if CPU(X86_64) || CPU(ARM64)
15583if (!args[1].tmp().isGP())
15584OPGEN_RETURN(false);
15585if (!args[2].tmp().isGP())
15586OPGEN_RETURN(false);
15587OPGEN_RETURN(true);
15588#endif
15589break;
15590break;
15591case Arg::Imm:
15592#if CPU(X86_64) || CPU(ARM64)
15593if (!args[1].tmp().isGP())
15594OPGEN_RETURN(false);
15595if (!Arg::isValidImmForm(args[2].value()))
15596OPGEN_RETURN(false);
15597OPGEN_RETURN(true);
15598#endif
15599break;
15600break;
15601case Arg::Addr:
15602case Arg::Stack:
15603case Arg::CallArg:
15604#if CPU(X86_64)
15605if (!args[1].tmp().isGP())
15606OPGEN_RETURN(false);
15607if (!Arg::isValidAddrForm(args[2].offset()))
15608OPGEN_RETURN(false);
15609OPGEN_RETURN(true);
15610#endif
15611break;
15612break;
15613default:
15614break;
15615}
15616break;
15617case Arg::Addr:
15618case Arg::Stack:
15619case Arg::CallArg:
15620switch (this->args[2].kind()) {
15621case Arg::Tmp:
15622#if CPU(X86_64)
15623if (!Arg::isValidAddrForm(args[1].offset()))
15624OPGEN_RETURN(false);
15625if (!args[2].tmp().isGP())
15626OPGEN_RETURN(false);
15627OPGEN_RETURN(true);
15628#endif
15629break;
15630break;
15631case Arg::Imm:
15632#if CPU(X86_64)
15633if (!Arg::isValidAddrForm(args[1].offset()))
15634OPGEN_RETURN(false);
15635if (!Arg::isValidImmForm(args[2].value()))
15636OPGEN_RETURN(false);
15637OPGEN_RETURN(true);
15638#endif
15639break;
15640break;
15641default:
15642break;
15643}
15644break;
15645case Arg::Index:
15646switch (this->args[2].kind()) {
15647case Arg::Tmp:
15648#if CPU(X86_64)
15649if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
15650OPGEN_RETURN(false);
15651if (!args[2].tmp().isGP())
15652OPGEN_RETURN(false);
15653OPGEN_RETURN(true);
15654#endif
15655break;
15656break;
15657default:
15658break;
15659}
15660break;
15661default:
15662break;
15663}
15664break;
15665default:
15666break;
15667}
15668break;
15669default:
15670break;
15671}
15672break;
15673case Opcode::BranchTest8:
15674switch (this->args.size()) {
15675case 3:
15676switch (this->args[0].kind()) {
15677case Arg::ResCond:
15678switch (this->args[1].kind()) {
15679case Arg::Addr:
15680case Arg::Stack:
15681case Arg::CallArg:
15682switch (this->args[2].kind()) {
15683case Arg::BitImm:
15684#if CPU(X86) || CPU(X86_64)
15685if (!Arg::isValidAddrForm(args[1].offset()))
15686OPGEN_RETURN(false);
15687if (!Arg::isValidBitImmForm(args[2].value()))
15688OPGEN_RETURN(false);
15689OPGEN_RETURN(true);
15690#endif
15691break;
15692break;
15693default:
15694break;
15695}
15696break;
15697case Arg::Index:
15698switch (this->args[2].kind()) {
15699case Arg::BitImm:
15700#if CPU(X86) || CPU(X86_64)
15701if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
15702OPGEN_RETURN(false);
15703if (!Arg::isValidBitImmForm(args[2].value()))
15704OPGEN_RETURN(false);
15705OPGEN_RETURN(true);
15706#endif
15707break;
15708break;
15709default:
15710break;
15711}
15712break;
15713default:
15714break;
15715}
15716break;
15717default:
15718break;
15719}
15720break;
15721default:
15722break;
15723}
15724break;
15725case Opcode::BranchTest32:
15726switch (this->args.size()) {
15727case 3:
15728switch (this->args[0].kind()) {
15729case Arg::ResCond:
15730switch (this->args[1].kind()) {
15731case Arg::Tmp:
15732switch (this->args[2].kind()) {
15733case Arg::Tmp:
15734if (!args[1].tmp().isGP())
15735OPGEN_RETURN(false);
15736if (!args[2].tmp().isGP())
15737OPGEN_RETURN(false);
15738OPGEN_RETURN(true);
15739break;
15740break;
15741case Arg::BitImm:
15742if (!args[1].tmp().isGP())
15743OPGEN_RETURN(false);
15744if (!Arg::isValidBitImmForm(args[2].value()))
15745OPGEN_RETURN(false);
15746OPGEN_RETURN(true);
15747break;
15748break;
15749default:
15750break;
15751}
15752break;
15753case Arg::Addr:
15754case Arg::Stack:
15755case Arg::CallArg:
15756switch (this->args[2].kind()) {
15757case Arg::BitImm:
15758#if CPU(X86) || CPU(X86_64)
15759if (!Arg::isValidAddrForm(args[1].offset()))
15760OPGEN_RETURN(false);
15761if (!Arg::isValidBitImmForm(args[2].value()))
15762OPGEN_RETURN(false);
15763OPGEN_RETURN(true);
15764#endif
15765break;
15766break;
15767default:
15768break;
15769}
15770break;
15771case Arg::Index:
15772switch (this->args[2].kind()) {
15773case Arg::BitImm:
15774#if CPU(X86) || CPU(X86_64)
15775if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
15776OPGEN_RETURN(false);
15777if (!Arg::isValidBitImmForm(args[2].value()))
15778OPGEN_RETURN(false);
15779OPGEN_RETURN(true);
15780#endif
15781break;
15782break;
15783default:
15784break;
15785}
15786break;
15787default:
15788break;
15789}
15790break;
15791default:
15792break;
15793}
15794break;
15795default:
15796break;
15797}
15798break;
15799case Opcode::BranchTest64:
15800switch (this->args.size()) {
15801case 3:
15802switch (this->args[0].kind()) {
15803case Arg::ResCond:
15804switch (this->args[1].kind()) {
15805case Arg::Tmp:
15806switch (this->args[2].kind()) {
15807case Arg::Tmp:
15808#if CPU(X86_64) || CPU(ARM64)
15809if (!args[1].tmp().isGP())
15810OPGEN_RETURN(false);
15811if (!args[2].tmp().isGP())
15812OPGEN_RETURN(false);
15813OPGEN_RETURN(true);
15814#endif
15815break;
15816break;
15817#if USE(JSVALUE64)
15818case Arg::BitImm64:
15819#if CPU(ARM64)
15820if (!args[1].tmp().isGP())
15821OPGEN_RETURN(false);
15822if (!Arg::isValidBitImm64Form(args[2].value()))
15823OPGEN_RETURN(false);
15824OPGEN_RETURN(true);
15825#endif
15826break;
15827break;
15828#endif // USE(JSVALUE64)
15829case Arg::BitImm:
15830#if CPU(X86_64)
15831if (!args[1].tmp().isGP())
15832OPGEN_RETURN(false);
15833if (!Arg::isValidBitImmForm(args[2].value()))
15834OPGEN_RETURN(false);
15835OPGEN_RETURN(true);
15836#endif
15837break;
15838break;
15839default:
15840break;
15841}
15842break;
15843case Arg::Addr:
15844case Arg::Stack:
15845case Arg::CallArg:
15846switch (this->args[2].kind()) {
15847case Arg::BitImm:
15848#if CPU(X86_64)
15849if (!Arg::isValidAddrForm(args[1].offset()))
15850OPGEN_RETURN(false);
15851if (!Arg::isValidBitImmForm(args[2].value()))
15852OPGEN_RETURN(false);
15853OPGEN_RETURN(true);
15854#endif
15855break;
15856break;
15857case Arg::Tmp:
15858#if CPU(X86_64)
15859if (!Arg::isValidAddrForm(args[1].offset()))
15860OPGEN_RETURN(false);
15861if (!args[2].tmp().isGP())
15862OPGEN_RETURN(false);
15863OPGEN_RETURN(true);
15864#endif
15865break;
15866break;
15867default:
15868break;
15869}
15870break;
15871case Arg::Index:
15872switch (this->args[2].kind()) {
15873case Arg::BitImm:
15874#if CPU(X86_64)
15875if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
15876OPGEN_RETURN(false);
15877if (!Arg::isValidBitImmForm(args[2].value()))
15878OPGEN_RETURN(false);
15879OPGEN_RETURN(true);
15880#endif
15881break;
15882break;
15883default:
15884break;
15885}
15886break;
15887default:
15888break;
15889}
15890break;
15891default:
15892break;
15893}
15894break;
15895default:
15896break;
15897}
15898break;
15899case Opcode::BranchTestBit64:
15900switch (this->args.size()) {
15901case 3:
15902switch (this->args[0].kind()) {
15903case Arg::ResCond:
15904switch (this->args[1].kind()) {
15905case Arg::Tmp:
15906switch (this->args[2].kind()) {
15907case Arg::Imm:
15908#if CPU(X86_64)
15909if (!args[1].tmp().isGP())
15910OPGEN_RETURN(false);
15911if (!Arg::isValidImmForm(args[2].value()))
15912OPGEN_RETURN(false);
15913OPGEN_RETURN(true);
15914#endif
15915break;
15916break;
15917case Arg::Tmp:
15918#if CPU(X86_64)
15919if (!args[1].tmp().isGP())
15920OPGEN_RETURN(false);
15921if (!args[2].tmp().isGP())
15922OPGEN_RETURN(false);
15923OPGEN_RETURN(true);
15924#endif
15925break;
15926break;
15927default:
15928break;
15929}
15930break;
15931case Arg::Addr:
15932case Arg::Stack:
15933case Arg::CallArg:
15934switch (this->args[2].kind()) {
15935case Arg::Imm:
15936#if CPU(X86_64)
15937if (!Arg::isValidAddrForm(args[1].offset()))
15938OPGEN_RETURN(false);
15939if (!Arg::isValidImmForm(args[2].value()))
15940OPGEN_RETURN(false);
15941OPGEN_RETURN(true);
15942#endif
15943break;
15944break;
15945default:
15946break;
15947}
15948break;
15949default:
15950break;
15951}
15952break;
15953default:
15954break;
15955}
15956break;
15957default:
15958break;
15959}
15960break;
15961case Opcode::BranchTestBit32:
15962switch (this->args.size()) {
15963case 3:
15964switch (this->args[0].kind()) {
15965case Arg::ResCond:
15966switch (this->args[1].kind()) {
15967case Arg::Tmp:
15968switch (this->args[2].kind()) {
15969case Arg::Imm:
15970#if CPU(X86) || CPU(X86_64)
15971if (!args[1].tmp().isGP())
15972OPGEN_RETURN(false);
15973if (!Arg::isValidImmForm(args[2].value()))
15974OPGEN_RETURN(false);
15975OPGEN_RETURN(true);
15976#endif
15977break;
15978break;
15979case Arg::Tmp:
15980#if CPU(X86) || CPU(X86_64)
15981if (!args[1].tmp().isGP())
15982OPGEN_RETURN(false);
15983if (!args[2].tmp().isGP())
15984OPGEN_RETURN(false);
15985OPGEN_RETURN(true);
15986#endif
15987break;
15988break;
15989default:
15990break;
15991}
15992break;
15993case Arg::Addr:
15994case Arg::Stack:
15995case Arg::CallArg:
15996switch (this->args[2].kind()) {
15997case Arg::Imm:
15998#if CPU(X86) || CPU(X86_64)
15999if (!Arg::isValidAddrForm(args[1].offset()))
16000OPGEN_RETURN(false);
16001if (!Arg::isValidImmForm(args[2].value()))
16002OPGEN_RETURN(false);
16003OPGEN_RETURN(true);
16004#endif
16005break;
16006break;
16007default:
16008break;
16009}
16010break;
16011default:
16012break;
16013}
16014break;
16015default:
16016break;
16017}
16018break;
16019default:
16020break;
16021}
16022break;
16023case Opcode::BranchDouble:
16024switch (this->args.size()) {
16025case 3:
16026switch (this->args[0].kind()) {
16027case Arg::DoubleCond:
16028switch (this->args[1].kind()) {
16029case Arg::Tmp:
16030switch (this->args[2].kind()) {
16031case Arg::Tmp:
16032if (!args[1].tmp().isFP())
16033OPGEN_RETURN(false);
16034if (!args[2].tmp().isFP())
16035OPGEN_RETURN(false);
16036OPGEN_RETURN(true);
16037break;
16038break;
16039default:
16040break;
16041}
16042break;
16043default:
16044break;
16045}
16046break;
16047default:
16048break;
16049}
16050break;
16051default:
16052break;
16053}
16054break;
16055case Opcode::BranchFloat:
16056switch (this->args.size()) {
16057case 3:
16058switch (this->args[0].kind()) {
16059case Arg::DoubleCond:
16060switch (this->args[1].kind()) {
16061case Arg::Tmp:
16062switch (this->args[2].kind()) {
16063case Arg::Tmp:
16064if (!args[1].tmp().isFP())
16065OPGEN_RETURN(false);
16066if (!args[2].tmp().isFP())
16067OPGEN_RETURN(false);
16068OPGEN_RETURN(true);
16069break;
16070break;
16071default:
16072break;
16073}
16074break;
16075default:
16076break;
16077}
16078break;
16079default:
16080break;
16081}
16082break;
16083default:
16084break;
16085}
16086break;
16087case Opcode::BranchAdd32:
16088switch (this->args.size()) {
16089case 4:
16090switch (this->args[0].kind()) {
16091case Arg::ResCond:
16092switch (this->args[1].kind()) {
16093case Arg::Tmp:
16094switch (this->args[2].kind()) {
16095case Arg::Tmp:
16096switch (this->args[3].kind()) {
16097case Arg::Tmp:
16098if (!args[1].tmp().isGP())
16099OPGEN_RETURN(false);
16100if (!args[2].tmp().isGP())
16101OPGEN_RETURN(false);
16102if (!args[3].tmp().isGP())
16103OPGEN_RETURN(false);
16104OPGEN_RETURN(true);
16105break;
16106break;
16107default:
16108break;
16109}
16110break;
16111case Arg::Addr:
16112case Arg::Stack:
16113case Arg::CallArg:
16114switch (this->args[3].kind()) {
16115case Arg::Tmp:
16116#if CPU(X86) || CPU(X86_64)
16117if (!args[1].tmp().isGP())
16118OPGEN_RETURN(false);
16119if (!Arg::isValidAddrForm(args[2].offset()))
16120OPGEN_RETURN(false);
16121if (!args[3].tmp().isGP())
16122OPGEN_RETURN(false);
16123OPGEN_RETURN(true);
16124#endif
16125break;
16126break;
16127default:
16128break;
16129}
16130break;
16131default:
16132break;
16133}
16134break;
16135case Arg::Addr:
16136case Arg::Stack:
16137case Arg::CallArg:
16138switch (this->args[2].kind()) {
16139case Arg::Tmp:
16140switch (this->args[3].kind()) {
16141case Arg::Tmp:
16142#if CPU(X86) || CPU(X86_64)
16143if (!Arg::isValidAddrForm(args[1].offset()))
16144OPGEN_RETURN(false);
16145if (!args[2].tmp().isGP())
16146OPGEN_RETURN(false);
16147if (!args[3].tmp().isGP())
16148OPGEN_RETURN(false);
16149OPGEN_RETURN(true);
16150#endif
16151break;
16152break;
16153default:
16154break;
16155}
16156break;
16157default:
16158break;
16159}
16160break;
16161default:
16162break;
16163}
16164break;
16165default:
16166break;
16167}
16168break;
16169case 3:
16170switch (this->args[0].kind()) {
16171case Arg::ResCond:
16172switch (this->args[1].kind()) {
16173case Arg::Tmp:
16174switch (this->args[2].kind()) {
16175case Arg::Tmp:
16176if (!args[1].tmp().isGP())
16177OPGEN_RETURN(false);
16178if (!args[2].tmp().isGP())
16179OPGEN_RETURN(false);
16180OPGEN_RETURN(true);
16181break;
16182break;
16183case Arg::Addr:
16184case Arg::Stack:
16185case Arg::CallArg:
16186#if CPU(X86) || CPU(X86_64)
16187if (!args[1].tmp().isGP())
16188OPGEN_RETURN(false);
16189if (!Arg::isValidAddrForm(args[2].offset()))
16190OPGEN_RETURN(false);
16191OPGEN_RETURN(true);
16192#endif
16193break;
16194break;
16195default:
16196break;
16197}
16198break;
16199case Arg::Imm:
16200switch (this->args[2].kind()) {
16201case Arg::Tmp:
16202if (!Arg::isValidImmForm(args[1].value()))
16203OPGEN_RETURN(false);
16204if (!args[2].tmp().isGP())
16205OPGEN_RETURN(false);
16206OPGEN_RETURN(true);
16207break;
16208break;
16209case Arg::Addr:
16210case Arg::Stack:
16211case Arg::CallArg:
16212#if CPU(X86) || CPU(X86_64)
16213if (!Arg::isValidImmForm(args[1].value()))
16214OPGEN_RETURN(false);
16215if (!Arg::isValidAddrForm(args[2].offset()))
16216OPGEN_RETURN(false);
16217OPGEN_RETURN(true);
16218#endif
16219break;
16220break;
16221default:
16222break;
16223}
16224break;
16225case Arg::Addr:
16226case Arg::Stack:
16227case Arg::CallArg:
16228switch (this->args[2].kind()) {
16229case Arg::Tmp:
16230#if CPU(X86) || CPU(X86_64)
16231if (!Arg::isValidAddrForm(args[1].offset()))
16232OPGEN_RETURN(false);
16233if (!args[2].tmp().isGP())
16234OPGEN_RETURN(false);
16235OPGEN_RETURN(true);
16236#endif
16237break;
16238break;
16239default:
16240break;
16241}
16242break;
16243default:
16244break;
16245}
16246break;
16247default:
16248break;
16249}
16250break;
16251default:
16252break;
16253}
16254break;
16255case Opcode::BranchAdd64:
16256switch (this->args.size()) {
16257case 4:
16258switch (this->args[0].kind()) {
16259case Arg::ResCond:
16260switch (this->args[1].kind()) {
16261case Arg::Tmp:
16262switch (this->args[2].kind()) {
16263case Arg::Tmp:
16264switch (this->args[3].kind()) {
16265case Arg::Tmp:
16266if (!args[1].tmp().isGP())
16267OPGEN_RETURN(false);
16268if (!args[2].tmp().isGP())
16269OPGEN_RETURN(false);
16270if (!args[3].tmp().isGP())
16271OPGEN_RETURN(false);
16272OPGEN_RETURN(true);
16273break;
16274break;
16275default:
16276break;
16277}
16278break;
16279case Arg::Addr:
16280case Arg::Stack:
16281case Arg::CallArg:
16282switch (this->args[3].kind()) {
16283case Arg::Tmp:
16284#if CPU(X86) || CPU(X86_64)
16285if (!args[1].tmp().isGP())
16286OPGEN_RETURN(false);
16287if (!Arg::isValidAddrForm(args[2].offset()))
16288OPGEN_RETURN(false);
16289if (!args[3].tmp().isGP())
16290OPGEN_RETURN(false);
16291OPGEN_RETURN(true);
16292#endif
16293break;
16294break;
16295default:
16296break;
16297}
16298break;
16299default:
16300break;
16301}
16302break;
16303case Arg::Addr:
16304case Arg::Stack:
16305case Arg::CallArg:
16306switch (this->args[2].kind()) {
16307case Arg::Tmp:
16308switch (this->args[3].kind()) {
16309case Arg::Tmp:
16310#if CPU(X86) || CPU(X86_64)
16311if (!Arg::isValidAddrForm(args[1].offset()))
16312OPGEN_RETURN(false);
16313if (!args[2].tmp().isGP())
16314OPGEN_RETURN(false);
16315if (!args[3].tmp().isGP())
16316OPGEN_RETURN(false);
16317OPGEN_RETURN(true);
16318#endif
16319break;
16320break;
16321default:
16322break;
16323}
16324break;
16325default:
16326break;
16327}
16328break;
16329default:
16330break;
16331}
16332break;
16333default:
16334break;
16335}
16336break;
16337case 3:
16338switch (this->args[0].kind()) {
16339case Arg::ResCond:
16340switch (this->args[1].kind()) {
16341case Arg::Imm:
16342switch (this->args[2].kind()) {
16343case Arg::Tmp:
16344#if CPU(X86_64) || CPU(ARM64)
16345if (!Arg::isValidImmForm(args[1].value()))
16346OPGEN_RETURN(false);
16347if (!args[2].tmp().isGP())
16348OPGEN_RETURN(false);
16349OPGEN_RETURN(true);
16350#endif
16351break;
16352break;
16353default:
16354break;
16355}
16356break;
16357case Arg::Tmp:
16358switch (this->args[2].kind()) {
16359case Arg::Tmp:
16360#if CPU(X86_64) || CPU(ARM64)
16361if (!args[1].tmp().isGP())
16362OPGEN_RETURN(false);
16363if (!args[2].tmp().isGP())
16364OPGEN_RETURN(false);
16365OPGEN_RETURN(true);
16366#endif
16367break;
16368break;
16369default:
16370break;
16371}
16372break;
16373case Arg::Addr:
16374case Arg::Stack:
16375case Arg::CallArg:
16376switch (this->args[2].kind()) {
16377case Arg::Tmp:
16378#if CPU(X86_64)
16379if (!Arg::isValidAddrForm(args[1].offset()))
16380OPGEN_RETURN(false);
16381if (!args[2].tmp().isGP())
16382OPGEN_RETURN(false);
16383OPGEN_RETURN(true);
16384#endif
16385break;
16386break;
16387default:
16388break;
16389}
16390break;
16391default:
16392break;
16393}
16394break;
16395default:
16396break;
16397}
16398break;
16399default:
16400break;
16401}
16402break;
16403case Opcode::BranchMul32:
16404switch (this->args.size()) {
16405case 3:
16406switch (this->args[0].kind()) {
16407case Arg::ResCond:
16408switch (this->args[1].kind()) {
16409case Arg::Tmp:
16410switch (this->args[2].kind()) {
16411case Arg::Tmp:
16412#if CPU(X86) || CPU(X86_64)
16413if (!args[1].tmp().isGP())
16414OPGEN_RETURN(false);
16415if (!args[2].tmp().isGP())
16416OPGEN_RETURN(false);
16417OPGEN_RETURN(true);
16418#endif
16419break;
16420break;
16421default:
16422break;
16423}
16424break;
16425case Arg::Addr:
16426case Arg::Stack:
16427case Arg::CallArg:
16428switch (this->args[2].kind()) {
16429case Arg::Tmp:
16430#if CPU(X86) || CPU(X86_64)
16431if (!Arg::isValidAddrForm(args[1].offset()))
16432OPGEN_RETURN(false);
16433if (!args[2].tmp().isGP())
16434OPGEN_RETURN(false);
16435OPGEN_RETURN(true);
16436#endif
16437break;
16438break;
16439default:
16440break;
16441}
16442break;
16443default:
16444break;
16445}
16446break;
16447default:
16448break;
16449}
16450break;
16451case 4:
16452switch (this->args[0].kind()) {
16453case Arg::ResCond:
16454switch (this->args[1].kind()) {
16455case Arg::Tmp:
16456switch (this->args[2].kind()) {
16457case Arg::Imm:
16458switch (this->args[3].kind()) {
16459case Arg::Tmp:
16460#if CPU(X86) || CPU(X86_64)
16461if (!args[1].tmp().isGP())
16462OPGEN_RETURN(false);
16463if (!Arg::isValidImmForm(args[2].value()))
16464OPGEN_RETURN(false);
16465if (!args[3].tmp().isGP())
16466OPGEN_RETURN(false);
16467OPGEN_RETURN(true);
16468#endif
16469break;
16470break;
16471default:
16472break;
16473}
16474break;
16475default:
16476break;
16477}
16478break;
16479default:
16480break;
16481}
16482break;
16483default:
16484break;
16485}
16486break;
16487case 6:
16488switch (this->args[0].kind()) {
16489case Arg::ResCond:
16490switch (this->args[1].kind()) {
16491case Arg::Tmp:
16492switch (this->args[2].kind()) {
16493case Arg::Tmp:
16494switch (this->args[3].kind()) {
16495case Arg::Tmp:
16496switch (this->args[4].kind()) {
16497case Arg::Tmp:
16498switch (this->args[5].kind()) {
16499case Arg::Tmp:
16500#if CPU(ARM64)
16501if (!args[1].tmp().isGP())
16502OPGEN_RETURN(false);
16503if (!args[2].tmp().isGP())
16504OPGEN_RETURN(false);
16505if (!args[3].tmp().isGP())
16506OPGEN_RETURN(false);
16507if (!args[4].tmp().isGP())
16508OPGEN_RETURN(false);
16509if (!args[5].tmp().isGP())
16510OPGEN_RETURN(false);
16511OPGEN_RETURN(true);
16512#endif
16513break;
16514break;
16515default:
16516break;
16517}
16518break;
16519default:
16520break;
16521}
16522break;
16523default:
16524break;
16525}
16526break;
16527default:
16528break;
16529}
16530break;
16531default:
16532break;
16533}
16534break;
16535default:
16536break;
16537}
16538break;
16539default:
16540break;
16541}
16542break;
16543case Opcode::BranchMul64:
16544switch (this->args.size()) {
16545case 3:
16546switch (this->args[0].kind()) {
16547case Arg::ResCond:
16548switch (this->args[1].kind()) {
16549case Arg::Tmp:
16550switch (this->args[2].kind()) {
16551case Arg::Tmp:
16552#if CPU(X86_64)
16553if (!args[1].tmp().isGP())
16554OPGEN_RETURN(false);
16555if (!args[2].tmp().isGP())
16556OPGEN_RETURN(false);
16557OPGEN_RETURN(true);
16558#endif
16559break;
16560break;
16561default:
16562break;
16563}
16564break;
16565default:
16566break;
16567}
16568break;
16569default:
16570break;
16571}
16572break;
16573case 6:
16574switch (this->args[0].kind()) {
16575case Arg::ResCond:
16576switch (this->args[1].kind()) {
16577case Arg::Tmp:
16578switch (this->args[2].kind()) {
16579case Arg::Tmp:
16580switch (this->args[3].kind()) {
16581case Arg::Tmp:
16582switch (this->args[4].kind()) {
16583case Arg::Tmp:
16584switch (this->args[5].kind()) {
16585case Arg::Tmp:
16586#if CPU(ARM64)
16587if (!args[1].tmp().isGP())
16588OPGEN_RETURN(false);
16589if (!args[2].tmp().isGP())
16590OPGEN_RETURN(false);
16591if (!args[3].tmp().isGP())
16592OPGEN_RETURN(false);
16593if (!args[4].tmp().isGP())
16594OPGEN_RETURN(false);
16595if (!args[5].tmp().isGP())
16596OPGEN_RETURN(false);
16597OPGEN_RETURN(true);
16598#endif
16599break;
16600break;
16601default:
16602break;
16603}
16604break;
16605default:
16606break;
16607}
16608break;
16609default:
16610break;
16611}
16612break;
16613default:
16614break;
16615}
16616break;
16617default:
16618break;
16619}
16620break;
16621default:
16622break;
16623}
16624break;
16625default:
16626break;
16627}
16628break;
16629case Opcode::BranchSub32:
16630switch (this->args.size()) {
16631case 3:
16632switch (this->args[0].kind()) {
16633case Arg::ResCond:
16634switch (this->args[1].kind()) {
16635case Arg::Tmp:
16636switch (this->args[2].kind()) {
16637case Arg::Tmp:
16638if (!args[1].tmp().isGP())
16639OPGEN_RETURN(false);
16640if (!args[2].tmp().isGP())
16641OPGEN_RETURN(false);
16642OPGEN_RETURN(true);
16643break;
16644break;
16645case Arg::Addr:
16646case Arg::Stack:
16647case Arg::CallArg:
16648#if CPU(X86) || CPU(X86_64)
16649if (!args[1].tmp().isGP())
16650OPGEN_RETURN(false);
16651if (!Arg::isValidAddrForm(args[2].offset()))
16652OPGEN_RETURN(false);
16653OPGEN_RETURN(true);
16654#endif
16655break;
16656break;
16657default:
16658break;
16659}
16660break;
16661case Arg::Imm:
16662switch (this->args[2].kind()) {
16663case Arg::Tmp:
16664if (!Arg::isValidImmForm(args[1].value()))
16665OPGEN_RETURN(false);
16666if (!args[2].tmp().isGP())
16667OPGEN_RETURN(false);
16668OPGEN_RETURN(true);
16669break;
16670break;
16671case Arg::Addr:
16672case Arg::Stack:
16673case Arg::CallArg:
16674#if CPU(X86) || CPU(X86_64)
16675if (!Arg::isValidImmForm(args[1].value()))
16676OPGEN_RETURN(false);
16677if (!Arg::isValidAddrForm(args[2].offset()))
16678OPGEN_RETURN(false);
16679OPGEN_RETURN(true);
16680#endif
16681break;
16682break;
16683default:
16684break;
16685}
16686break;
16687case Arg::Addr:
16688case Arg::Stack:
16689case Arg::CallArg:
16690switch (this->args[2].kind()) {
16691case Arg::Tmp:
16692#if CPU(X86) || CPU(X86_64)
16693if (!Arg::isValidAddrForm(args[1].offset()))
16694OPGEN_RETURN(false);
16695if (!args[2].tmp().isGP())
16696OPGEN_RETURN(false);
16697OPGEN_RETURN(true);
16698#endif
16699break;
16700break;
16701default:
16702break;
16703}
16704break;
16705default:
16706break;
16707}
16708break;
16709default:
16710break;
16711}
16712break;
16713default:
16714break;
16715}
16716break;
16717case Opcode::BranchSub64:
16718switch (this->args.size()) {
16719case 3:
16720switch (this->args[0].kind()) {
16721case Arg::ResCond:
16722switch (this->args[1].kind()) {
16723case Arg::Imm:
16724switch (this->args[2].kind()) {
16725case Arg::Tmp:
16726#if CPU(X86_64) || CPU(ARM64)
16727if (!Arg::isValidImmForm(args[1].value()))
16728OPGEN_RETURN(false);
16729if (!args[2].tmp().isGP())
16730OPGEN_RETURN(false);
16731OPGEN_RETURN(true);
16732#endif
16733break;
16734break;
16735default:
16736break;
16737}
16738break;
16739case Arg::Tmp:
16740switch (this->args[2].kind()) {
16741case Arg::Tmp:
16742#if CPU(X86_64) || CPU(ARM64)
16743if (!args[1].tmp().isGP())
16744OPGEN_RETURN(false);
16745if (!args[2].tmp().isGP())
16746OPGEN_RETURN(false);
16747OPGEN_RETURN(true);
16748#endif
16749break;
16750break;
16751default:
16752break;
16753}
16754break;
16755default:
16756break;
16757}
16758break;
16759default:
16760break;
16761}
16762break;
16763default:
16764break;
16765}
16766break;
16767case Opcode::BranchNeg32:
16768switch (this->args.size()) {
16769case 2:
16770switch (this->args[0].kind()) {
16771case Arg::ResCond:
16772switch (this->args[1].kind()) {
16773case Arg::Tmp:
16774if (!args[1].tmp().isGP())
16775OPGEN_RETURN(false);
16776OPGEN_RETURN(true);
16777break;
16778break;
16779default:
16780break;
16781}
16782break;
16783default:
16784break;
16785}
16786break;
16787default:
16788break;
16789}
16790break;
16791case Opcode::BranchNeg64:
16792switch (this->args.size()) {
16793case 2:
16794switch (this->args[0].kind()) {
16795case Arg::ResCond:
16796switch (this->args[1].kind()) {
16797case Arg::Tmp:
16798#if CPU(X86_64) || CPU(ARM64)
16799if (!args[1].tmp().isGP())
16800OPGEN_RETURN(false);
16801OPGEN_RETURN(true);
16802#endif
16803break;
16804break;
16805default:
16806break;
16807}
16808break;
16809default:
16810break;
16811}
16812break;
16813default:
16814break;
16815}
16816break;
16817case Opcode::MoveConditionally32:
16818switch (this->args.size()) {
16819case 5:
16820switch (this->args[0].kind()) {
16821case Arg::RelCond:
16822switch (this->args[1].kind()) {
16823case Arg::Tmp:
16824switch (this->args[2].kind()) {
16825case Arg::Tmp:
16826switch (this->args[3].kind()) {
16827case Arg::Tmp:
16828switch (this->args[4].kind()) {
16829case Arg::Tmp:
16830if (!args[1].tmp().isGP())
16831OPGEN_RETURN(false);
16832if (!args[2].tmp().isGP())
16833OPGEN_RETURN(false);
16834if (!args[3].tmp().isGP())
16835OPGEN_RETURN(false);
16836if (!args[4].tmp().isGP())
16837OPGEN_RETURN(false);
16838OPGEN_RETURN(true);
16839break;
16840break;
16841default:
16842break;
16843}
16844break;
16845default:
16846break;
16847}
16848break;
16849default:
16850break;
16851}
16852break;
16853default:
16854break;
16855}
16856break;
16857default:
16858break;
16859}
16860break;
16861case 6:
16862switch (this->args[0].kind()) {
16863case Arg::RelCond:
16864switch (this->args[1].kind()) {
16865case Arg::Tmp:
16866switch (this->args[2].kind()) {
16867case Arg::Tmp:
16868switch (this->args[3].kind()) {
16869case Arg::Tmp:
16870switch (this->args[4].kind()) {
16871case Arg::Tmp:
16872switch (this->args[5].kind()) {
16873case Arg::Tmp:
16874if (!args[1].tmp().isGP())
16875OPGEN_RETURN(false);
16876if (!args[2].tmp().isGP())
16877OPGEN_RETURN(false);
16878if (!args[3].tmp().isGP())
16879OPGEN_RETURN(false);
16880if (!args[4].tmp().isGP())
16881OPGEN_RETURN(false);
16882if (!args[5].tmp().isGP())
16883OPGEN_RETURN(false);
16884OPGEN_RETURN(true);
16885break;
16886break;
16887default:
16888break;
16889}
16890break;
16891default:
16892break;
16893}
16894break;
16895default:
16896break;
16897}
16898break;
16899case Arg::Imm:
16900switch (this->args[3].kind()) {
16901case Arg::Tmp:
16902switch (this->args[4].kind()) {
16903case Arg::Tmp:
16904switch (this->args[5].kind()) {
16905case Arg::Tmp:
16906if (!args[1].tmp().isGP())
16907OPGEN_RETURN(false);
16908if (!Arg::isValidImmForm(args[2].value()))
16909OPGEN_RETURN(false);
16910if (!args[3].tmp().isGP())
16911OPGEN_RETURN(false);
16912if (!args[4].tmp().isGP())
16913OPGEN_RETURN(false);
16914if (!args[5].tmp().isGP())
16915OPGEN_RETURN(false);
16916OPGEN_RETURN(true);
16917break;
16918break;
16919default:
16920break;
16921}
16922break;
16923default:
16924break;
16925}
16926break;
16927default:
16928break;
16929}
16930break;
16931default:
16932break;
16933}
16934break;
16935default:
16936break;
16937}
16938break;
16939default:
16940break;
16941}
16942break;
16943default:
16944break;
16945}
16946break;
16947case Opcode::MoveConditionally64:
16948switch (this->args.size()) {
16949case 5:
16950switch (this->args[0].kind()) {
16951case Arg::RelCond:
16952switch (this->args[1].kind()) {
16953case Arg::Tmp:
16954switch (this->args[2].kind()) {
16955case Arg::Tmp:
16956switch (this->args[3].kind()) {
16957case Arg::Tmp:
16958switch (this->args[4].kind()) {
16959case Arg::Tmp:
16960#if CPU(X86_64) || CPU(ARM64)
16961if (!args[1].tmp().isGP())
16962OPGEN_RETURN(false);
16963if (!args[2].tmp().isGP())
16964OPGEN_RETURN(false);
16965if (!args[3].tmp().isGP())
16966OPGEN_RETURN(false);
16967if (!args[4].tmp().isGP())
16968OPGEN_RETURN(false);
16969OPGEN_RETURN(true);
16970#endif
16971break;
16972break;
16973default:
16974break;
16975}
16976break;
16977default:
16978break;
16979}
16980break;
16981default:
16982break;
16983}
16984break;
16985default:
16986break;
16987}
16988break;
16989default:
16990break;
16991}
16992break;
16993case 6:
16994switch (this->args[0].kind()) {
16995case Arg::RelCond:
16996switch (this->args[1].kind()) {
16997case Arg::Tmp:
16998switch (this->args[2].kind()) {
16999case Arg::Tmp:
17000switch (this->args[3].kind()) {
17001case Arg::Tmp:
17002switch (this->args[4].kind()) {
17003case Arg::Tmp:
17004switch (this->args[5].kind()) {
17005case Arg::Tmp:
17006#if CPU(X86_64) || CPU(ARM64)
17007if (!args[1].tmp().isGP())
17008OPGEN_RETURN(false);
17009if (!args[2].tmp().isGP())
17010OPGEN_RETURN(false);
17011if (!args[3].tmp().isGP())
17012OPGEN_RETURN(false);
17013if (!args[4].tmp().isGP())
17014OPGEN_RETURN(false);
17015if (!args[5].tmp().isGP())
17016OPGEN_RETURN(false);
17017OPGEN_RETURN(true);
17018#endif
17019break;
17020break;
17021default:
17022break;
17023}
17024break;
17025default:
17026break;
17027}
17028break;
17029default:
17030break;
17031}
17032break;
17033case Arg::Imm:
17034switch (this->args[3].kind()) {
17035case Arg::Tmp:
17036switch (this->args[4].kind()) {
17037case Arg::Tmp:
17038switch (this->args[5].kind()) {
17039case Arg::Tmp:
17040#if CPU(X86_64) || CPU(ARM64)
17041if (!args[1].tmp().isGP())
17042OPGEN_RETURN(false);
17043if (!Arg::isValidImmForm(args[2].value()))
17044OPGEN_RETURN(false);
17045if (!args[3].tmp().isGP())
17046OPGEN_RETURN(false);
17047if (!args[4].tmp().isGP())
17048OPGEN_RETURN(false);
17049if (!args[5].tmp().isGP())
17050OPGEN_RETURN(false);
17051OPGEN_RETURN(true);
17052#endif
17053break;
17054break;
17055default:
17056break;
17057}
17058break;
17059default:
17060break;
17061}
17062break;
17063default:
17064break;
17065}
17066break;
17067default:
17068break;
17069}
17070break;
17071default:
17072break;
17073}
17074break;
17075default:
17076break;
17077}
17078break;
17079default:
17080break;
17081}
17082break;
17083case Opcode::MoveConditionallyTest32:
17084switch (this->args.size()) {
17085case 5:
17086switch (this->args[0].kind()) {
17087case Arg::ResCond:
17088switch (this->args[1].kind()) {
17089case Arg::Tmp:
17090switch (this->args[2].kind()) {
17091case Arg::Tmp:
17092switch (this->args[3].kind()) {
17093case Arg::Tmp:
17094switch (this->args[4].kind()) {
17095case Arg::Tmp:
17096if (!args[1].tmp().isGP())
17097OPGEN_RETURN(false);
17098if (!args[2].tmp().isGP())
17099OPGEN_RETURN(false);
17100if (!args[3].tmp().isGP())
17101OPGEN_RETURN(false);
17102if (!args[4].tmp().isGP())
17103OPGEN_RETURN(false);
17104OPGEN_RETURN(true);
17105break;
17106break;
17107default:
17108break;
17109}
17110break;
17111default:
17112break;
17113}
17114break;
17115case Arg::Imm:
17116switch (this->args[3].kind()) {
17117case Arg::Tmp:
17118switch (this->args[4].kind()) {
17119case Arg::Tmp:
17120#if CPU(X86) || CPU(X86_64)
17121if (!args[1].tmp().isGP())
17122OPGEN_RETURN(false);
17123if (!Arg::isValidImmForm(args[2].value()))
17124OPGEN_RETURN(false);
17125if (!args[3].tmp().isGP())
17126OPGEN_RETURN(false);
17127if (!args[4].tmp().isGP())
17128OPGEN_RETURN(false);
17129OPGEN_RETURN(true);
17130#endif
17131break;
17132break;
17133default:
17134break;
17135}
17136break;
17137default:
17138break;
17139}
17140break;
17141default:
17142break;
17143}
17144break;
17145default:
17146break;
17147}
17148break;
17149default:
17150break;
17151}
17152break;
17153case 6:
17154switch (this->args[0].kind()) {
17155case Arg::ResCond:
17156switch (this->args[1].kind()) {
17157case Arg::Tmp:
17158switch (this->args[2].kind()) {
17159case Arg::Tmp:
17160switch (this->args[3].kind()) {
17161case Arg::Tmp:
17162switch (this->args[4].kind()) {
17163case Arg::Tmp:
17164switch (this->args[5].kind()) {
17165case Arg::Tmp:
17166if (!args[1].tmp().isGP())
17167OPGEN_RETURN(false);
17168if (!args[2].tmp().isGP())
17169OPGEN_RETURN(false);
17170if (!args[3].tmp().isGP())
17171OPGEN_RETURN(false);
17172if (!args[4].tmp().isGP())
17173OPGEN_RETURN(false);
17174if (!args[5].tmp().isGP())
17175OPGEN_RETURN(false);
17176OPGEN_RETURN(true);
17177break;
17178break;
17179default:
17180break;
17181}
17182break;
17183default:
17184break;
17185}
17186break;
17187default:
17188break;
17189}
17190break;
17191case Arg::BitImm:
17192switch (this->args[3].kind()) {
17193case Arg::Tmp:
17194switch (this->args[4].kind()) {
17195case Arg::Tmp:
17196switch (this->args[5].kind()) {
17197case Arg::Tmp:
17198if (!args[1].tmp().isGP())
17199OPGEN_RETURN(false);
17200if (!Arg::isValidBitImmForm(args[2].value()))
17201OPGEN_RETURN(false);
17202if (!args[3].tmp().isGP())
17203OPGEN_RETURN(false);
17204if (!args[4].tmp().isGP())
17205OPGEN_RETURN(false);
17206if (!args[5].tmp().isGP())
17207OPGEN_RETURN(false);
17208OPGEN_RETURN(true);
17209break;
17210break;
17211default:
17212break;
17213}
17214break;
17215default:
17216break;
17217}
17218break;
17219default:
17220break;
17221}
17222break;
17223default:
17224break;
17225}
17226break;
17227default:
17228break;
17229}
17230break;
17231default:
17232break;
17233}
17234break;
17235default:
17236break;
17237}
17238break;
17239case Opcode::MoveConditionallyTest64:
17240switch (this->args.size()) {
17241case 5:
17242switch (this->args[0].kind()) {
17243case Arg::ResCond:
17244switch (this->args[1].kind()) {
17245case Arg::Tmp:
17246switch (this->args[2].kind()) {
17247case Arg::Tmp:
17248switch (this->args[3].kind()) {
17249case Arg::Tmp:
17250switch (this->args[4].kind()) {
17251case Arg::Tmp:
17252#if CPU(X86_64) || CPU(ARM64)
17253if (!args[1].tmp().isGP())
17254OPGEN_RETURN(false);
17255if (!args[2].tmp().isGP())
17256OPGEN_RETURN(false);
17257if (!args[3].tmp().isGP())
17258OPGEN_RETURN(false);
17259if (!args[4].tmp().isGP())
17260OPGEN_RETURN(false);
17261OPGEN_RETURN(true);
17262#endif
17263break;
17264break;
17265default:
17266break;
17267}
17268break;
17269default:
17270break;
17271}
17272break;
17273case Arg::Imm:
17274switch (this->args[3].kind()) {
17275case Arg::Tmp:
17276switch (this->args[4].kind()) {
17277case Arg::Tmp:
17278#if CPU(X86_64)
17279if (!args[1].tmp().isGP())
17280OPGEN_RETURN(false);
17281if (!Arg::isValidImmForm(args[2].value()))
17282OPGEN_RETURN(false);
17283if (!args[3].tmp().isGP())
17284OPGEN_RETURN(false);
17285if (!args[4].tmp().isGP())
17286OPGEN_RETURN(false);
17287OPGEN_RETURN(true);
17288#endif
17289break;
17290break;
17291default:
17292break;
17293}
17294break;
17295default:
17296break;
17297}
17298break;
17299default:
17300break;
17301}
17302break;
17303default:
17304break;
17305}
17306break;
17307default:
17308break;
17309}
17310break;
17311case 6:
17312switch (this->args[0].kind()) {
17313case Arg::ResCond:
17314switch (this->args[1].kind()) {
17315case Arg::Tmp:
17316switch (this->args[2].kind()) {
17317case Arg::Tmp:
17318switch (this->args[3].kind()) {
17319case Arg::Tmp:
17320switch (this->args[4].kind()) {
17321case Arg::Tmp:
17322switch (this->args[5].kind()) {
17323case Arg::Tmp:
17324#if CPU(X86_64) || CPU(ARM64)
17325if (!args[1].tmp().isGP())
17326OPGEN_RETURN(false);
17327if (!args[2].tmp().isGP())
17328OPGEN_RETURN(false);
17329if (!args[3].tmp().isGP())
17330OPGEN_RETURN(false);
17331if (!args[4].tmp().isGP())
17332OPGEN_RETURN(false);
17333if (!args[5].tmp().isGP())
17334OPGEN_RETURN(false);
17335OPGEN_RETURN(true);
17336#endif
17337break;
17338break;
17339default:
17340break;
17341}
17342break;
17343default:
17344break;
17345}
17346break;
17347default:
17348break;
17349}
17350break;
17351case Arg::Imm:
17352switch (this->args[3].kind()) {
17353case Arg::Tmp:
17354switch (this->args[4].kind()) {
17355case Arg::Tmp:
17356switch (this->args[5].kind()) {
17357case Arg::Tmp:
17358#if CPU(X86_64)
17359if (!args[1].tmp().isGP())
17360OPGEN_RETURN(false);
17361if (!Arg::isValidImmForm(args[2].value()))
17362OPGEN_RETURN(false);
17363if (!args[3].tmp().isGP())
17364OPGEN_RETURN(false);
17365if (!args[4].tmp().isGP())
17366OPGEN_RETURN(false);
17367if (!args[5].tmp().isGP())
17368OPGEN_RETURN(false);
17369OPGEN_RETURN(true);
17370#endif
17371break;
17372break;
17373default:
17374break;
17375}
17376break;
17377default:
17378break;
17379}
17380break;
17381default:
17382break;
17383}
17384break;
17385default:
17386break;
17387}
17388break;
17389default:
17390break;
17391}
17392break;
17393default:
17394break;
17395}
17396break;
17397default:
17398break;
17399}
17400break;
17401case Opcode::MoveConditionallyDouble:
17402switch (this->args.size()) {
17403case 6:
17404switch (this->args[0].kind()) {
17405case Arg::DoubleCond:
17406switch (this->args[1].kind()) {
17407case Arg::Tmp:
17408switch (this->args[2].kind()) {
17409case Arg::Tmp:
17410switch (this->args[3].kind()) {
17411case Arg::Tmp:
17412switch (this->args[4].kind()) {
17413case Arg::Tmp:
17414switch (this->args[5].kind()) {
17415case Arg::Tmp:
17416if (!args[1].tmp().isFP())
17417OPGEN_RETURN(false);
17418if (!args[2].tmp().isFP())
17419OPGEN_RETURN(false);
17420if (!args[3].tmp().isGP())
17421OPGEN_RETURN(false);
17422if (!args[4].tmp().isGP())
17423OPGEN_RETURN(false);
17424if (!args[5].tmp().isGP())
17425OPGEN_RETURN(false);
17426OPGEN_RETURN(true);
17427break;
17428break;
17429default:
17430break;
17431}
17432break;
17433default:
17434break;
17435}
17436break;
17437default:
17438break;
17439}
17440break;
17441default:
17442break;
17443}
17444break;
17445default:
17446break;
17447}
17448break;
17449default:
17450break;
17451}
17452break;
17453case 5:
17454switch (this->args[0].kind()) {
17455case Arg::DoubleCond:
17456switch (this->args[1].kind()) {
17457case Arg::Tmp:
17458switch (this->args[2].kind()) {
17459case Arg::Tmp:
17460switch (this->args[3].kind()) {
17461case Arg::Tmp:
17462switch (this->args[4].kind()) {
17463case Arg::Tmp:
17464if (!args[1].tmp().isFP())
17465OPGEN_RETURN(false);
17466if (!args[2].tmp().isFP())
17467OPGEN_RETURN(false);
17468if (!args[3].tmp().isGP())
17469OPGEN_RETURN(false);
17470if (!args[4].tmp().isGP())
17471OPGEN_RETURN(false);
17472OPGEN_RETURN(true);
17473break;
17474break;
17475default:
17476break;
17477}
17478break;
17479default:
17480break;
17481}
17482break;
17483default:
17484break;
17485}
17486break;
17487default:
17488break;
17489}
17490break;
17491default:
17492break;
17493}
17494break;
17495default:
17496break;
17497}
17498break;
17499case Opcode::MoveConditionallyFloat:
17500switch (this->args.size()) {
17501case 6:
17502switch (this->args[0].kind()) {
17503case Arg::DoubleCond:
17504switch (this->args[1].kind()) {
17505case Arg::Tmp:
17506switch (this->args[2].kind()) {
17507case Arg::Tmp:
17508switch (this->args[3].kind()) {
17509case Arg::Tmp:
17510switch (this->args[4].kind()) {
17511case Arg::Tmp:
17512switch (this->args[5].kind()) {
17513case Arg::Tmp:
17514if (!args[1].tmp().isFP())
17515OPGEN_RETURN(false);
17516if (!args[2].tmp().isFP())
17517OPGEN_RETURN(false);
17518if (!args[3].tmp().isGP())
17519OPGEN_RETURN(false);
17520if (!args[4].tmp().isGP())
17521OPGEN_RETURN(false);
17522if (!args[5].tmp().isGP())
17523OPGEN_RETURN(false);
17524OPGEN_RETURN(true);
17525break;
17526break;
17527default:
17528break;
17529}
17530break;
17531default:
17532break;
17533}
17534break;
17535default:
17536break;
17537}
17538break;
17539default:
17540break;
17541}
17542break;
17543default:
17544break;
17545}
17546break;
17547default:
17548break;
17549}
17550break;
17551case 5:
17552switch (this->args[0].kind()) {
17553case Arg::DoubleCond:
17554switch (this->args[1].kind()) {
17555case Arg::Tmp:
17556switch (this->args[2].kind()) {
17557case Arg::Tmp:
17558switch (this->args[3].kind()) {
17559case Arg::Tmp:
17560switch (this->args[4].kind()) {
17561case Arg::Tmp:
17562if (!args[1].tmp().isFP())
17563OPGEN_RETURN(false);
17564if (!args[2].tmp().isFP())
17565OPGEN_RETURN(false);
17566if (!args[3].tmp().isGP())
17567OPGEN_RETURN(false);
17568if (!args[4].tmp().isGP())
17569OPGEN_RETURN(false);
17570OPGEN_RETURN(true);
17571break;
17572break;
17573default:
17574break;
17575}
17576break;
17577default:
17578break;
17579}
17580break;
17581default:
17582break;
17583}
17584break;
17585default:
17586break;
17587}
17588break;
17589default:
17590break;
17591}
17592break;
17593default:
17594break;
17595}
17596break;
17597case Opcode::MoveDoubleConditionally32:
17598switch (this->args.size()) {
17599case 6:
17600switch (this->args[0].kind()) {
17601case Arg::RelCond:
17602switch (this->args[1].kind()) {
17603case Arg::Tmp:
17604switch (this->args[2].kind()) {
17605case Arg::Tmp:
17606switch (this->args[3].kind()) {
17607case Arg::Tmp:
17608switch (this->args[4].kind()) {
17609case Arg::Tmp:
17610switch (this->args[5].kind()) {
17611case Arg::Tmp:
17612if (!args[1].tmp().isGP())
17613OPGEN_RETURN(false);
17614if (!args[2].tmp().isGP())
17615OPGEN_RETURN(false);
17616if (!args[3].tmp().isFP())
17617OPGEN_RETURN(false);
17618if (!args[4].tmp().isFP())
17619OPGEN_RETURN(false);
17620if (!args[5].tmp().isFP())
17621OPGEN_RETURN(false);
17622OPGEN_RETURN(true);
17623break;
17624break;
17625default:
17626break;
17627}
17628break;
17629default:
17630break;
17631}
17632break;
17633default:
17634break;
17635}
17636break;
17637case Arg::Imm:
17638switch (this->args[3].kind()) {
17639case Arg::Tmp:
17640switch (this->args[4].kind()) {
17641case Arg::Tmp:
17642switch (this->args[5].kind()) {
17643case Arg::Tmp:
17644if (!args[1].tmp().isGP())
17645OPGEN_RETURN(false);
17646if (!Arg::isValidImmForm(args[2].value()))
17647OPGEN_RETURN(false);
17648if (!args[3].tmp().isFP())
17649OPGEN_RETURN(false);
17650if (!args[4].tmp().isFP())
17651OPGEN_RETURN(false);
17652if (!args[5].tmp().isFP())
17653OPGEN_RETURN(false);
17654OPGEN_RETURN(true);
17655break;
17656break;
17657default:
17658break;
17659}
17660break;
17661default:
17662break;
17663}
17664break;
17665default:
17666break;
17667}
17668break;
17669case Arg::Addr:
17670case Arg::Stack:
17671case Arg::CallArg:
17672switch (this->args[3].kind()) {
17673case Arg::Tmp:
17674switch (this->args[4].kind()) {
17675case Arg::Tmp:
17676switch (this->args[5].kind()) {
17677case Arg::Tmp:
17678#if CPU(X86) || CPU(X86_64)
17679if (!args[1].tmp().isGP())
17680OPGEN_RETURN(false);
17681if (!Arg::isValidAddrForm(args[2].offset()))
17682OPGEN_RETURN(false);
17683if (!args[3].tmp().isFP())
17684OPGEN_RETURN(false);
17685if (!args[4].tmp().isFP())
17686OPGEN_RETURN(false);
17687if (!args[5].tmp().isFP())
17688OPGEN_RETURN(false);
17689OPGEN_RETURN(true);
17690#endif
17691break;
17692break;
17693default:
17694break;
17695}
17696break;
17697default:
17698break;
17699}
17700break;
17701default:
17702break;
17703}
17704break;
17705default:
17706break;
17707}
17708break;
17709case Arg::Addr:
17710case Arg::Stack:
17711case Arg::CallArg:
17712switch (this->args[2].kind()) {
17713case Arg::Imm:
17714switch (this->args[3].kind()) {
17715case Arg::Tmp:
17716switch (this->args[4].kind()) {
17717case Arg::Tmp:
17718switch (this->args[5].kind()) {
17719case Arg::Tmp:
17720#if CPU(X86) || CPU(X86_64)
17721if (!Arg::isValidAddrForm(args[1].offset()))
17722OPGEN_RETURN(false);
17723if (!Arg::isValidImmForm(args[2].value()))
17724OPGEN_RETURN(false);
17725if (!args[3].tmp().isFP())
17726OPGEN_RETURN(false);
17727if (!args[4].tmp().isFP())
17728OPGEN_RETURN(false);
17729if (!args[5].tmp().isFP())
17730OPGEN_RETURN(false);
17731OPGEN_RETURN(true);
17732#endif
17733break;
17734break;
17735default:
17736break;
17737}
17738break;
17739default:
17740break;
17741}
17742break;
17743default:
17744break;
17745}
17746break;
17747case Arg::Tmp:
17748switch (this->args[3].kind()) {
17749case Arg::Tmp:
17750switch (this->args[4].kind()) {
17751case Arg::Tmp:
17752switch (this->args[5].kind()) {
17753case Arg::Tmp:
17754#if CPU(X86) || CPU(X86_64)
17755if (!Arg::isValidAddrForm(args[1].offset()))
17756OPGEN_RETURN(false);
17757if (!args[2].tmp().isGP())
17758OPGEN_RETURN(false);
17759if (!args[3].tmp().isFP())
17760OPGEN_RETURN(false);
17761if (!args[4].tmp().isFP())
17762OPGEN_RETURN(false);
17763if (!args[5].tmp().isFP())
17764OPGEN_RETURN(false);
17765OPGEN_RETURN(true);
17766#endif
17767break;
17768break;
17769default:
17770break;
17771}
17772break;
17773default:
17774break;
17775}
17776break;
17777default:
17778break;
17779}
17780break;
17781default:
17782break;
17783}
17784break;
17785case Arg::Index:
17786switch (this->args[2].kind()) {
17787case Arg::Imm:
17788switch (this->args[3].kind()) {
17789case Arg::Tmp:
17790switch (this->args[4].kind()) {
17791case Arg::Tmp:
17792switch (this->args[5].kind()) {
17793case Arg::Tmp:
17794#if CPU(X86) || CPU(X86_64)
17795if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
17796OPGEN_RETURN(false);
17797if (!Arg::isValidImmForm(args[2].value()))
17798OPGEN_RETURN(false);
17799if (!args[3].tmp().isFP())
17800OPGEN_RETURN(false);
17801if (!args[4].tmp().isFP())
17802OPGEN_RETURN(false);
17803if (!args[5].tmp().isFP())
17804OPGEN_RETURN(false);
17805OPGEN_RETURN(true);
17806#endif
17807break;
17808break;
17809default:
17810break;
17811}
17812break;
17813default:
17814break;
17815}
17816break;
17817default:
17818break;
17819}
17820break;
17821default:
17822break;
17823}
17824break;
17825default:
17826break;
17827}
17828break;
17829default:
17830break;
17831}
17832break;
17833default:
17834break;
17835}
17836break;
17837case Opcode::MoveDoubleConditionally64:
17838switch (this->args.size()) {
17839case 6:
17840switch (this->args[0].kind()) {
17841case Arg::RelCond:
17842switch (this->args[1].kind()) {
17843case Arg::Tmp:
17844switch (this->args[2].kind()) {
17845case Arg::Tmp:
17846switch (this->args[3].kind()) {
17847case Arg::Tmp:
17848switch (this->args[4].kind()) {
17849case Arg::Tmp:
17850switch (this->args[5].kind()) {
17851case Arg::Tmp:
17852#if CPU(X86_64) || CPU(ARM64)
17853if (!args[1].tmp().isGP())
17854OPGEN_RETURN(false);
17855if (!args[2].tmp().isGP())
17856OPGEN_RETURN(false);
17857if (!args[3].tmp().isFP())
17858OPGEN_RETURN(false);
17859if (!args[4].tmp().isFP())
17860OPGEN_RETURN(false);
17861if (!args[5].tmp().isFP())
17862OPGEN_RETURN(false);
17863OPGEN_RETURN(true);
17864#endif
17865break;
17866break;
17867default:
17868break;
17869}
17870break;
17871default:
17872break;
17873}
17874break;
17875default:
17876break;
17877}
17878break;
17879case Arg::Imm:
17880switch (this->args[3].kind()) {
17881case Arg::Tmp:
17882switch (this->args[4].kind()) {
17883case Arg::Tmp:
17884switch (this->args[5].kind()) {
17885case Arg::Tmp:
17886#if CPU(X86_64) || CPU(ARM64)
17887if (!args[1].tmp().isGP())
17888OPGEN_RETURN(false);
17889if (!Arg::isValidImmForm(args[2].value()))
17890OPGEN_RETURN(false);
17891if (!args[3].tmp().isFP())
17892OPGEN_RETURN(false);
17893if (!args[4].tmp().isFP())
17894OPGEN_RETURN(false);
17895if (!args[5].tmp().isFP())
17896OPGEN_RETURN(false);
17897OPGEN_RETURN(true);
17898#endif
17899break;
17900break;
17901default:
17902break;
17903}
17904break;
17905default:
17906break;
17907}
17908break;
17909default:
17910break;
17911}
17912break;
17913case Arg::Addr:
17914case Arg::Stack:
17915case Arg::CallArg:
17916switch (this->args[3].kind()) {
17917case Arg::Tmp:
17918switch (this->args[4].kind()) {
17919case Arg::Tmp:
17920switch (this->args[5].kind()) {
17921case Arg::Tmp:
17922#if CPU(X86_64)
17923if (!args[1].tmp().isGP())
17924OPGEN_RETURN(false);
17925if (!Arg::isValidAddrForm(args[2].offset()))
17926OPGEN_RETURN(false);
17927if (!args[3].tmp().isFP())
17928OPGEN_RETURN(false);
17929if (!args[4].tmp().isFP())
17930OPGEN_RETURN(false);
17931if (!args[5].tmp().isFP())
17932OPGEN_RETURN(false);
17933OPGEN_RETURN(true);
17934#endif
17935break;
17936break;
17937default:
17938break;
17939}
17940break;
17941default:
17942break;
17943}
17944break;
17945default:
17946break;
17947}
17948break;
17949default:
17950break;
17951}
17952break;
17953case Arg::Addr:
17954case Arg::Stack:
17955case Arg::CallArg:
17956switch (this->args[2].kind()) {
17957case Arg::Tmp:
17958switch (this->args[3].kind()) {
17959case Arg::Tmp:
17960switch (this->args[4].kind()) {
17961case Arg::Tmp:
17962switch (this->args[5].kind()) {
17963case Arg::Tmp:
17964#if CPU(X86_64)
17965if (!Arg::isValidAddrForm(args[1].offset()))
17966OPGEN_RETURN(false);
17967if (!args[2].tmp().isGP())
17968OPGEN_RETURN(false);
17969if (!args[3].tmp().isFP())
17970OPGEN_RETURN(false);
17971if (!args[4].tmp().isFP())
17972OPGEN_RETURN(false);
17973if (!args[5].tmp().isFP())
17974OPGEN_RETURN(false);
17975OPGEN_RETURN(true);
17976#endif
17977break;
17978break;
17979default:
17980break;
17981}
17982break;
17983default:
17984break;
17985}
17986break;
17987default:
17988break;
17989}
17990break;
17991case Arg::Imm:
17992switch (this->args[3].kind()) {
17993case Arg::Tmp:
17994switch (this->args[4].kind()) {
17995case Arg::Tmp:
17996switch (this->args[5].kind()) {
17997case Arg::Tmp:
17998#if CPU(X86_64)
17999if (!Arg::isValidAddrForm(args[1].offset()))
18000OPGEN_RETURN(false);
18001if (!Arg::isValidImmForm(args[2].value()))
18002OPGEN_RETURN(false);
18003if (!args[3].tmp().isFP())
18004OPGEN_RETURN(false);
18005if (!args[4].tmp().isFP())
18006OPGEN_RETURN(false);
18007if (!args[5].tmp().isFP())
18008OPGEN_RETURN(false);
18009OPGEN_RETURN(true);
18010#endif
18011break;
18012break;
18013default:
18014break;
18015}
18016break;
18017default:
18018break;
18019}
18020break;
18021default:
18022break;
18023}
18024break;
18025default:
18026break;
18027}
18028break;
18029case Arg::Index:
18030switch (this->args[2].kind()) {
18031case Arg::Tmp:
18032switch (this->args[3].kind()) {
18033case Arg::Tmp:
18034switch (this->args[4].kind()) {
18035case Arg::Tmp:
18036switch (this->args[5].kind()) {
18037case Arg::Tmp:
18038#if CPU(X86_64)
18039if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
18040OPGEN_RETURN(false);
18041if (!args[2].tmp().isGP())
18042OPGEN_RETURN(false);
18043if (!args[3].tmp().isFP())
18044OPGEN_RETURN(false);
18045if (!args[4].tmp().isFP())
18046OPGEN_RETURN(false);
18047if (!args[5].tmp().isFP())
18048OPGEN_RETURN(false);
18049OPGEN_RETURN(true);
18050#endif
18051break;
18052break;
18053default:
18054break;
18055}
18056break;
18057default:
18058break;
18059}
18060break;
18061default:
18062break;
18063}
18064break;
18065default:
18066break;
18067}
18068break;
18069default:
18070break;
18071}
18072break;
18073default:
18074break;
18075}
18076break;
18077default:
18078break;
18079}
18080break;
18081case Opcode::MoveDoubleConditionallyTest32:
18082switch (this->args.size()) {
18083case 6:
18084switch (this->args[0].kind()) {
18085case Arg::ResCond:
18086switch (this->args[1].kind()) {
18087case Arg::Tmp:
18088switch (this->args[2].kind()) {
18089case Arg::Tmp:
18090switch (this->args[3].kind()) {
18091case Arg::Tmp:
18092switch (this->args[4].kind()) {
18093case Arg::Tmp:
18094switch (this->args[5].kind()) {
18095case Arg::Tmp:
18096if (!args[1].tmp().isGP())
18097OPGEN_RETURN(false);
18098if (!args[2].tmp().isGP())
18099OPGEN_RETURN(false);
18100if (!args[3].tmp().isFP())
18101OPGEN_RETURN(false);
18102if (!args[4].tmp().isFP())
18103OPGEN_RETURN(false);
18104if (!args[5].tmp().isFP())
18105OPGEN_RETURN(false);
18106OPGEN_RETURN(true);
18107break;
18108break;
18109default:
18110break;
18111}
18112break;
18113default:
18114break;
18115}
18116break;
18117default:
18118break;
18119}
18120break;
18121case Arg::BitImm:
18122switch (this->args[3].kind()) {
18123case Arg::Tmp:
18124switch (this->args[4].kind()) {
18125case Arg::Tmp:
18126switch (this->args[5].kind()) {
18127case Arg::Tmp:
18128if (!args[1].tmp().isGP())
18129OPGEN_RETURN(false);
18130if (!Arg::isValidBitImmForm(args[2].value()))
18131OPGEN_RETURN(false);
18132if (!args[3].tmp().isFP())
18133OPGEN_RETURN(false);
18134if (!args[4].tmp().isFP())
18135OPGEN_RETURN(false);
18136if (!args[5].tmp().isFP())
18137OPGEN_RETURN(false);
18138OPGEN_RETURN(true);
18139break;
18140break;
18141default:
18142break;
18143}
18144break;
18145default:
18146break;
18147}
18148break;
18149default:
18150break;
18151}
18152break;
18153default:
18154break;
18155}
18156break;
18157case Arg::Addr:
18158case Arg::Stack:
18159case Arg::CallArg:
18160switch (this->args[2].kind()) {
18161case Arg::Imm:
18162switch (this->args[3].kind()) {
18163case Arg::Tmp:
18164switch (this->args[4].kind()) {
18165case Arg::Tmp:
18166switch (this->args[5].kind()) {
18167case Arg::Tmp:
18168#if CPU(X86) || CPU(X86_64)
18169if (!Arg::isValidAddrForm(args[1].offset()))
18170OPGEN_RETURN(false);
18171if (!Arg::isValidImmForm(args[2].value()))
18172OPGEN_RETURN(false);
18173if (!args[3].tmp().isFP())
18174OPGEN_RETURN(false);
18175if (!args[4].tmp().isFP())
18176OPGEN_RETURN(false);
18177if (!args[5].tmp().isFP())
18178OPGEN_RETURN(false);
18179OPGEN_RETURN(true);
18180#endif
18181break;
18182break;
18183default:
18184break;
18185}
18186break;
18187default:
18188break;
18189}
18190break;
18191default:
18192break;
18193}
18194break;
18195default:
18196break;
18197}
18198break;
18199case Arg::Index:
18200switch (this->args[2].kind()) {
18201case Arg::Imm:
18202switch (this->args[3].kind()) {
18203case Arg::Tmp:
18204switch (this->args[4].kind()) {
18205case Arg::Tmp:
18206switch (this->args[5].kind()) {
18207case Arg::Tmp:
18208#if CPU(X86) || CPU(X86_64)
18209if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
18210OPGEN_RETURN(false);
18211if (!Arg::isValidImmForm(args[2].value()))
18212OPGEN_RETURN(false);
18213if (!args[3].tmp().isFP())
18214OPGEN_RETURN(false);
18215if (!args[4].tmp().isFP())
18216OPGEN_RETURN(false);
18217if (!args[5].tmp().isFP())
18218OPGEN_RETURN(false);
18219OPGEN_RETURN(true);
18220#endif
18221break;
18222break;
18223default:
18224break;
18225}
18226break;
18227default:
18228break;
18229}
18230break;
18231default:
18232break;
18233}
18234break;
18235default:
18236break;
18237}
18238break;
18239default:
18240break;
18241}
18242break;
18243default:
18244break;
18245}
18246break;
18247default:
18248break;
18249}
18250break;
18251case Opcode::MoveDoubleConditionallyTest64:
18252switch (this->args.size()) {
18253case 6:
18254switch (this->args[0].kind()) {
18255case Arg::ResCond:
18256switch (this->args[1].kind()) {
18257case Arg::Tmp:
18258switch (this->args[2].kind()) {
18259case Arg::Tmp:
18260switch (this->args[3].kind()) {
18261case Arg::Tmp:
18262switch (this->args[4].kind()) {
18263case Arg::Tmp:
18264switch (this->args[5].kind()) {
18265case Arg::Tmp:
18266#if CPU(X86_64) || CPU(ARM64)
18267if (!args[1].tmp().isGP())
18268OPGEN_RETURN(false);
18269if (!args[2].tmp().isGP())
18270OPGEN_RETURN(false);
18271if (!args[3].tmp().isFP())
18272OPGEN_RETURN(false);
18273if (!args[4].tmp().isFP())
18274OPGEN_RETURN(false);
18275if (!args[5].tmp().isFP())
18276OPGEN_RETURN(false);
18277OPGEN_RETURN(true);
18278#endif
18279break;
18280break;
18281default:
18282break;
18283}
18284break;
18285default:
18286break;
18287}
18288break;
18289default:
18290break;
18291}
18292break;
18293case Arg::Imm:
18294switch (this->args[3].kind()) {
18295case Arg::Tmp:
18296switch (this->args[4].kind()) {
18297case Arg::Tmp:
18298switch (this->args[5].kind()) {
18299case Arg::Tmp:
18300#if CPU(X86_64)
18301if (!args[1].tmp().isGP())
18302OPGEN_RETURN(false);
18303if (!Arg::isValidImmForm(args[2].value()))
18304OPGEN_RETURN(false);
18305if (!args[3].tmp().isFP())
18306OPGEN_RETURN(false);
18307if (!args[4].tmp().isFP())
18308OPGEN_RETURN(false);
18309if (!args[5].tmp().isFP())
18310OPGEN_RETURN(false);
18311OPGEN_RETURN(true);
18312#endif
18313break;
18314break;
18315default:
18316break;
18317}
18318break;
18319default:
18320break;
18321}
18322break;
18323default:
18324break;
18325}
18326break;
18327default:
18328break;
18329}
18330break;
18331case Arg::Addr:
18332case Arg::Stack:
18333case Arg::CallArg:
18334switch (this->args[2].kind()) {
18335case Arg::Imm:
18336switch (this->args[3].kind()) {
18337case Arg::Tmp:
18338switch (this->args[4].kind()) {
18339case Arg::Tmp:
18340switch (this->args[5].kind()) {
18341case Arg::Tmp:
18342#if CPU(X86_64)
18343if (!Arg::isValidAddrForm(args[1].offset()))
18344OPGEN_RETURN(false);
18345if (!Arg::isValidImmForm(args[2].value()))
18346OPGEN_RETURN(false);
18347if (!args[3].tmp().isFP())
18348OPGEN_RETURN(false);
18349if (!args[4].tmp().isFP())
18350OPGEN_RETURN(false);
18351if (!args[5].tmp().isFP())
18352OPGEN_RETURN(false);
18353OPGEN_RETURN(true);
18354#endif
18355break;
18356break;
18357default:
18358break;
18359}
18360break;
18361default:
18362break;
18363}
18364break;
18365default:
18366break;
18367}
18368break;
18369case Arg::Tmp:
18370switch (this->args[3].kind()) {
18371case Arg::Tmp:
18372switch (this->args[4].kind()) {
18373case Arg::Tmp:
18374switch (this->args[5].kind()) {
18375case Arg::Tmp:
18376#if CPU(X86_64)
18377if (!Arg::isValidAddrForm(args[1].offset()))
18378OPGEN_RETURN(false);
18379if (!args[2].tmp().isGP())
18380OPGEN_RETURN(false);
18381if (!args[3].tmp().isFP())
18382OPGEN_RETURN(false);
18383if (!args[4].tmp().isFP())
18384OPGEN_RETURN(false);
18385if (!args[5].tmp().isFP())
18386OPGEN_RETURN(false);
18387OPGEN_RETURN(true);
18388#endif
18389break;
18390break;
18391default:
18392break;
18393}
18394break;
18395default:
18396break;
18397}
18398break;
18399default:
18400break;
18401}
18402break;
18403default:
18404break;
18405}
18406break;
18407case Arg::Index:
18408switch (this->args[2].kind()) {
18409case Arg::Imm:
18410switch (this->args[3].kind()) {
18411case Arg::Tmp:
18412switch (this->args[4].kind()) {
18413case Arg::Tmp:
18414switch (this->args[5].kind()) {
18415case Arg::Tmp:
18416#if CPU(X86_64)
18417if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
18418OPGEN_RETURN(false);
18419if (!Arg::isValidImmForm(args[2].value()))
18420OPGEN_RETURN(false);
18421if (!args[3].tmp().isFP())
18422OPGEN_RETURN(false);
18423if (!args[4].tmp().isFP())
18424OPGEN_RETURN(false);
18425if (!args[5].tmp().isFP())
18426OPGEN_RETURN(false);
18427OPGEN_RETURN(true);
18428#endif
18429break;
18430break;
18431default:
18432break;
18433}
18434break;
18435default:
18436break;
18437}
18438break;
18439default:
18440break;
18441}
18442break;
18443default:
18444break;
18445}
18446break;
18447default:
18448break;
18449}
18450break;
18451default:
18452break;
18453}
18454break;
18455default:
18456break;
18457}
18458break;
18459case Opcode::MoveDoubleConditionallyDouble:
18460switch (this->args.size()) {
18461case 6:
18462switch (this->args[0].kind()) {
18463case Arg::DoubleCond:
18464switch (this->args[1].kind()) {
18465case Arg::Tmp:
18466switch (this->args[2].kind()) {
18467case Arg::Tmp:
18468switch (this->args[3].kind()) {
18469case Arg::Tmp:
18470switch (this->args[4].kind()) {
18471case Arg::Tmp:
18472switch (this->args[5].kind()) {
18473case Arg::Tmp:
18474if (!args[1].tmp().isFP())
18475OPGEN_RETURN(false);
18476if (!args[2].tmp().isFP())
18477OPGEN_RETURN(false);
18478if (!args[3].tmp().isFP())
18479OPGEN_RETURN(false);
18480if (!args[4].tmp().isFP())
18481OPGEN_RETURN(false);
18482if (!args[5].tmp().isFP())
18483OPGEN_RETURN(false);
18484OPGEN_RETURN(true);
18485break;
18486break;
18487default:
18488break;
18489}
18490break;
18491default:
18492break;
18493}
18494break;
18495default:
18496break;
18497}
18498break;
18499default:
18500break;
18501}
18502break;
18503default:
18504break;
18505}
18506break;
18507default:
18508break;
18509}
18510break;
18511default:
18512break;
18513}
18514break;
18515case Opcode::MoveDoubleConditionallyFloat:
18516switch (this->args.size()) {
18517case 6:
18518switch (this->args[0].kind()) {
18519case Arg::DoubleCond:
18520switch (this->args[1].kind()) {
18521case Arg::Tmp:
18522switch (this->args[2].kind()) {
18523case Arg::Tmp:
18524switch (this->args[3].kind()) {
18525case Arg::Tmp:
18526switch (this->args[4].kind()) {
18527case Arg::Tmp:
18528switch (this->args[5].kind()) {
18529case Arg::Tmp:
18530if (!args[1].tmp().isFP())
18531OPGEN_RETURN(false);
18532if (!args[2].tmp().isFP())
18533OPGEN_RETURN(false);
18534if (!args[3].tmp().isFP())
18535OPGEN_RETURN(false);
18536if (!args[4].tmp().isFP())
18537OPGEN_RETURN(false);
18538if (!args[5].tmp().isFP())
18539OPGEN_RETURN(false);
18540OPGEN_RETURN(true);
18541break;
18542break;
18543default:
18544break;
18545}
18546break;
18547default:
18548break;
18549}
18550break;
18551default:
18552break;
18553}
18554break;
18555default:
18556break;
18557}
18558break;
18559default:
18560break;
18561}
18562break;
18563default:
18564break;
18565}
18566break;
18567default:
18568break;
18569}
18570break;
18571case Opcode::MemoryFence:
18572switch (this->args.size()) {
18573case 0:
18574OPGEN_RETURN(true);
18575break;
18576break;
18577default:
18578break;
18579}
18580break;
18581case Opcode::StoreFence:
18582switch (this->args.size()) {
18583case 0:
18584OPGEN_RETURN(true);
18585break;
18586break;
18587default:
18588break;
18589}
18590break;
18591case Opcode::LoadFence:
18592switch (this->args.size()) {
18593case 0:
18594OPGEN_RETURN(true);
18595break;
18596break;
18597default:
18598break;
18599}
18600break;
18601case Opcode::Jump:
18602switch (this->args.size()) {
18603case 0:
18604OPGEN_RETURN(true);
18605break;
18606break;
18607default:
18608break;
18609}
18610break;
18611case Opcode::RetVoid:
18612switch (this->args.size()) {
18613case 0:
18614OPGEN_RETURN(true);
18615break;
18616break;
18617default:
18618break;
18619}
18620break;
18621case Opcode::Ret32:
18622switch (this->args.size()) {
18623case 1:
18624switch (this->args[0].kind()) {
18625case Arg::Tmp:
18626if (!args[0].tmp().isGP())
18627OPGEN_RETURN(false);
18628OPGEN_RETURN(true);
18629break;
18630break;
18631default:
18632break;
18633}
18634break;
18635default:
18636break;
18637}
18638break;
18639case Opcode::Ret64:
18640switch (this->args.size()) {
18641case 1:
18642switch (this->args[0].kind()) {
18643case Arg::Tmp:
18644#if CPU(X86_64) || CPU(ARM64)
18645if (!args[0].tmp().isGP())
18646OPGEN_RETURN(false);
18647OPGEN_RETURN(true);
18648#endif
18649break;
18650break;
18651default:
18652break;
18653}
18654break;
18655default:
18656break;
18657}
18658break;
18659case Opcode::RetFloat:
18660switch (this->args.size()) {
18661case 1:
18662switch (this->args[0].kind()) {
18663case Arg::Tmp:
18664if (!args[0].tmp().isFP())
18665OPGEN_RETURN(false);
18666OPGEN_RETURN(true);
18667break;
18668break;
18669default:
18670break;
18671}
18672break;
18673default:
18674break;
18675}
18676break;
18677case Opcode::RetDouble:
18678switch (this->args.size()) {
18679case 1:
18680switch (this->args[0].kind()) {
18681case Arg::Tmp:
18682if (!args[0].tmp().isFP())
18683OPGEN_RETURN(false);
18684OPGEN_RETURN(true);
18685break;
18686break;
18687default:
18688break;
18689}
18690break;
18691default:
18692break;
18693}
18694break;
18695case Opcode::Oops:
18696switch (this->args.size()) {
18697case 0:
18698OPGEN_RETURN(true);
18699break;
18700break;
18701default:
18702break;
18703}
18704break;
18705case Opcode::EntrySwitch:
18706OPGEN_RETURN(EntrySwitchCustom::isValidForm(*this));
18707break;
18708case Opcode::Shuffle:
18709OPGEN_RETURN(ShuffleCustom::isValidForm(*this));
18710break;
18711case Opcode::Patch:
18712OPGEN_RETURN(PatchCustom::isValidForm(*this));
18713break;
18714case Opcode::CCall:
18715OPGEN_RETURN(CCallCustom::isValidForm(*this));
18716break;
18717case Opcode::ColdCCall:
18718OPGEN_RETURN(ColdCCallCustom::isValidForm(*this));
18719break;
18720case Opcode::WasmBoundsCheck:
18721OPGEN_RETURN(WasmBoundsCheckCustom::isValidForm(*this));
18722break;
18723default:
18724break;
18725}
18726return false;
18727}
18728bool Inst::admitsStack(unsigned argIndex)
18729{
18730switch (kind.opcode) {
18731case Opcode::Nop:
18732switch (argIndex) {
18733default:
18734break;
18735}
18736break;
18737case Opcode::Add32:
18738switch (argIndex) {
18739case 0:
18740switch (args.size()) {
18741case 2:
18742switch (Arg::Addr) {
18743case Arg::Tmp:
18744break;
18745case Arg::Imm:
18746break;
18747case Arg::Addr:
18748case Arg::Stack:
18749case Arg::CallArg:
18750switch (args[1].kind()) {
18751case Arg::Tmp:
18752#if CPU(X86) || CPU(X86_64)
18753OPGEN_RETURN(true);
18754#endif
18755break;
18756break;
18757default:
18758break;
18759}
18760break;
18761case Arg::Index:
18762break;
18763default:
18764break;
18765}
18766break;
18767default:
18768break;
18769}
18770break;
18771case 1:
18772switch (args.size()) {
18773case 2:
18774switch (args[0].kind()) {
18775case Arg::Tmp:
18776switch (Arg::Addr) {
18777case Arg::Tmp:
18778break;
18779case Arg::Addr:
18780case Arg::Stack:
18781case Arg::CallArg:
18782#if CPU(X86) || CPU(X86_64)
18783OPGEN_RETURN(true);
18784#endif
18785break;
18786break;
18787case Arg::Index:
18788break;
18789default:
18790break;
18791}
18792break;
18793case Arg::Imm:
18794switch (Arg::Addr) {
18795case Arg::Addr:
18796case Arg::Stack:
18797case Arg::CallArg:
18798#if CPU(X86) || CPU(X86_64)
18799OPGEN_RETURN(true);
18800#endif
18801break;
18802break;
18803case Arg::Index:
18804break;
18805case Arg::Tmp:
18806break;
18807default:
18808break;
18809}
18810break;
18811case Arg::Addr:
18812case Arg::Stack:
18813case Arg::CallArg:
18814break;
18815case Arg::Index:
18816break;
18817default:
18818break;
18819}
18820break;
18821default:
18822break;
18823}
18824break;
18825case 2:
18826OPGEN_RETURN(false);
18827break;
18828default:
18829break;
18830}
18831break;
18832case Opcode::Add8:
18833switch (argIndex) {
18834case 0:
18835OPGEN_RETURN(false);
18836break;
18837case 1:
18838switch (args[0].kind()) {
18839case Arg::Imm:
18840switch (Arg::Addr) {
18841case Arg::Addr:
18842case Arg::Stack:
18843case Arg::CallArg:
18844#if CPU(X86) || CPU(X86_64)
18845OPGEN_RETURN(true);
18846#endif
18847break;
18848break;
18849case Arg::Index:
18850break;
18851default:
18852break;
18853}
18854break;
18855case Arg::Tmp:
18856switch (Arg::Addr) {
18857case Arg::Addr:
18858case Arg::Stack:
18859case Arg::CallArg:
18860#if CPU(X86) || CPU(X86_64)
18861OPGEN_RETURN(true);
18862#endif
18863break;
18864break;
18865case Arg::Index:
18866break;
18867default:
18868break;
18869}
18870break;
18871default:
18872break;
18873}
18874break;
18875default:
18876break;
18877}
18878break;
18879case Opcode::Add16:
18880switch (argIndex) {
18881case 0:
18882OPGEN_RETURN(false);
18883break;
18884case 1:
18885switch (args[0].kind()) {
18886case Arg::Imm:
18887switch (Arg::Addr) {
18888case Arg::Addr:
18889case Arg::Stack:
18890case Arg::CallArg:
18891#if CPU(X86) || CPU(X86_64)
18892OPGEN_RETURN(true);
18893#endif
18894break;
18895break;
18896case Arg::Index:
18897break;
18898default:
18899break;
18900}
18901break;
18902case Arg::Tmp:
18903switch (Arg::Addr) {
18904case Arg::Addr:
18905case Arg::Stack:
18906case Arg::CallArg:
18907#if CPU(X86) || CPU(X86_64)
18908OPGEN_RETURN(true);
18909#endif
18910break;
18911break;
18912case Arg::Index:
18913break;
18914default:
18915break;
18916}
18917break;
18918default:
18919break;
18920}
18921break;
18922default:
18923break;
18924}
18925break;
18926case Opcode::Add64:
18927switch (argIndex) {
18928case 0:
18929switch (args.size()) {
18930case 2:
18931switch (Arg::Addr) {
18932case Arg::Tmp:
18933break;
18934case Arg::Imm:
18935break;
18936case Arg::Addr:
18937case Arg::Stack:
18938case Arg::CallArg:
18939switch (args[1].kind()) {
18940case Arg::Tmp:
18941#if CPU(X86_64)
18942OPGEN_RETURN(true);
18943#endif
18944break;
18945break;
18946default:
18947break;
18948}
18949break;
18950case Arg::Index:
18951break;
18952default:
18953break;
18954}
18955break;
18956default:
18957break;
18958}
18959break;
18960case 1:
18961switch (args.size()) {
18962case 2:
18963switch (args[0].kind()) {
18964case Arg::Tmp:
18965switch (Arg::Addr) {
18966case Arg::Tmp:
18967break;
18968case Arg::Addr:
18969case Arg::Stack:
18970case Arg::CallArg:
18971#if CPU(X86_64)
18972OPGEN_RETURN(true);
18973#endif
18974break;
18975break;
18976case Arg::Index:
18977break;
18978default:
18979break;
18980}
18981break;
18982case Arg::Imm:
18983switch (Arg::Addr) {
18984case Arg::Addr:
18985case Arg::Stack:
18986case Arg::CallArg:
18987#if CPU(X86_64)
18988OPGEN_RETURN(true);
18989#endif
18990break;
18991break;
18992case Arg::Index:
18993break;
18994case Arg::Tmp:
18995break;
18996default:
18997break;
18998}
18999break;
19000case Arg::Addr:
19001case Arg::Stack:
19002case Arg::CallArg:
19003break;
19004case Arg::Index:
19005break;
19006default:
19007break;
19008}
19009break;
19010default:
19011break;
19012}
19013break;
19014case 2:
19015OPGEN_RETURN(false);
19016break;
19017default:
19018break;
19019}
19020break;
19021case Opcode::AddDouble:
19022switch (argIndex) {
19023case 0:
19024switch (args.size()) {
19025case 3:
19026switch (Arg::Addr) {
19027case Arg::Tmp:
19028break;
19029case Arg::Addr:
19030case Arg::Stack:
19031case Arg::CallArg:
19032switch (args[1].kind()) {
19033case Arg::Tmp:
19034switch (args[2].kind()) {
19035case Arg::Tmp:
19036#if CPU(X86) || CPU(X86_64)
19037OPGEN_RETURN(true);
19038#endif
19039break;
19040break;
19041default:
19042break;
19043}
19044break;
19045default:
19046break;
19047}
19048break;
19049case Arg::Index:
19050break;
19051default:
19052break;
19053}
19054break;
19055case 2:
19056switch (Arg::Addr) {
19057case Arg::Tmp:
19058break;
19059case Arg::Addr:
19060case Arg::Stack:
19061case Arg::CallArg:
19062switch (args[1].kind()) {
19063case Arg::Tmp:
19064#if CPU(X86) || CPU(X86_64)
19065OPGEN_RETURN(true);
19066#endif
19067break;
19068break;
19069default:
19070break;
19071}
19072break;
19073default:
19074break;
19075}
19076break;
19077default:
19078break;
19079}
19080break;
19081case 1:
19082switch (args.size()) {
19083case 3:
19084switch (args[0].kind()) {
19085case Arg::Tmp:
19086switch (Arg::Addr) {
19087case Arg::Tmp:
19088break;
19089case Arg::Addr:
19090case Arg::Stack:
19091case Arg::CallArg:
19092switch (args[2].kind()) {
19093case Arg::Tmp:
19094#if CPU(X86) || CPU(X86_64)
19095OPGEN_RETURN(true);
19096#endif
19097break;
19098break;
19099default:
19100break;
19101}
19102break;
19103default:
19104break;
19105}
19106break;
19107case Arg::Addr:
19108case Arg::Stack:
19109case Arg::CallArg:
19110break;
19111case Arg::Index:
19112break;
19113default:
19114break;
19115}
19116break;
19117default:
19118break;
19119}
19120break;
19121case 2:
19122OPGEN_RETURN(false);
19123break;
19124default:
19125break;
19126}
19127break;
19128case Opcode::AddFloat:
19129switch (argIndex) {
19130case 0:
19131switch (args.size()) {
19132case 3:
19133switch (Arg::Addr) {
19134case Arg::Tmp:
19135break;
19136case Arg::Addr:
19137case Arg::Stack:
19138case Arg::CallArg:
19139switch (args[1].kind()) {
19140case Arg::Tmp:
19141switch (args[2].kind()) {
19142case Arg::Tmp:
19143#if CPU(X86) || CPU(X86_64)
19144OPGEN_RETURN(true);
19145#endif
19146break;
19147break;
19148default:
19149break;
19150}
19151break;
19152default:
19153break;
19154}
19155break;
19156case Arg::Index:
19157break;
19158default:
19159break;
19160}
19161break;
19162case 2:
19163switch (Arg::Addr) {
19164case Arg::Tmp:
19165break;
19166case Arg::Addr:
19167case Arg::Stack:
19168case Arg::CallArg:
19169switch (args[1].kind()) {
19170case Arg::Tmp:
19171#if CPU(X86) || CPU(X86_64)
19172OPGEN_RETURN(true);
19173#endif
19174break;
19175break;
19176default:
19177break;
19178}
19179break;
19180default:
19181break;
19182}
19183break;
19184default:
19185break;
19186}
19187break;
19188case 1:
19189switch (args.size()) {
19190case 3:
19191switch (args[0].kind()) {
19192case Arg::Tmp:
19193switch (Arg::Addr) {
19194case Arg::Tmp:
19195break;
19196case Arg::Addr:
19197case Arg::Stack:
19198case Arg::CallArg:
19199switch (args[2].kind()) {
19200case Arg::Tmp:
19201#if CPU(X86) || CPU(X86_64)
19202OPGEN_RETURN(true);
19203#endif
19204break;
19205break;
19206default:
19207break;
19208}
19209break;
19210default:
19211break;
19212}
19213break;
19214case Arg::Addr:
19215case Arg::Stack:
19216case Arg::CallArg:
19217break;
19218case Arg::Index:
19219break;
19220default:
19221break;
19222}
19223break;
19224default:
19225break;
19226}
19227break;
19228case 2:
19229OPGEN_RETURN(false);
19230break;
19231default:
19232break;
19233}
19234break;
19235case Opcode::Sub32:
19236switch (argIndex) {
19237case 0:
19238switch (args.size()) {
19239case 2:
19240switch (Arg::Addr) {
19241case Arg::Tmp:
19242break;
19243case Arg::Imm:
19244break;
19245case Arg::Addr:
19246case Arg::Stack:
19247case Arg::CallArg:
19248switch (args[1].kind()) {
19249case Arg::Tmp:
19250#if CPU(X86) || CPU(X86_64)
19251OPGEN_RETURN(true);
19252#endif
19253break;
19254break;
19255default:
19256break;
19257}
19258break;
19259case Arg::Index:
19260break;
19261default:
19262break;
19263}
19264break;
19265default:
19266break;
19267}
19268break;
19269case 1:
19270switch (args.size()) {
19271case 2:
19272switch (args[0].kind()) {
19273case Arg::Tmp:
19274switch (Arg::Addr) {
19275case Arg::Tmp:
19276break;
19277case Arg::Addr:
19278case Arg::Stack:
19279case Arg::CallArg:
19280#if CPU(X86) || CPU(X86_64)
19281OPGEN_RETURN(true);
19282#endif
19283break;
19284break;
19285case Arg::Index:
19286break;
19287default:
19288break;
19289}
19290break;
19291case Arg::Imm:
19292switch (Arg::Addr) {
19293case Arg::Addr:
19294case Arg::Stack:
19295case Arg::CallArg:
19296#if CPU(X86) || CPU(X86_64)
19297OPGEN_RETURN(true);
19298#endif
19299break;
19300break;
19301case Arg::Index:
19302break;
19303case Arg::Tmp:
19304break;
19305default:
19306break;
19307}
19308break;
19309case Arg::Addr:
19310case Arg::Stack:
19311case Arg::CallArg:
19312break;
19313case Arg::Index:
19314break;
19315default:
19316break;
19317}
19318break;
19319default:
19320break;
19321}
19322break;
19323case 2:
19324OPGEN_RETURN(false);
19325break;
19326default:
19327break;
19328}
19329break;
19330case Opcode::Sub64:
19331switch (argIndex) {
19332case 0:
19333switch (args.size()) {
19334case 2:
19335switch (Arg::Addr) {
19336case Arg::Tmp:
19337break;
19338case Arg::Imm:
19339break;
19340case Arg::Addr:
19341case Arg::Stack:
19342case Arg::CallArg:
19343switch (args[1].kind()) {
19344case Arg::Tmp:
19345#if CPU(X86_64)
19346OPGEN_RETURN(true);
19347#endif
19348break;
19349break;
19350default:
19351break;
19352}
19353break;
19354case Arg::Index:
19355break;
19356default:
19357break;
19358}
19359break;
19360default:
19361break;
19362}
19363break;
19364case 1:
19365switch (args.size()) {
19366case 2:
19367switch (args[0].kind()) {
19368case Arg::Tmp:
19369switch (Arg::Addr) {
19370case Arg::Tmp:
19371break;
19372case Arg::Addr:
19373case Arg::Stack:
19374case Arg::CallArg:
19375#if CPU(X86_64)
19376OPGEN_RETURN(true);
19377#endif
19378break;
19379break;
19380case Arg::Index:
19381break;
19382default:
19383break;
19384}
19385break;
19386case Arg::Imm:
19387switch (Arg::Addr) {
19388case Arg::Addr:
19389case Arg::Stack:
19390case Arg::CallArg:
19391#if CPU(X86_64)
19392OPGEN_RETURN(true);
19393#endif
19394break;
19395break;
19396case Arg::Index:
19397break;
19398case Arg::Tmp:
19399break;
19400default:
19401break;
19402}
19403break;
19404case Arg::Addr:
19405case Arg::Stack:
19406case Arg::CallArg:
19407break;
19408case Arg::Index:
19409break;
19410default:
19411break;
19412}
19413break;
19414default:
19415break;
19416}
19417break;
19418case 2:
19419OPGEN_RETURN(false);
19420break;
19421default:
19422break;
19423}
19424break;
19425case Opcode::SubDouble:
19426switch (argIndex) {
19427case 0:
19428switch (args.size()) {
19429case 2:
19430switch (Arg::Addr) {
19431case Arg::Tmp:
19432break;
19433case Arg::Addr:
19434case Arg::Stack:
19435case Arg::CallArg:
19436switch (args[1].kind()) {
19437case Arg::Tmp:
19438#if CPU(X86) || CPU(X86_64)
19439OPGEN_RETURN(true);
19440#endif
19441break;
19442break;
19443default:
19444break;
19445}
19446break;
19447default:
19448break;
19449}
19450break;
19451default:
19452break;
19453}
19454break;
19455case 1:
19456switch (args.size()) {
19457case 3:
19458switch (args[0].kind()) {
19459case Arg::Tmp:
19460switch (Arg::Addr) {
19461case Arg::Tmp:
19462break;
19463case Arg::Addr:
19464case Arg::Stack:
19465case Arg::CallArg:
19466switch (args[2].kind()) {
19467case Arg::Tmp:
19468#if CPU(X86) || CPU(X86_64)
19469OPGEN_RETURN(true);
19470#endif
19471break;
19472break;
19473default:
19474break;
19475}
19476break;
19477case Arg::Index:
19478break;
19479default:
19480break;
19481}
19482break;
19483default:
19484break;
19485}
19486break;
19487default:
19488break;
19489}
19490break;
19491case 2:
19492OPGEN_RETURN(false);
19493break;
19494default:
19495break;
19496}
19497break;
19498case Opcode::SubFloat:
19499switch (argIndex) {
19500case 0:
19501switch (args.size()) {
19502case 2:
19503switch (Arg::Addr) {
19504case Arg::Tmp:
19505break;
19506case Arg::Addr:
19507case Arg::Stack:
19508case Arg::CallArg:
19509switch (args[1].kind()) {
19510case Arg::Tmp:
19511#if CPU(X86) || CPU(X86_64)
19512OPGEN_RETURN(true);
19513#endif
19514break;
19515break;
19516default:
19517break;
19518}
19519break;
19520default:
19521break;
19522}
19523break;
19524default:
19525break;
19526}
19527break;
19528case 1:
19529switch (args.size()) {
19530case 3:
19531switch (args[0].kind()) {
19532case Arg::Tmp:
19533switch (Arg::Addr) {
19534case Arg::Tmp:
19535break;
19536case Arg::Addr:
19537case Arg::Stack:
19538case Arg::CallArg:
19539switch (args[2].kind()) {
19540case Arg::Tmp:
19541#if CPU(X86) || CPU(X86_64)
19542OPGEN_RETURN(true);
19543#endif
19544break;
19545break;
19546default:
19547break;
19548}
19549break;
19550case Arg::Index:
19551break;
19552default:
19553break;
19554}
19555break;
19556default:
19557break;
19558}
19559break;
19560default:
19561break;
19562}
19563break;
19564case 2:
19565OPGEN_RETURN(false);
19566break;
19567default:
19568break;
19569}
19570break;
19571case Opcode::Neg32:
19572switch (argIndex) {
19573case 0:
19574switch (Arg::Addr) {
19575case Arg::Tmp:
19576break;
19577case Arg::Addr:
19578case Arg::Stack:
19579case Arg::CallArg:
19580#if CPU(X86) || CPU(X86_64)
19581OPGEN_RETURN(true);
19582#endif
19583break;
19584break;
19585case Arg::Index:
19586break;
19587default:
19588break;
19589}
19590break;
19591default:
19592break;
19593}
19594break;
19595case Opcode::Neg64:
19596switch (argIndex) {
19597case 0:
19598switch (Arg::Addr) {
19599case Arg::Tmp:
19600break;
19601case Arg::Addr:
19602case Arg::Stack:
19603case Arg::CallArg:
19604#if CPU(X86_64)
19605OPGEN_RETURN(true);
19606#endif
19607break;
19608break;
19609case Arg::Index:
19610break;
19611default:
19612break;
19613}
19614break;
19615default:
19616break;
19617}
19618break;
19619case Opcode::NegateDouble:
19620switch (argIndex) {
19621case 0:
19622OPGEN_RETURN(false);
19623break;
19624case 1:
19625OPGEN_RETURN(false);
19626break;
19627default:
19628break;
19629}
19630break;
19631case Opcode::NegateFloat:
19632switch (argIndex) {
19633case 0:
19634OPGEN_RETURN(false);
19635break;
19636case 1:
19637OPGEN_RETURN(false);
19638break;
19639default:
19640break;
19641}
19642break;
19643case Opcode::Mul32:
19644switch (argIndex) {
19645case 0:
19646switch (args.size()) {
19647case 2:
19648switch (Arg::Addr) {
19649case Arg::Tmp:
19650break;
19651case Arg::Addr:
19652case Arg::Stack:
19653case Arg::CallArg:
19654switch (args[1].kind()) {
19655case Arg::Tmp:
19656#if CPU(X86) || CPU(X86_64)
19657OPGEN_RETURN(true);
19658#endif
19659break;
19660break;
19661default:
19662break;
19663}
19664break;
19665default:
19666break;
19667}
19668break;
19669case 3:
19670switch (Arg::Addr) {
19671case Arg::Tmp:
19672break;
19673case Arg::Addr:
19674case Arg::Stack:
19675case Arg::CallArg:
19676switch (args[1].kind()) {
19677case Arg::Tmp:
19678switch (args[2].kind()) {
19679case Arg::Tmp:
19680#if CPU(X86) || CPU(X86_64)
19681OPGEN_RETURN(true);
19682#endif
19683break;
19684break;
19685default:
19686break;
19687}
19688break;
19689default:
19690break;
19691}
19692break;
19693case Arg::Imm:
19694break;
19695default:
19696break;
19697}
19698break;
19699default:
19700break;
19701}
19702break;
19703case 1:
19704switch (args.size()) {
19705case 3:
19706switch (args[0].kind()) {
19707case Arg::Tmp:
19708switch (Arg::Addr) {
19709case Arg::Tmp:
19710break;
19711case Arg::Addr:
19712case Arg::Stack:
19713case Arg::CallArg:
19714switch (args[2].kind()) {
19715case Arg::Tmp:
19716#if CPU(X86) || CPU(X86_64)
19717OPGEN_RETURN(true);
19718#endif
19719break;
19720break;
19721default:
19722break;
19723}
19724break;
19725default:
19726break;
19727}
19728break;
19729case Arg::Addr:
19730case Arg::Stack:
19731case Arg::CallArg:
19732break;
19733case Arg::Imm:
19734break;
19735default:
19736break;
19737}
19738break;
19739default:
19740break;
19741}
19742break;
19743case 2:
19744OPGEN_RETURN(false);
19745break;
19746default:
19747break;
19748}
19749break;
19750case Opcode::Mul64:
19751switch (argIndex) {
19752case 0:
19753OPGEN_RETURN(false);
19754break;
19755case 1:
19756OPGEN_RETURN(false);
19757break;
19758case 2:
19759OPGEN_RETURN(false);
19760break;
19761default:
19762break;
19763}
19764break;
19765case Opcode::MultiplyAdd32:
19766switch (argIndex) {
19767case 0:
19768OPGEN_RETURN(false);
19769break;
19770case 1:
19771OPGEN_RETURN(false);
19772break;
19773case 2:
19774OPGEN_RETURN(false);
19775break;
19776case 3:
19777OPGEN_RETURN(false);
19778break;
19779default:
19780break;
19781}
19782break;
19783case Opcode::MultiplyAdd64:
19784switch (argIndex) {
19785case 0:
19786OPGEN_RETURN(false);
19787break;
19788case 1:
19789OPGEN_RETURN(false);
19790break;
19791case 2:
19792OPGEN_RETURN(false);
19793break;
19794case 3:
19795OPGEN_RETURN(false);
19796break;
19797default:
19798break;
19799}
19800break;
19801case Opcode::MultiplySub32:
19802switch (argIndex) {
19803case 0:
19804OPGEN_RETURN(false);
19805break;
19806case 1:
19807OPGEN_RETURN(false);
19808break;
19809case 2:
19810OPGEN_RETURN(false);
19811break;
19812case 3:
19813OPGEN_RETURN(false);
19814break;
19815default:
19816break;
19817}
19818break;
19819case Opcode::MultiplySub64:
19820switch (argIndex) {
19821case 0:
19822OPGEN_RETURN(false);
19823break;
19824case 1:
19825OPGEN_RETURN(false);
19826break;
19827case 2:
19828OPGEN_RETURN(false);
19829break;
19830case 3:
19831OPGEN_RETURN(false);
19832break;
19833default:
19834break;
19835}
19836break;
19837case Opcode::MultiplyNeg32:
19838switch (argIndex) {
19839case 0:
19840OPGEN_RETURN(false);
19841break;
19842case 1:
19843OPGEN_RETURN(false);
19844break;
19845case 2:
19846OPGEN_RETURN(false);
19847break;
19848default:
19849break;
19850}
19851break;
19852case Opcode::MultiplyNeg64:
19853switch (argIndex) {
19854case 0:
19855OPGEN_RETURN(false);
19856break;
19857case 1:
19858OPGEN_RETURN(false);
19859break;
19860case 2:
19861OPGEN_RETURN(false);
19862break;
19863default:
19864break;
19865}
19866break;
19867case Opcode::MultiplySignExtend32:
19868switch (argIndex) {
19869case 0:
19870OPGEN_RETURN(false);
19871break;
19872case 1:
19873OPGEN_RETURN(false);
19874break;
19875case 2:
19876OPGEN_RETURN(false);
19877break;
19878default:
19879break;
19880}
19881break;
19882case Opcode::Div32:
19883switch (argIndex) {
19884case 0:
19885OPGEN_RETURN(false);
19886break;
19887case 1:
19888OPGEN_RETURN(false);
19889break;
19890case 2:
19891OPGEN_RETURN(false);
19892break;
19893default:
19894break;
19895}
19896break;
19897case Opcode::UDiv32:
19898switch (argIndex) {
19899case 0:
19900OPGEN_RETURN(false);
19901break;
19902case 1:
19903OPGEN_RETURN(false);
19904break;
19905case 2:
19906OPGEN_RETURN(false);
19907break;
19908default:
19909break;
19910}
19911break;
19912case Opcode::Div64:
19913switch (argIndex) {
19914case 0:
19915OPGEN_RETURN(false);
19916break;
19917case 1:
19918OPGEN_RETURN(false);
19919break;
19920case 2:
19921OPGEN_RETURN(false);
19922break;
19923default:
19924break;
19925}
19926break;
19927case Opcode::UDiv64:
19928switch (argIndex) {
19929case 0:
19930OPGEN_RETURN(false);
19931break;
19932case 1:
19933OPGEN_RETURN(false);
19934break;
19935case 2:
19936OPGEN_RETURN(false);
19937break;
19938default:
19939break;
19940}
19941break;
19942case Opcode::MulDouble:
19943switch (argIndex) {
19944case 0:
19945switch (args.size()) {
19946case 3:
19947switch (Arg::Addr) {
19948case Arg::Tmp:
19949break;
19950case Arg::Addr:
19951case Arg::Stack:
19952case Arg::CallArg:
19953switch (args[1].kind()) {
19954case Arg::Tmp:
19955switch (args[2].kind()) {
19956case Arg::Tmp:
19957#if CPU(X86) || CPU(X86_64)
19958OPGEN_RETURN(true);
19959#endif
19960break;
19961break;
19962default:
19963break;
19964}
19965break;
19966default:
19967break;
19968}
19969break;
19970case Arg::Index:
19971break;
19972default:
19973break;
19974}
19975break;
19976case 2:
19977switch (Arg::Addr) {
19978case Arg::Tmp:
19979break;
19980case Arg::Addr:
19981case Arg::Stack:
19982case Arg::CallArg:
19983switch (args[1].kind()) {
19984case Arg::Tmp:
19985#if CPU(X86) || CPU(X86_64)
19986OPGEN_RETURN(true);
19987#endif
19988break;
19989break;
19990default:
19991break;
19992}
19993break;
19994default:
19995break;
19996}
19997break;
19998default:
19999break;
20000}
20001break;
20002case 1:
20003switch (args.size()) {
20004case 3:
20005switch (args[0].kind()) {
20006case Arg::Tmp:
20007switch (Arg::Addr) {
20008case Arg::Tmp:
20009break;
20010case Arg::Addr:
20011case Arg::Stack:
20012case Arg::CallArg:
20013switch (args[2].kind()) {
20014case Arg::Tmp:
20015#if CPU(X86) || CPU(X86_64)
20016OPGEN_RETURN(true);
20017#endif
20018break;
20019break;
20020default:
20021break;
20022}
20023break;
20024default:
20025break;
20026}
20027break;
20028case Arg::Addr:
20029case Arg::Stack:
20030case Arg::CallArg:
20031break;
20032case Arg::Index:
20033break;
20034default:
20035break;
20036}
20037break;
20038default:
20039break;
20040}
20041break;
20042case 2:
20043OPGEN_RETURN(false);
20044break;
20045default:
20046break;
20047}
20048break;
20049case Opcode::MulFloat:
20050switch (argIndex) {
20051case 0:
20052switch (args.size()) {
20053case 3:
20054switch (Arg::Addr) {
20055case Arg::Tmp:
20056break;
20057case Arg::Addr:
20058case Arg::Stack:
20059case Arg::CallArg:
20060switch (args[1].kind()) {
20061case Arg::Tmp:
20062switch (args[2].kind()) {
20063case Arg::Tmp:
20064#if CPU(X86) || CPU(X86_64)
20065OPGEN_RETURN(true);
20066#endif
20067break;
20068break;
20069default:
20070break;
20071}
20072break;
20073default:
20074break;
20075}
20076break;
20077case Arg::Index:
20078break;
20079default:
20080break;
20081}
20082break;
20083case 2:
20084switch (Arg::Addr) {
20085case Arg::Tmp:
20086break;
20087case Arg::Addr:
20088case Arg::Stack:
20089case Arg::CallArg:
20090switch (args[1].kind()) {
20091case Arg::Tmp:
20092#if CPU(X86) || CPU(X86_64)
20093OPGEN_RETURN(true);
20094#endif
20095break;
20096break;
20097default:
20098break;
20099}
20100break;
20101default:
20102break;
20103}
20104break;
20105default:
20106break;
20107}
20108break;
20109case 1:
20110switch (args.size()) {
20111case 3:
20112switch (args[0].kind()) {
20113case Arg::Tmp:
20114switch (Arg::Addr) {
20115case Arg::Tmp:
20116break;
20117case Arg::Addr:
20118case Arg::Stack:
20119case Arg::CallArg:
20120switch (args[2].kind()) {
20121case Arg::Tmp:
20122#if CPU(X86) || CPU(X86_64)
20123OPGEN_RETURN(true);
20124#endif
20125break;
20126break;
20127default:
20128break;
20129}
20130break;
20131default:
20132break;
20133}
20134break;
20135case Arg::Addr:
20136case Arg::Stack:
20137case Arg::CallArg:
20138break;
20139case Arg::Index:
20140break;
20141default:
20142break;
20143}
20144break;
20145default:
20146break;
20147}
20148break;
20149case 2:
20150OPGEN_RETURN(false);
20151break;
20152default:
20153break;
20154}
20155break;
20156case Opcode::DivDouble:
20157switch (argIndex) {
20158case 0:
20159switch (args.size()) {
20160case 2:
20161switch (Arg::Addr) {
20162case Arg::Tmp:
20163break;
20164case Arg::Addr:
20165case Arg::Stack:
20166case Arg::CallArg:
20167switch (args[1].kind()) {
20168case Arg::Tmp:
20169#if CPU(X86) || CPU(X86_64)
20170OPGEN_RETURN(true);
20171#endif
20172break;
20173break;
20174default:
20175break;
20176}
20177break;
20178default:
20179break;
20180}
20181break;
20182default:
20183break;
20184}
20185break;
20186case 1:
20187OPGEN_RETURN(false);
20188break;
20189case 2:
20190OPGEN_RETURN(false);
20191break;
20192default:
20193break;
20194}
20195break;
20196case Opcode::DivFloat:
20197switch (argIndex) {
20198case 0:
20199switch (args.size()) {
20200case 2:
20201switch (Arg::Addr) {
20202case Arg::Tmp:
20203break;
20204case Arg::Addr:
20205case Arg::Stack:
20206case Arg::CallArg:
20207switch (args[1].kind()) {
20208case Arg::Tmp:
20209#if CPU(X86) || CPU(X86_64)
20210OPGEN_RETURN(true);
20211#endif
20212break;
20213break;
20214default:
20215break;
20216}
20217break;
20218default:
20219break;
20220}
20221break;
20222default:
20223break;
20224}
20225break;
20226case 1:
20227OPGEN_RETURN(false);
20228break;
20229case 2:
20230OPGEN_RETURN(false);
20231break;
20232default:
20233break;
20234}
20235break;
20236case Opcode::X86ConvertToDoubleWord32:
20237switch (argIndex) {
20238case 0:
20239OPGEN_RETURN(false);
20240break;
20241case 1:
20242OPGEN_RETURN(false);
20243break;
20244default:
20245break;
20246}
20247break;
20248case Opcode::X86ConvertToQuadWord64:
20249switch (argIndex) {
20250case 0:
20251OPGEN_RETURN(false);
20252break;
20253case 1:
20254OPGEN_RETURN(false);
20255break;
20256default:
20257break;
20258}
20259break;
20260case Opcode::X86Div32:
20261switch (argIndex) {
20262case 0:
20263OPGEN_RETURN(false);
20264break;
20265case 1:
20266OPGEN_RETURN(false);
20267break;
20268case 2:
20269OPGEN_RETURN(false);
20270break;
20271default:
20272break;
20273}
20274break;
20275case Opcode::X86UDiv32:
20276switch (argIndex) {
20277case 0:
20278OPGEN_RETURN(false);
20279break;
20280case 1:
20281OPGEN_RETURN(false);
20282break;
20283case 2:
20284OPGEN_RETURN(false);
20285break;
20286default:
20287break;
20288}
20289break;
20290case Opcode::X86Div64:
20291switch (argIndex) {
20292case 0:
20293OPGEN_RETURN(false);
20294break;
20295case 1:
20296OPGEN_RETURN(false);
20297break;
20298case 2:
20299OPGEN_RETURN(false);
20300break;
20301default:
20302break;
20303}
20304break;
20305case Opcode::X86UDiv64:
20306switch (argIndex) {
20307case 0:
20308OPGEN_RETURN(false);
20309break;
20310case 1:
20311OPGEN_RETURN(false);
20312break;
20313case 2:
20314OPGEN_RETURN(false);
20315break;
20316default:
20317break;
20318}
20319break;
20320case Opcode::Lea32:
20321switch (argIndex) {
20322case 0:
20323OPGEN_RETURN(false);
20324break;
20325case 1:
20326OPGEN_RETURN(false);
20327break;
20328default:
20329break;
20330}
20331break;
20332case Opcode::Lea64:
20333switch (argIndex) {
20334case 0:
20335OPGEN_RETURN(false);
20336break;
20337case 1:
20338OPGEN_RETURN(false);
20339break;
20340default:
20341break;
20342}
20343break;
20344case Opcode::And32:
20345switch (argIndex) {
20346case 0:
20347switch (args.size()) {
20348case 3:
20349switch (Arg::Addr) {
20350case Arg::Tmp:
20351break;
20352case Arg::BitImm:
20353break;
20354case Arg::Addr:
20355case Arg::Stack:
20356case Arg::CallArg:
20357switch (args[1].kind()) {
20358case Arg::Tmp:
20359switch (args[2].kind()) {
20360case Arg::Tmp:
20361#if CPU(X86) || CPU(X86_64)
20362OPGEN_RETURN(true);
20363#endif
20364break;
20365break;
20366default:
20367break;
20368}
20369break;
20370default:
20371break;
20372}
20373break;
20374default:
20375break;
20376}
20377break;
20378case 2:
20379switch (Arg::Addr) {
20380case Arg::Tmp:
20381break;
20382case Arg::Imm:
20383break;
20384case Arg::Addr:
20385case Arg::Stack:
20386case Arg::CallArg:
20387switch (args[1].kind()) {
20388case Arg::Tmp:
20389#if CPU(X86) || CPU(X86_64)
20390OPGEN_RETURN(true);
20391#endif
20392break;
20393break;
20394default:
20395break;
20396}
20397break;
20398case Arg::Index:
20399break;
20400default:
20401break;
20402}
20403break;
20404default:
20405break;
20406}
20407break;
20408case 1:
20409switch (args.size()) {
20410case 3:
20411switch (args[0].kind()) {
20412case Arg::Tmp:
20413switch (Arg::Addr) {
20414case Arg::Tmp:
20415break;
20416case Arg::Addr:
20417case Arg::Stack:
20418case Arg::CallArg:
20419switch (args[2].kind()) {
20420case Arg::Tmp:
20421#if CPU(X86) || CPU(X86_64)
20422OPGEN_RETURN(true);
20423#endif
20424break;
20425break;
20426default:
20427break;
20428}
20429break;
20430default:
20431break;
20432}
20433break;
20434case Arg::BitImm:
20435break;
20436case Arg::Addr:
20437case Arg::Stack:
20438case Arg::CallArg:
20439break;
20440default:
20441break;
20442}
20443break;
20444case 2:
20445switch (args[0].kind()) {
20446case Arg::Tmp:
20447switch (Arg::Addr) {
20448case Arg::Tmp:
20449break;
20450case Arg::Addr:
20451case Arg::Stack:
20452case Arg::CallArg:
20453#if CPU(X86) || CPU(X86_64)
20454OPGEN_RETURN(true);
20455#endif
20456break;
20457break;
20458case Arg::Index:
20459break;
20460default:
20461break;
20462}
20463break;
20464case Arg::Imm:
20465switch (Arg::Addr) {
20466case Arg::Tmp:
20467break;
20468case Arg::Addr:
20469case Arg::Stack:
20470case Arg::CallArg:
20471#if CPU(X86) || CPU(X86_64)
20472OPGEN_RETURN(true);
20473#endif
20474break;
20475break;
20476case Arg::Index:
20477break;
20478default:
20479break;
20480}
20481break;
20482case Arg::Addr:
20483case Arg::Stack:
20484case Arg::CallArg:
20485break;
20486case Arg::Index:
20487break;
20488default:
20489break;
20490}
20491break;
20492default:
20493break;
20494}
20495break;
20496case 2:
20497OPGEN_RETURN(false);
20498break;
20499default:
20500break;
20501}
20502break;
20503case Opcode::And64:
20504switch (argIndex) {
20505case 0:
20506switch (args.size()) {
20507case 2:
20508switch (Arg::Addr) {
20509case Arg::Tmp:
20510break;
20511case Arg::Imm:
20512break;
20513case Arg::Addr:
20514case Arg::Stack:
20515case Arg::CallArg:
20516switch (args[1].kind()) {
20517case Arg::Tmp:
20518#if CPU(X86_64)
20519OPGEN_RETURN(true);
20520#endif
20521break;
20522break;
20523default:
20524break;
20525}
20526break;
20527case Arg::Index:
20528break;
20529default:
20530break;
20531}
20532break;
20533default:
20534break;
20535}
20536break;
20537case 1:
20538switch (args.size()) {
20539case 2:
20540switch (args[0].kind()) {
20541case Arg::Tmp:
20542switch (Arg::Addr) {
20543case Arg::Tmp:
20544break;
20545case Arg::Addr:
20546case Arg::Stack:
20547case Arg::CallArg:
20548#if CPU(X86_64)
20549OPGEN_RETURN(true);
20550#endif
20551break;
20552break;
20553case Arg::Index:
20554break;
20555default:
20556break;
20557}
20558break;
20559case Arg::Imm:
20560switch (Arg::Addr) {
20561case Arg::Tmp:
20562break;
20563case Arg::Addr:
20564case Arg::Stack:
20565case Arg::CallArg:
20566#if CPU(X86_64)
20567OPGEN_RETURN(true);
20568#endif
20569break;
20570break;
20571case Arg::Index:
20572break;
20573default:
20574break;
20575}
20576break;
20577case Arg::Addr:
20578case Arg::Stack:
20579case Arg::CallArg:
20580break;
20581case Arg::Index:
20582break;
20583default:
20584break;
20585}
20586break;
20587default:
20588break;
20589}
20590break;
20591case 2:
20592OPGEN_RETURN(false);
20593break;
20594default:
20595break;
20596}
20597break;
20598case Opcode::AndDouble:
20599switch (argIndex) {
20600case 0:
20601OPGEN_RETURN(false);
20602break;
20603case 1:
20604OPGEN_RETURN(false);
20605break;
20606case 2:
20607OPGEN_RETURN(false);
20608break;
20609default:
20610break;
20611}
20612break;
20613case Opcode::AndFloat:
20614switch (argIndex) {
20615case 0:
20616OPGEN_RETURN(false);
20617break;
20618case 1:
20619OPGEN_RETURN(false);
20620break;
20621case 2:
20622OPGEN_RETURN(false);
20623break;
20624default:
20625break;
20626}
20627break;
20628case Opcode::OrDouble:
20629switch (argIndex) {
20630case 0:
20631OPGEN_RETURN(false);
20632break;
20633case 1:
20634OPGEN_RETURN(false);
20635break;
20636case 2:
20637OPGEN_RETURN(false);
20638break;
20639default:
20640break;
20641}
20642break;
20643case Opcode::OrFloat:
20644switch (argIndex) {
20645case 0:
20646OPGEN_RETURN(false);
20647break;
20648case 1:
20649OPGEN_RETURN(false);
20650break;
20651case 2:
20652OPGEN_RETURN(false);
20653break;
20654default:
20655break;
20656}
20657break;
20658case Opcode::XorDouble:
20659switch (argIndex) {
20660case 0:
20661OPGEN_RETURN(false);
20662break;
20663case 1:
20664OPGEN_RETURN(false);
20665break;
20666case 2:
20667OPGEN_RETURN(false);
20668break;
20669default:
20670break;
20671}
20672break;
20673case Opcode::XorFloat:
20674switch (argIndex) {
20675case 0:
20676OPGEN_RETURN(false);
20677break;
20678case 1:
20679OPGEN_RETURN(false);
20680break;
20681case 2:
20682OPGEN_RETURN(false);
20683break;
20684default:
20685break;
20686}
20687break;
20688case Opcode::Lshift32:
20689switch (argIndex) {
20690case 0:
20691OPGEN_RETURN(false);
20692break;
20693case 1:
20694OPGEN_RETURN(false);
20695break;
20696case 2:
20697OPGEN_RETURN(false);
20698break;
20699default:
20700break;
20701}
20702break;
20703case Opcode::Lshift64:
20704switch (argIndex) {
20705case 0:
20706OPGEN_RETURN(false);
20707break;
20708case 1:
20709OPGEN_RETURN(false);
20710break;
20711case 2:
20712OPGEN_RETURN(false);
20713break;
20714default:
20715break;
20716}
20717break;
20718case Opcode::Rshift32:
20719switch (argIndex) {
20720case 0:
20721OPGEN_RETURN(false);
20722break;
20723case 1:
20724OPGEN_RETURN(false);
20725break;
20726case 2:
20727OPGEN_RETURN(false);
20728break;
20729default:
20730break;
20731}
20732break;
20733case Opcode::Rshift64:
20734switch (argIndex) {
20735case 0:
20736OPGEN_RETURN(false);
20737break;
20738case 1:
20739OPGEN_RETURN(false);
20740break;
20741case 2:
20742OPGEN_RETURN(false);
20743break;
20744default:
20745break;
20746}
20747break;
20748case Opcode::Urshift32:
20749switch (argIndex) {
20750case 0:
20751OPGEN_RETURN(false);
20752break;
20753case 1:
20754OPGEN_RETURN(false);
20755break;
20756case 2:
20757OPGEN_RETURN(false);
20758break;
20759default:
20760break;
20761}
20762break;
20763case Opcode::Urshift64:
20764switch (argIndex) {
20765case 0:
20766OPGEN_RETURN(false);
20767break;
20768case 1:
20769OPGEN_RETURN(false);
20770break;
20771case 2:
20772OPGEN_RETURN(false);
20773break;
20774default:
20775break;
20776}
20777break;
20778case Opcode::RotateRight32:
20779switch (argIndex) {
20780case 0:
20781OPGEN_RETURN(false);
20782break;
20783case 1:
20784OPGEN_RETURN(false);
20785break;
20786case 2:
20787OPGEN_RETURN(false);
20788break;
20789default:
20790break;
20791}
20792break;
20793case Opcode::RotateRight64:
20794switch (argIndex) {
20795case 0:
20796OPGEN_RETURN(false);
20797break;
20798case 1:
20799OPGEN_RETURN(false);
20800break;
20801case 2:
20802OPGEN_RETURN(false);
20803break;
20804default:
20805break;
20806}
20807break;
20808case Opcode::RotateLeft32:
20809switch (argIndex) {
20810case 0:
20811OPGEN_RETURN(false);
20812break;
20813case 1:
20814OPGEN_RETURN(false);
20815break;
20816default:
20817break;
20818}
20819break;
20820case Opcode::RotateLeft64:
20821switch (argIndex) {
20822case 0:
20823OPGEN_RETURN(false);
20824break;
20825case 1:
20826OPGEN_RETURN(false);
20827break;
20828default:
20829break;
20830}
20831break;
20832case Opcode::Or32:
20833switch (argIndex) {
20834case 0:
20835switch (args.size()) {
20836case 3:
20837switch (Arg::Addr) {
20838case Arg::Tmp:
20839break;
20840case Arg::BitImm:
20841break;
20842case Arg::Addr:
20843case Arg::Stack:
20844case Arg::CallArg:
20845switch (args[1].kind()) {
20846case Arg::Tmp:
20847switch (args[2].kind()) {
20848case Arg::Tmp:
20849#if CPU(X86) || CPU(X86_64)
20850OPGEN_RETURN(true);
20851#endif
20852break;
20853break;
20854default:
20855break;
20856}
20857break;
20858default:
20859break;
20860}
20861break;
20862default:
20863break;
20864}
20865break;
20866case 2:
20867switch (Arg::Addr) {
20868case Arg::Tmp:
20869break;
20870case Arg::Imm:
20871break;
20872case Arg::Addr:
20873case Arg::Stack:
20874case Arg::CallArg:
20875switch (args[1].kind()) {
20876case Arg::Tmp:
20877#if CPU(X86) || CPU(X86_64)
20878OPGEN_RETURN(true);
20879#endif
20880break;
20881break;
20882default:
20883break;
20884}
20885break;
20886case Arg::Index:
20887break;
20888default:
20889break;
20890}
20891break;
20892default:
20893break;
20894}
20895break;
20896case 1:
20897switch (args.size()) {
20898case 3:
20899switch (args[0].kind()) {
20900case Arg::Tmp:
20901switch (Arg::Addr) {
20902case Arg::Tmp:
20903break;
20904case Arg::Addr:
20905case Arg::Stack:
20906case Arg::CallArg:
20907switch (args[2].kind()) {
20908case Arg::Tmp:
20909#if CPU(X86) || CPU(X86_64)
20910OPGEN_RETURN(true);
20911#endif
20912break;
20913break;
20914default:
20915break;
20916}
20917break;
20918default:
20919break;
20920}
20921break;
20922case Arg::BitImm:
20923break;
20924case Arg::Addr:
20925case Arg::Stack:
20926case Arg::CallArg:
20927break;
20928default:
20929break;
20930}
20931break;
20932case 2:
20933switch (args[0].kind()) {
20934case Arg::Tmp:
20935switch (Arg::Addr) {
20936case Arg::Tmp:
20937break;
20938case Arg::Addr:
20939case Arg::Stack:
20940case Arg::CallArg:
20941#if CPU(X86) || CPU(X86_64)
20942OPGEN_RETURN(true);
20943#endif
20944break;
20945break;
20946case Arg::Index:
20947break;
20948default:
20949break;
20950}
20951break;
20952case Arg::Imm:
20953switch (Arg::Addr) {
20954case Arg::Tmp:
20955break;
20956case Arg::Addr:
20957case Arg::Stack:
20958case Arg::CallArg:
20959#if CPU(X86) || CPU(X86_64)
20960OPGEN_RETURN(true);
20961#endif
20962break;
20963break;
20964case Arg::Index:
20965break;
20966default:
20967break;
20968}
20969break;
20970case Arg::Addr:
20971case Arg::Stack:
20972case Arg::CallArg:
20973break;
20974case Arg::Index:
20975break;
20976default:
20977break;
20978}
20979break;
20980default:
20981break;
20982}
20983break;
20984case 2:
20985OPGEN_RETURN(false);
20986break;
20987default:
20988break;
20989}
20990break;
20991case Opcode::Or64:
20992switch (argIndex) {
20993case 0:
20994switch (args.size()) {
20995case 2:
20996switch (Arg::Addr) {
20997case Arg::Tmp:
20998break;
20999case Arg::Imm:
21000break;
21001case Arg::Addr:
21002case Arg::Stack:
21003case Arg::CallArg:
21004switch (args[1].kind()) {
21005case Arg::Tmp:
21006#if CPU(X86_64)
21007OPGEN_RETURN(true);
21008#endif
21009break;
21010break;
21011default:
21012break;
21013}
21014break;
21015case Arg::Index:
21016break;
21017default:
21018break;
21019}
21020break;
21021default:
21022break;
21023}
21024break;
21025case 1:
21026switch (args.size()) {
21027case 2:
21028switch (args[0].kind()) {
21029case Arg::Tmp:
21030switch (Arg::Addr) {
21031case Arg::Tmp:
21032break;
21033case Arg::Addr:
21034case Arg::Stack:
21035case Arg::CallArg:
21036#if CPU(X86_64)
21037OPGEN_RETURN(true);
21038#endif
21039break;
21040break;
21041case Arg::Index:
21042break;
21043default:
21044break;
21045}
21046break;
21047case Arg::Imm:
21048switch (Arg::Addr) {
21049case Arg::Tmp:
21050break;
21051case Arg::Addr:
21052case Arg::Stack:
21053case Arg::CallArg:
21054#if CPU(X86_64)
21055OPGEN_RETURN(true);
21056#endif
21057break;
21058break;
21059case Arg::Index:
21060break;
21061default:
21062break;
21063}
21064break;
21065case Arg::Addr:
21066case Arg::Stack:
21067case Arg::CallArg:
21068break;
21069case Arg::Index:
21070break;
21071default:
21072break;
21073}
21074break;
21075default:
21076break;
21077}
21078break;
21079case 2:
21080OPGEN_RETURN(false);
21081break;
21082default:
21083break;
21084}
21085break;
21086case Opcode::Xor32:
21087switch (argIndex) {
21088case 0:
21089switch (args.size()) {
21090case 3:
21091switch (Arg::Addr) {
21092case Arg::Tmp:
21093break;
21094case Arg::BitImm:
21095break;
21096case Arg::Addr:
21097case Arg::Stack:
21098case Arg::CallArg:
21099switch (args[1].kind()) {
21100case Arg::Tmp:
21101switch (args[2].kind()) {
21102case Arg::Tmp:
21103#if CPU(X86) || CPU(X86_64)
21104OPGEN_RETURN(true);
21105#endif
21106break;
21107break;
21108default:
21109break;
21110}
21111break;
21112default:
21113break;
21114}
21115break;
21116default:
21117break;
21118}
21119break;
21120case 2:
21121switch (Arg::Addr) {
21122case Arg::Tmp:
21123break;
21124case Arg::Imm:
21125break;
21126case Arg::Addr:
21127case Arg::Stack:
21128case Arg::CallArg:
21129switch (args[1].kind()) {
21130case Arg::Tmp:
21131#if CPU(X86) || CPU(X86_64)
21132OPGEN_RETURN(true);
21133#endif
21134break;
21135break;
21136default:
21137break;
21138}
21139break;
21140case Arg::Index:
21141break;
21142default:
21143break;
21144}
21145break;
21146default:
21147break;
21148}
21149break;
21150case 1:
21151switch (args.size()) {
21152case 3:
21153switch (args[0].kind()) {
21154case Arg::Tmp:
21155switch (Arg::Addr) {
21156case Arg::Tmp:
21157break;
21158case Arg::Addr:
21159case Arg::Stack:
21160case Arg::CallArg:
21161switch (args[2].kind()) {
21162case Arg::Tmp:
21163#if CPU(X86) || CPU(X86_64)
21164OPGEN_RETURN(true);
21165#endif
21166break;
21167break;
21168default:
21169break;
21170}
21171break;
21172default:
21173break;
21174}
21175break;
21176case Arg::BitImm:
21177break;
21178case Arg::Addr:
21179case Arg::Stack:
21180case Arg::CallArg:
21181break;
21182default:
21183break;
21184}
21185break;
21186case 2:
21187switch (args[0].kind()) {
21188case Arg::Tmp:
21189switch (Arg::Addr) {
21190case Arg::Tmp:
21191break;
21192case Arg::Addr:
21193case Arg::Stack:
21194case Arg::CallArg:
21195#if CPU(X86) || CPU(X86_64)
21196OPGEN_RETURN(true);
21197#endif
21198break;
21199break;
21200case Arg::Index:
21201break;
21202default:
21203break;
21204}
21205break;
21206case Arg::Imm:
21207switch (Arg::Addr) {
21208case Arg::Tmp:
21209break;
21210case Arg::Addr:
21211case Arg::Stack:
21212case Arg::CallArg:
21213#if CPU(X86) || CPU(X86_64)
21214OPGEN_RETURN(true);
21215#endif
21216break;
21217break;
21218case Arg::Index:
21219break;
21220default:
21221break;
21222}
21223break;
21224case Arg::Addr:
21225case Arg::Stack:
21226case Arg::CallArg:
21227break;
21228case Arg::Index:
21229break;
21230default:
21231break;
21232}
21233break;
21234default:
21235break;
21236}
21237break;
21238case 2:
21239OPGEN_RETURN(false);
21240break;
21241default:
21242break;
21243}
21244break;
21245case Opcode::Xor64:
21246switch (argIndex) {
21247case 0:
21248switch (args.size()) {
21249case 2:
21250switch (Arg::Addr) {
21251case Arg::Tmp:
21252break;
21253case Arg::Addr:
21254case Arg::Stack:
21255case Arg::CallArg:
21256switch (args[1].kind()) {
21257case Arg::Tmp:
21258#if CPU(X86_64)
21259OPGEN_RETURN(true);
21260#endif
21261break;
21262break;
21263default:
21264break;
21265}
21266break;
21267case Arg::Index:
21268break;
21269case Arg::Imm:
21270break;
21271default:
21272break;
21273}
21274break;
21275default:
21276break;
21277}
21278break;
21279case 1:
21280switch (args.size()) {
21281case 2:
21282switch (args[0].kind()) {
21283case Arg::Tmp:
21284switch (Arg::Addr) {
21285case Arg::Tmp:
21286break;
21287case Arg::Addr:
21288case Arg::Stack:
21289case Arg::CallArg:
21290#if CPU(X86_64)
21291OPGEN_RETURN(true);
21292#endif
21293break;
21294break;
21295case Arg::Index:
21296break;
21297default:
21298break;
21299}
21300break;
21301case Arg::Addr:
21302case Arg::Stack:
21303case Arg::CallArg:
21304break;
21305case Arg::Index:
21306break;
21307case Arg::Imm:
21308switch (Arg::Addr) {
21309case Arg::Addr:
21310case Arg::Stack:
21311case Arg::CallArg:
21312#if CPU(X86_64)
21313OPGEN_RETURN(true);
21314#endif
21315break;
21316break;
21317case Arg::Index:
21318break;
21319case Arg::Tmp:
21320break;
21321default:
21322break;
21323}
21324break;
21325default:
21326break;
21327}
21328break;
21329default:
21330break;
21331}
21332break;
21333case 2:
21334OPGEN_RETURN(false);
21335break;
21336default:
21337break;
21338}
21339break;
21340case Opcode::Not32:
21341switch (argIndex) {
21342case 0:
21343switch (args.size()) {
21344case 1:
21345switch (Arg::Addr) {
21346case Arg::Tmp:
21347break;
21348case Arg::Addr:
21349case Arg::Stack:
21350case Arg::CallArg:
21351#if CPU(X86) || CPU(X86_64)
21352OPGEN_RETURN(true);
21353#endif
21354break;
21355break;
21356case Arg::Index:
21357break;
21358default:
21359break;
21360}
21361break;
21362default:
21363break;
21364}
21365break;
21366case 1:
21367OPGEN_RETURN(false);
21368break;
21369default:
21370break;
21371}
21372break;
21373case Opcode::Not64:
21374switch (argIndex) {
21375case 0:
21376switch (args.size()) {
21377case 1:
21378switch (Arg::Addr) {
21379case Arg::Tmp:
21380break;
21381case Arg::Addr:
21382case Arg::Stack:
21383case Arg::CallArg:
21384#if CPU(X86_64)
21385OPGEN_RETURN(true);
21386#endif
21387break;
21388break;
21389case Arg::Index:
21390break;
21391default:
21392break;
21393}
21394break;
21395default:
21396break;
21397}
21398break;
21399case 1:
21400OPGEN_RETURN(false);
21401break;
21402default:
21403break;
21404}
21405break;
21406case Opcode::AbsDouble:
21407switch (argIndex) {
21408case 0:
21409OPGEN_RETURN(false);
21410break;
21411case 1:
21412OPGEN_RETURN(false);
21413break;
21414default:
21415break;
21416}
21417break;
21418case Opcode::AbsFloat:
21419switch (argIndex) {
21420case 0:
21421OPGEN_RETURN(false);
21422break;
21423case 1:
21424OPGEN_RETURN(false);
21425break;
21426default:
21427break;
21428}
21429break;
21430case Opcode::CeilDouble:
21431switch (argIndex) {
21432case 0:
21433switch (Arg::Addr) {
21434case Arg::Tmp:
21435break;
21436case Arg::Addr:
21437case Arg::Stack:
21438case Arg::CallArg:
21439switch (args[1].kind()) {
21440case Arg::Tmp:
21441#if CPU(X86) || CPU(X86_64)
21442OPGEN_RETURN(true);
21443#endif
21444break;
21445break;
21446default:
21447break;
21448}
21449break;
21450default:
21451break;
21452}
21453break;
21454case 1:
21455OPGEN_RETURN(false);
21456break;
21457default:
21458break;
21459}
21460break;
21461case Opcode::CeilFloat:
21462switch (argIndex) {
21463case 0:
21464switch (Arg::Addr) {
21465case Arg::Tmp:
21466break;
21467case Arg::Addr:
21468case Arg::Stack:
21469case Arg::CallArg:
21470switch (args[1].kind()) {
21471case Arg::Tmp:
21472#if CPU(X86) || CPU(X86_64)
21473OPGEN_RETURN(true);
21474#endif
21475break;
21476break;
21477default:
21478break;
21479}
21480break;
21481default:
21482break;
21483}
21484break;
21485case 1:
21486OPGEN_RETURN(false);
21487break;
21488default:
21489break;
21490}
21491break;
21492case Opcode::FloorDouble:
21493switch (argIndex) {
21494case 0:
21495switch (Arg::Addr) {
21496case Arg::Tmp:
21497break;
21498case Arg::Addr:
21499case Arg::Stack:
21500case Arg::CallArg:
21501switch (args[1].kind()) {
21502case Arg::Tmp:
21503#if CPU(X86) || CPU(X86_64)
21504OPGEN_RETURN(true);
21505#endif
21506break;
21507break;
21508default:
21509break;
21510}
21511break;
21512default:
21513break;
21514}
21515break;
21516case 1:
21517OPGEN_RETURN(false);
21518break;
21519default:
21520break;
21521}
21522break;
21523case Opcode::FloorFloat:
21524switch (argIndex) {
21525case 0:
21526switch (Arg::Addr) {
21527case Arg::Tmp:
21528break;
21529case Arg::Addr:
21530case Arg::Stack:
21531case Arg::CallArg:
21532switch (args[1].kind()) {
21533case Arg::Tmp:
21534#if CPU(X86) || CPU(X86_64)
21535OPGEN_RETURN(true);
21536#endif
21537break;
21538break;
21539default:
21540break;
21541}
21542break;
21543default:
21544break;
21545}
21546break;
21547case 1:
21548OPGEN_RETURN(false);
21549break;
21550default:
21551break;
21552}
21553break;
21554case Opcode::SqrtDouble:
21555switch (argIndex) {
21556case 0:
21557switch (Arg::Addr) {
21558case Arg::Tmp:
21559break;
21560case Arg::Addr:
21561case Arg::Stack:
21562case Arg::CallArg:
21563switch (args[1].kind()) {
21564case Arg::Tmp:
21565#if CPU(X86) || CPU(X86_64)
21566OPGEN_RETURN(true);
21567#endif
21568break;
21569break;
21570default:
21571break;
21572}
21573break;
21574default:
21575break;
21576}
21577break;
21578case 1:
21579OPGEN_RETURN(false);
21580break;
21581default:
21582break;
21583}
21584break;
21585case Opcode::SqrtFloat:
21586switch (argIndex) {
21587case 0:
21588switch (Arg::Addr) {
21589case Arg::Tmp:
21590break;
21591case Arg::Addr:
21592case Arg::Stack:
21593case Arg::CallArg:
21594switch (args[1].kind()) {
21595case Arg::Tmp:
21596#if CPU(X86) || CPU(X86_64)
21597OPGEN_RETURN(true);
21598#endif
21599break;
21600break;
21601default:
21602break;
21603}
21604break;
21605default:
21606break;
21607}
21608break;
21609case 1:
21610OPGEN_RETURN(false);
21611break;
21612default:
21613break;
21614}
21615break;
21616case Opcode::ConvertInt32ToDouble:
21617switch (argIndex) {
21618case 0:
21619switch (Arg::Addr) {
21620case Arg::Tmp:
21621break;
21622case Arg::Addr:
21623case Arg::Stack:
21624case Arg::CallArg:
21625switch (args[1].kind()) {
21626case Arg::Tmp:
21627#if CPU(X86) || CPU(X86_64)
21628OPGEN_RETURN(true);
21629#endif
21630break;
21631break;
21632default:
21633break;
21634}
21635break;
21636default:
21637break;
21638}
21639break;
21640case 1:
21641OPGEN_RETURN(false);
21642break;
21643default:
21644break;
21645}
21646break;
21647case Opcode::ConvertInt64ToDouble:
21648switch (argIndex) {
21649case 0:
21650switch (Arg::Addr) {
21651case Arg::Tmp:
21652break;
21653case Arg::Addr:
21654case Arg::Stack:
21655case Arg::CallArg:
21656switch (args[1].kind()) {
21657case Arg::Tmp:
21658#if CPU(X86_64)
21659OPGEN_RETURN(true);
21660#endif
21661break;
21662break;
21663default:
21664break;
21665}
21666break;
21667default:
21668break;
21669}
21670break;
21671case 1:
21672OPGEN_RETURN(false);
21673break;
21674default:
21675break;
21676}
21677break;
21678case Opcode::ConvertInt32ToFloat:
21679switch (argIndex) {
21680case 0:
21681switch (Arg::Addr) {
21682case Arg::Tmp:
21683break;
21684case Arg::Addr:
21685case Arg::Stack:
21686case Arg::CallArg:
21687switch (args[1].kind()) {
21688case Arg::Tmp:
21689#if CPU(X86) || CPU(X86_64)
21690OPGEN_RETURN(true);
21691#endif
21692break;
21693break;
21694default:
21695break;
21696}
21697break;
21698default:
21699break;
21700}
21701break;
21702case 1:
21703OPGEN_RETURN(false);
21704break;
21705default:
21706break;
21707}
21708break;
21709case Opcode::ConvertInt64ToFloat:
21710switch (argIndex) {
21711case 0:
21712switch (Arg::Addr) {
21713case Arg::Tmp:
21714break;
21715case Arg::Addr:
21716case Arg::Stack:
21717case Arg::CallArg:
21718switch (args[1].kind()) {
21719case Arg::Tmp:
21720#if CPU(X86_64)
21721OPGEN_RETURN(true);
21722#endif
21723break;
21724break;
21725default:
21726break;
21727}
21728break;
21729default:
21730break;
21731}
21732break;
21733case 1:
21734OPGEN_RETURN(false);
21735break;
21736default:
21737break;
21738}
21739break;
21740case Opcode::CountLeadingZeros32:
21741switch (argIndex) {
21742case 0:
21743switch (Arg::Addr) {
21744case Arg::Tmp:
21745break;
21746case Arg::Addr:
21747case Arg::Stack:
21748case Arg::CallArg:
21749switch (args[1].kind()) {
21750case Arg::Tmp:
21751#if CPU(X86) || CPU(X86_64)
21752OPGEN_RETURN(true);
21753#endif
21754break;
21755break;
21756default:
21757break;
21758}
21759break;
21760default:
21761break;
21762}
21763break;
21764case 1:
21765OPGEN_RETURN(false);
21766break;
21767default:
21768break;
21769}
21770break;
21771case Opcode::CountLeadingZeros64:
21772switch (argIndex) {
21773case 0:
21774switch (Arg::Addr) {
21775case Arg::Tmp:
21776break;
21777case Arg::Addr:
21778case Arg::Stack:
21779case Arg::CallArg:
21780switch (args[1].kind()) {
21781case Arg::Tmp:
21782#if CPU(X86_64)
21783OPGEN_RETURN(true);
21784#endif
21785break;
21786break;
21787default:
21788break;
21789}
21790break;
21791default:
21792break;
21793}
21794break;
21795case 1:
21796OPGEN_RETURN(false);
21797break;
21798default:
21799break;
21800}
21801break;
21802case Opcode::ConvertDoubleToFloat:
21803switch (argIndex) {
21804case 0:
21805switch (Arg::Addr) {
21806case Arg::Tmp:
21807break;
21808case Arg::Addr:
21809case Arg::Stack:
21810case Arg::CallArg:
21811switch (args[1].kind()) {
21812case Arg::Tmp:
21813#if CPU(X86) || CPU(X86_64)
21814OPGEN_RETURN(true);
21815#endif
21816break;
21817break;
21818default:
21819break;
21820}
21821break;
21822default:
21823break;
21824}
21825break;
21826case 1:
21827OPGEN_RETURN(false);
21828break;
21829default:
21830break;
21831}
21832break;
21833case Opcode::ConvertFloatToDouble:
21834switch (argIndex) {
21835case 0:
21836switch (Arg::Addr) {
21837case Arg::Tmp:
21838break;
21839case Arg::Addr:
21840case Arg::Stack:
21841case Arg::CallArg:
21842switch (args[1].kind()) {
21843case Arg::Tmp:
21844#if CPU(X86) || CPU(X86_64)
21845OPGEN_RETURN(true);
21846#endif
21847break;
21848break;
21849default:
21850break;
21851}
21852break;
21853default:
21854break;
21855}
21856break;
21857case 1:
21858OPGEN_RETURN(false);
21859break;
21860default:
21861break;
21862}
21863break;
21864case Opcode::Move:
21865switch (argIndex) {
21866case 0:
21867switch (args.size()) {
21868case 2:
21869switch (Arg::Addr) {
21870case Arg::Tmp:
21871break;
21872case Arg::Imm:
21873break;
21874#if USE(JSVALUE64)
21875case Arg::BigImm:
21876break;
21877#endif // USE(JSVALUE64)
21878case Arg::Addr:
21879case Arg::Stack:
21880case Arg::CallArg:
21881switch (args[1].kind()) {
21882case Arg::Tmp:
21883OPGEN_RETURN(true);
21884break;
21885break;
21886default:
21887break;
21888}
21889break;
21890case Arg::Index:
21891break;
21892default:
21893break;
21894}
21895break;
21896case 3:
21897OPGEN_RETURN(true);
21898break;
21899default:
21900break;
21901}
21902break;
21903case 1:
21904switch (args.size()) {
21905case 2:
21906switch (args[0].kind()) {
21907case Arg::Tmp:
21908switch (Arg::Addr) {
21909case Arg::Tmp:
21910break;
21911case Arg::Addr:
21912case Arg::Stack:
21913case Arg::CallArg:
21914OPGEN_RETURN(true);
21915break;
21916break;
21917case Arg::Index:
21918break;
21919default:
21920break;
21921}
21922break;
21923case Arg::Imm:
21924switch (Arg::Addr) {
21925case Arg::Tmp:
21926break;
21927case Arg::Addr:
21928case Arg::Stack:
21929case Arg::CallArg:
21930#if CPU(X86) || CPU(X86_64)
21931OPGEN_RETURN(true);
21932#endif
21933break;
21934break;
21935default:
21936break;
21937}
21938break;
21939#if USE(JSVALUE64)
21940case Arg::BigImm:
21941break;
21942#endif // USE(JSVALUE64)
21943case Arg::Addr:
21944case Arg::Stack:
21945case Arg::CallArg:
21946break;
21947case Arg::Index:
21948break;
21949default:
21950break;
21951}
21952break;
21953case 3:
21954OPGEN_RETURN(true);
21955break;
21956default:
21957break;
21958}
21959break;
21960case 2:
21961OPGEN_RETURN(false);
21962break;
21963default:
21964break;
21965}
21966break;
21967case Opcode::Swap32:
21968switch (argIndex) {
21969case 0:
21970OPGEN_RETURN(false);
21971break;
21972case 1:
21973switch (args[0].kind()) {
21974case Arg::Tmp:
21975switch (Arg::Addr) {
21976case Arg::Tmp:
21977break;
21978case Arg::Addr:
21979case Arg::Stack:
21980case Arg::CallArg:
21981#if CPU(X86) || CPU(X86_64)
21982OPGEN_RETURN(true);
21983#endif
21984break;
21985break;
21986default:
21987break;
21988}
21989break;
21990default:
21991break;
21992}
21993break;
21994default:
21995break;
21996}
21997break;
21998case Opcode::Swap64:
21999switch (argIndex) {
22000case 0:
22001OPGEN_RETURN(false);
22002break;
22003case 1:
22004switch (args[0].kind()) {
22005case Arg::Tmp:
22006switch (Arg::Addr) {
22007case Arg::Tmp:
22008break;
22009case Arg::Addr:
22010case Arg::Stack:
22011case Arg::CallArg:
22012#if CPU(X86_64)
22013OPGEN_RETURN(true);
22014#endif
22015break;
22016break;
22017default:
22018break;
22019}
22020break;
22021default:
22022break;
22023}
22024break;
22025default:
22026break;
22027}
22028break;
22029case Opcode::Move32:
22030switch (argIndex) {
22031case 0:
22032switch (args.size()) {
22033case 2:
22034switch (Arg::Addr) {
22035case Arg::Tmp:
22036break;
22037case Arg::Addr:
22038case Arg::Stack:
22039case Arg::CallArg:
22040switch (args[1].kind()) {
22041case Arg::Tmp:
22042OPGEN_RETURN(true);
22043break;
22044break;
22045default:
22046break;
22047}
22048break;
22049case Arg::Index:
22050break;
22051case Arg::Imm:
22052break;
22053default:
22054break;
22055}
22056break;
22057case 3:
22058OPGEN_RETURN(true);
22059break;
22060default:
22061break;
22062}
22063break;
22064case 1:
22065switch (args.size()) {
22066case 2:
22067switch (args[0].kind()) {
22068case Arg::Tmp:
22069switch (Arg::Addr) {
22070case Arg::Tmp:
22071break;
22072case Arg::Addr:
22073case Arg::Stack:
22074case Arg::CallArg:
22075OPGEN_RETURN(true);
22076break;
22077break;
22078case Arg::Index:
22079break;
22080default:
22081break;
22082}
22083break;
22084case Arg::Addr:
22085case Arg::Stack:
22086case Arg::CallArg:
22087break;
22088case Arg::Index:
22089break;
22090case Arg::Imm:
22091switch (Arg::Addr) {
22092case Arg::Tmp:
22093break;
22094case Arg::Addr:
22095case Arg::Stack:
22096case Arg::CallArg:
22097#if CPU(X86) || CPU(X86_64)
22098OPGEN_RETURN(true);
22099#endif
22100break;
22101break;
22102case Arg::Index:
22103break;
22104default:
22105break;
22106}
22107break;
22108default:
22109break;
22110}
22111break;
22112case 3:
22113OPGEN_RETURN(true);
22114break;
22115default:
22116break;
22117}
22118break;
22119case 2:
22120OPGEN_RETURN(false);
22121break;
22122default:
22123break;
22124}
22125break;
22126case Opcode::StoreZero32:
22127switch (argIndex) {
22128case 0:
22129switch (Arg::Addr) {
22130case Arg::Addr:
22131case Arg::Stack:
22132case Arg::CallArg:
22133OPGEN_RETURN(true);
22134break;
22135break;
22136case Arg::Index:
22137break;
22138default:
22139break;
22140}
22141break;
22142default:
22143break;
22144}
22145break;
22146case Opcode::StoreZero64:
22147switch (argIndex) {
22148case 0:
22149switch (Arg::Addr) {
22150case Arg::Addr:
22151case Arg::Stack:
22152case Arg::CallArg:
22153#if CPU(X86_64) || CPU(ARM64)
22154OPGEN_RETURN(true);
22155#endif
22156break;
22157break;
22158case Arg::Index:
22159break;
22160default:
22161break;
22162}
22163break;
22164default:
22165break;
22166}
22167break;
22168case Opcode::SignExtend32ToPtr:
22169switch (argIndex) {
22170case 0:
22171OPGEN_RETURN(false);
22172break;
22173case 1:
22174OPGEN_RETURN(false);
22175break;
22176default:
22177break;
22178}
22179break;
22180case Opcode::ZeroExtend8To32:
22181switch (argIndex) {
22182case 0:
22183switch (Arg::Addr) {
22184case Arg::Tmp:
22185break;
22186case Arg::Addr:
22187case Arg::Stack:
22188case Arg::CallArg:
22189switch (args[1].kind()) {
22190case Arg::Tmp:
22191#if CPU(X86) || CPU(X86_64)
22192OPGEN_RETURN(true);
22193#endif
22194break;
22195break;
22196default:
22197break;
22198}
22199break;
22200case Arg::Index:
22201break;
22202default:
22203break;
22204}
22205break;
22206case 1:
22207OPGEN_RETURN(false);
22208break;
22209default:
22210break;
22211}
22212break;
22213case Opcode::SignExtend8To32:
22214switch (argIndex) {
22215case 0:
22216switch (Arg::Addr) {
22217case Arg::Tmp:
22218break;
22219case Arg::Addr:
22220case Arg::Stack:
22221case Arg::CallArg:
22222switch (args[1].kind()) {
22223case Arg::Tmp:
22224#if CPU(X86) || CPU(X86_64)
22225OPGEN_RETURN(true);
22226#endif
22227break;
22228break;
22229default:
22230break;
22231}
22232break;
22233case Arg::Index:
22234break;
22235default:
22236break;
22237}
22238break;
22239case 1:
22240OPGEN_RETURN(false);
22241break;
22242default:
22243break;
22244}
22245break;
22246case Opcode::ZeroExtend16To32:
22247switch (argIndex) {
22248case 0:
22249switch (Arg::Addr) {
22250case Arg::Tmp:
22251break;
22252case Arg::Addr:
22253case Arg::Stack:
22254case Arg::CallArg:
22255switch (args[1].kind()) {
22256case Arg::Tmp:
22257#if CPU(X86) || CPU(X86_64)
22258OPGEN_RETURN(true);
22259#endif
22260break;
22261break;
22262default:
22263break;
22264}
22265break;
22266case Arg::Index:
22267break;
22268default:
22269break;
22270}
22271break;
22272case 1:
22273OPGEN_RETURN(false);
22274break;
22275default:
22276break;
22277}
22278break;
22279case Opcode::SignExtend16To32:
22280switch (argIndex) {
22281case 0:
22282switch (Arg::Addr) {
22283case Arg::Tmp:
22284break;
22285case Arg::Addr:
22286case Arg::Stack:
22287case Arg::CallArg:
22288switch (args[1].kind()) {
22289case Arg::Tmp:
22290#if CPU(X86) || CPU(X86_64)
22291OPGEN_RETURN(true);
22292#endif
22293break;
22294break;
22295default:
22296break;
22297}
22298break;
22299case Arg::Index:
22300break;
22301default:
22302break;
22303}
22304break;
22305case 1:
22306OPGEN_RETURN(false);
22307break;
22308default:
22309break;
22310}
22311break;
22312case Opcode::MoveFloat:
22313switch (argIndex) {
22314case 0:
22315switch (args.size()) {
22316case 2:
22317switch (Arg::Addr) {
22318case Arg::Tmp:
22319break;
22320case Arg::Addr:
22321case Arg::Stack:
22322case Arg::CallArg:
22323switch (args[1].kind()) {
22324case Arg::Tmp:
22325OPGEN_RETURN(true);
22326break;
22327break;
22328default:
22329break;
22330}
22331break;
22332case Arg::Index:
22333break;
22334default:
22335break;
22336}
22337break;
22338case 3:
22339OPGEN_RETURN(true);
22340break;
22341default:
22342break;
22343}
22344break;
22345case 1:
22346switch (args.size()) {
22347case 2:
22348switch (args[0].kind()) {
22349case Arg::Tmp:
22350switch (Arg::Addr) {
22351case Arg::Tmp:
22352break;
22353case Arg::Addr:
22354case Arg::Stack:
22355case Arg::CallArg:
22356OPGEN_RETURN(true);
22357break;
22358break;
22359case Arg::Index:
22360break;
22361default:
22362break;
22363}
22364break;
22365case Arg::Addr:
22366case Arg::Stack:
22367case Arg::CallArg:
22368break;
22369case Arg::Index:
22370break;
22371default:
22372break;
22373}
22374break;
22375case 3:
22376OPGEN_RETURN(true);
22377break;
22378default:
22379break;
22380}
22381break;
22382case 2:
22383OPGEN_RETURN(false);
22384break;
22385default:
22386break;
22387}
22388break;
22389case Opcode::MoveDouble:
22390switch (argIndex) {
22391case 0:
22392switch (args.size()) {
22393case 2:
22394switch (Arg::Addr) {
22395case Arg::Tmp:
22396break;
22397case Arg::Addr:
22398case Arg::Stack:
22399case Arg::CallArg:
22400switch (args[1].kind()) {
22401case Arg::Tmp:
22402OPGEN_RETURN(true);
22403break;
22404break;
22405default:
22406break;
22407}
22408break;
22409case Arg::Index:
22410break;
22411default:
22412break;
22413}
22414break;
22415case 3:
22416OPGEN_RETURN(true);
22417break;
22418default:
22419break;
22420}
22421break;
22422case 1:
22423switch (args.size()) {
22424case 2:
22425switch (args[0].kind()) {
22426case Arg::Tmp:
22427switch (Arg::Addr) {
22428case Arg::Tmp:
22429break;
22430case Arg::Addr:
22431case Arg::Stack:
22432case Arg::CallArg:
22433OPGEN_RETURN(true);
22434break;
22435break;
22436case Arg::Index:
22437break;
22438default:
22439break;
22440}
22441break;
22442case Arg::Addr:
22443case Arg::Stack:
22444case Arg::CallArg:
22445break;
22446case Arg::Index:
22447break;
22448default:
22449break;
22450}
22451break;
22452case 3:
22453OPGEN_RETURN(true);
22454break;
22455default:
22456break;
22457}
22458break;
22459case 2:
22460OPGEN_RETURN(false);
22461break;
22462default:
22463break;
22464}
22465break;
22466case Opcode::MoveZeroToDouble:
22467switch (argIndex) {
22468case 0:
22469OPGEN_RETURN(false);
22470break;
22471default:
22472break;
22473}
22474break;
22475case Opcode::Move64ToDouble:
22476switch (argIndex) {
22477case 0:
22478switch (Arg::Addr) {
22479case Arg::Tmp:
22480break;
22481case Arg::Addr:
22482case Arg::Stack:
22483case Arg::CallArg:
22484switch (args[1].kind()) {
22485case Arg::Tmp:
22486#if CPU(X86_64)
22487OPGEN_RETURN(true);
22488#endif
22489break;
22490break;
22491default:
22492break;
22493}
22494break;
22495case Arg::Index:
22496break;
22497default:
22498break;
22499}
22500break;
22501case 1:
22502OPGEN_RETURN(false);
22503break;
22504default:
22505break;
22506}
22507break;
22508case Opcode::Move32ToFloat:
22509switch (argIndex) {
22510case 0:
22511switch (Arg::Addr) {
22512case Arg::Tmp:
22513break;
22514case Arg::Addr:
22515case Arg::Stack:
22516case Arg::CallArg:
22517switch (args[1].kind()) {
22518case Arg::Tmp:
22519#if CPU(X86) || CPU(X86_64)
22520OPGEN_RETURN(true);
22521#endif
22522break;
22523break;
22524default:
22525break;
22526}
22527break;
22528case Arg::Index:
22529break;
22530default:
22531break;
22532}
22533break;
22534case 1:
22535OPGEN_RETURN(false);
22536break;
22537default:
22538break;
22539}
22540break;
22541case Opcode::MoveDoubleTo64:
22542switch (argIndex) {
22543case 0:
22544switch (Arg::Addr) {
22545case Arg::Tmp:
22546break;
22547case Arg::Addr:
22548case Arg::Stack:
22549case Arg::CallArg:
22550switch (args[1].kind()) {
22551case Arg::Tmp:
22552#if CPU(X86_64) || CPU(ARM64)
22553OPGEN_RETURN(true);
22554#endif
22555break;
22556break;
22557default:
22558break;
22559}
22560break;
22561case Arg::Index:
22562break;
22563default:
22564break;
22565}
22566break;
22567case 1:
22568OPGEN_RETURN(false);
22569break;
22570default:
22571break;
22572}
22573break;
22574case Opcode::MoveFloatTo32:
22575switch (argIndex) {
22576case 0:
22577switch (Arg::Addr) {
22578case Arg::Tmp:
22579break;
22580case Arg::Addr:
22581case Arg::Stack:
22582case Arg::CallArg:
22583switch (args[1].kind()) {
22584case Arg::Tmp:
22585OPGEN_RETURN(true);
22586break;
22587break;
22588default:
22589break;
22590}
22591break;
22592case Arg::Index:
22593break;
22594default:
22595break;
22596}
22597break;
22598case 1:
22599OPGEN_RETURN(false);
22600break;
22601default:
22602break;
22603}
22604break;
22605case Opcode::Load8:
22606switch (argIndex) {
22607case 0:
22608switch (Arg::Addr) {
22609case Arg::Addr:
22610case Arg::Stack:
22611case Arg::CallArg:
22612switch (args[1].kind()) {
22613case Arg::Tmp:
22614OPGEN_RETURN(true);
22615break;
22616break;
22617default:
22618break;
22619}
22620break;
22621case Arg::Index:
22622break;
22623default:
22624break;
22625}
22626break;
22627case 1:
22628OPGEN_RETURN(false);
22629break;
22630default:
22631break;
22632}
22633break;
22634case Opcode::LoadAcq8:
22635switch (argIndex) {
22636case 0:
22637OPGEN_RETURN(false);
22638break;
22639case 1:
22640OPGEN_RETURN(false);
22641break;
22642default:
22643break;
22644}
22645break;
22646case Opcode::Store8:
22647switch (argIndex) {
22648case 0:
22649OPGEN_RETURN(false);
22650break;
22651case 1:
22652switch (args[0].kind()) {
22653case Arg::Tmp:
22654switch (Arg::Addr) {
22655case Arg::Index:
22656break;
22657case Arg::Addr:
22658case Arg::Stack:
22659case Arg::CallArg:
22660OPGEN_RETURN(true);
22661break;
22662break;
22663default:
22664break;
22665}
22666break;
22667case Arg::Imm:
22668switch (Arg::Addr) {
22669case Arg::Index:
22670break;
22671case Arg::Addr:
22672case Arg::Stack:
22673case Arg::CallArg:
22674#if CPU(X86) || CPU(X86_64)
22675OPGEN_RETURN(true);
22676#endif
22677break;
22678break;
22679default:
22680break;
22681}
22682break;
22683default:
22684break;
22685}
22686break;
22687default:
22688break;
22689}
22690break;
22691case Opcode::StoreRel8:
22692switch (argIndex) {
22693case 0:
22694OPGEN_RETURN(false);
22695break;
22696case 1:
22697OPGEN_RETURN(false);
22698break;
22699default:
22700break;
22701}
22702break;
22703case Opcode::Load8SignedExtendTo32:
22704switch (argIndex) {
22705case 0:
22706switch (Arg::Addr) {
22707case Arg::Addr:
22708case Arg::Stack:
22709case Arg::CallArg:
22710switch (args[1].kind()) {
22711case Arg::Tmp:
22712OPGEN_RETURN(true);
22713break;
22714break;
22715default:
22716break;
22717}
22718break;
22719case Arg::Index:
22720break;
22721default:
22722break;
22723}
22724break;
22725case 1:
22726OPGEN_RETURN(false);
22727break;
22728default:
22729break;
22730}
22731break;
22732case Opcode::LoadAcq8SignedExtendTo32:
22733switch (argIndex) {
22734case 0:
22735OPGEN_RETURN(false);
22736break;
22737case 1:
22738OPGEN_RETURN(false);
22739break;
22740default:
22741break;
22742}
22743break;
22744case Opcode::Load16:
22745switch (argIndex) {
22746case 0:
22747switch (Arg::Addr) {
22748case Arg::Addr:
22749case Arg::Stack:
22750case Arg::CallArg:
22751switch (args[1].kind()) {
22752case Arg::Tmp:
22753OPGEN_RETURN(true);
22754break;
22755break;
22756default:
22757break;
22758}
22759break;
22760case Arg::Index:
22761break;
22762default:
22763break;
22764}
22765break;
22766case 1:
22767OPGEN_RETURN(false);
22768break;
22769default:
22770break;
22771}
22772break;
22773case Opcode::LoadAcq16:
22774switch (argIndex) {
22775case 0:
22776OPGEN_RETURN(false);
22777break;
22778case 1:
22779OPGEN_RETURN(false);
22780break;
22781default:
22782break;
22783}
22784break;
22785case Opcode::Load16SignedExtendTo32:
22786switch (argIndex) {
22787case 0:
22788switch (Arg::Addr) {
22789case Arg::Addr:
22790case Arg::Stack:
22791case Arg::CallArg:
22792switch (args[1].kind()) {
22793case Arg::Tmp:
22794OPGEN_RETURN(true);
22795break;
22796break;
22797default:
22798break;
22799}
22800break;
22801case Arg::Index:
22802break;
22803default:
22804break;
22805}
22806break;
22807case 1:
22808OPGEN_RETURN(false);
22809break;
22810default:
22811break;
22812}
22813break;
22814case Opcode::LoadAcq16SignedExtendTo32:
22815switch (argIndex) {
22816case 0:
22817OPGEN_RETURN(false);
22818break;
22819case 1:
22820OPGEN_RETURN(false);
22821break;
22822default:
22823break;
22824}
22825break;
22826case Opcode::Store16:
22827switch (argIndex) {
22828case 0:
22829OPGEN_RETURN(false);
22830break;
22831case 1:
22832switch (args[0].kind()) {
22833case Arg::Tmp:
22834switch (Arg::Addr) {
22835case Arg::Index:
22836break;
22837case Arg::Addr:
22838case Arg::Stack:
22839case Arg::CallArg:
22840OPGEN_RETURN(true);
22841break;
22842break;
22843default:
22844break;
22845}
22846break;
22847case Arg::Imm:
22848switch (Arg::Addr) {
22849case Arg::Index:
22850break;
22851case Arg::Addr:
22852case Arg::Stack:
22853case Arg::CallArg:
22854#if CPU(X86) || CPU(X86_64)
22855OPGEN_RETURN(true);
22856#endif
22857break;
22858break;
22859default:
22860break;
22861}
22862break;
22863default:
22864break;
22865}
22866break;
22867default:
22868break;
22869}
22870break;
22871case Opcode::StoreRel16:
22872switch (argIndex) {
22873case 0:
22874OPGEN_RETURN(false);
22875break;
22876case 1:
22877OPGEN_RETURN(false);
22878break;
22879default:
22880break;
22881}
22882break;
22883case Opcode::LoadAcq32:
22884switch (argIndex) {
22885case 0:
22886OPGEN_RETURN(false);
22887break;
22888case 1:
22889OPGEN_RETURN(false);
22890break;
22891default:
22892break;
22893}
22894break;
22895case Opcode::StoreRel32:
22896switch (argIndex) {
22897case 0:
22898OPGEN_RETURN(false);
22899break;
22900case 1:
22901OPGEN_RETURN(false);
22902break;
22903default:
22904break;
22905}
22906break;
22907case Opcode::LoadAcq64:
22908switch (argIndex) {
22909case 0:
22910OPGEN_RETURN(false);
22911break;
22912case 1:
22913OPGEN_RETURN(false);
22914break;
22915default:
22916break;
22917}
22918break;
22919case Opcode::StoreRel64:
22920switch (argIndex) {
22921case 0:
22922OPGEN_RETURN(false);
22923break;
22924case 1:
22925OPGEN_RETURN(false);
22926break;
22927default:
22928break;
22929}
22930break;
22931case Opcode::Xchg8:
22932switch (argIndex) {
22933case 0:
22934OPGEN_RETURN(false);
22935break;
22936case 1:
22937switch (args[0].kind()) {
22938case Arg::Tmp:
22939switch (Arg::Addr) {
22940case Arg::Addr:
22941case Arg::Stack:
22942case Arg::CallArg:
22943#if CPU(X86) || CPU(X86_64)
22944OPGEN_RETURN(true);
22945#endif
22946break;
22947break;
22948case Arg::Index:
22949break;
22950default:
22951break;
22952}
22953break;
22954default:
22955break;
22956}
22957break;
22958default:
22959break;
22960}
22961break;
22962case Opcode::Xchg16:
22963switch (argIndex) {
22964case 0:
22965OPGEN_RETURN(false);
22966break;
22967case 1:
22968switch (args[0].kind()) {
22969case Arg::Tmp:
22970switch (Arg::Addr) {
22971case Arg::Addr:
22972case Arg::Stack:
22973case Arg::CallArg:
22974#if CPU(X86) || CPU(X86_64)
22975OPGEN_RETURN(true);
22976#endif
22977break;
22978break;
22979case Arg::Index:
22980break;
22981default:
22982break;
22983}
22984break;
22985default:
22986break;
22987}
22988break;
22989default:
22990break;
22991}
22992break;
22993case Opcode::Xchg32:
22994switch (argIndex) {
22995case 0:
22996OPGEN_RETURN(false);
22997break;
22998case 1:
22999switch (args[0].kind()) {
23000case Arg::Tmp:
23001switch (Arg::Addr) {
23002case Arg::Addr:
23003case Arg::Stack:
23004case Arg::CallArg:
23005#if CPU(X86) || CPU(X86_64)
23006OPGEN_RETURN(true);
23007#endif
23008break;
23009break;
23010case Arg::Index:
23011break;
23012default:
23013break;
23014}
23015break;
23016default:
23017break;
23018}
23019break;
23020default:
23021break;
23022}
23023break;
23024case Opcode::Xchg64:
23025switch (argIndex) {
23026case 0:
23027OPGEN_RETURN(false);
23028break;
23029case 1:
23030switch (args[0].kind()) {
23031case Arg::Tmp:
23032switch (Arg::Addr) {
23033case Arg::Addr:
23034case Arg::Stack:
23035case Arg::CallArg:
23036#if CPU(X86_64)
23037OPGEN_RETURN(true);
23038#endif
23039break;
23040break;
23041case Arg::Index:
23042break;
23043default:
23044break;
23045}
23046break;
23047default:
23048break;
23049}
23050break;
23051default:
23052break;
23053}
23054break;
23055case Opcode::AtomicStrongCAS8:
23056switch (argIndex) {
23057case 0:
23058OPGEN_RETURN(false);
23059break;
23060case 1:
23061OPGEN_RETURN(false);
23062break;
23063case 2:
23064switch (args.size()) {
23065case 3:
23066switch (args[0].kind()) {
23067case Arg::Tmp:
23068switch (args[1].kind()) {
23069case Arg::Tmp:
23070switch (Arg::Addr) {
23071case Arg::Addr:
23072case Arg::Stack:
23073case Arg::CallArg:
23074#if CPU(X86) || CPU(X86_64)
23075OPGEN_RETURN(true);
23076#endif
23077break;
23078break;
23079case Arg::Index:
23080break;
23081default:
23082break;
23083}
23084break;
23085default:
23086break;
23087}
23088break;
23089default:
23090break;
23091}
23092break;
23093default:
23094break;
23095}
23096break;
23097case 3:
23098switch (args.size()) {
23099case 5:
23100switch (args[0].kind()) {
23101case Arg::StatusCond:
23102switch (args[1].kind()) {
23103case Arg::Tmp:
23104switch (args[2].kind()) {
23105case Arg::Tmp:
23106switch (Arg::Addr) {
23107case Arg::Addr:
23108case Arg::Stack:
23109case Arg::CallArg:
23110switch (args[4].kind()) {
23111case Arg::Tmp:
23112#if CPU(X86) || CPU(X86_64)
23113OPGEN_RETURN(true);
23114#endif
23115break;
23116break;
23117default:
23118break;
23119}
23120break;
23121case Arg::Index:
23122break;
23123default:
23124break;
23125}
23126break;
23127default:
23128break;
23129}
23130break;
23131default:
23132break;
23133}
23134break;
23135default:
23136break;
23137}
23138break;
23139default:
23140break;
23141}
23142break;
23143case 4:
23144OPGEN_RETURN(false);
23145break;
23146default:
23147break;
23148}
23149break;
23150case Opcode::AtomicStrongCAS16:
23151switch (argIndex) {
23152case 0:
23153OPGEN_RETURN(false);
23154break;
23155case 1:
23156OPGEN_RETURN(false);
23157break;
23158case 2:
23159switch (args.size()) {
23160case 3:
23161switch (args[0].kind()) {
23162case Arg::Tmp:
23163switch (args[1].kind()) {
23164case Arg::Tmp:
23165switch (Arg::Addr) {
23166case Arg::Addr:
23167case Arg::Stack:
23168case Arg::CallArg:
23169#if CPU(X86) || CPU(X86_64)
23170OPGEN_RETURN(true);
23171#endif
23172break;
23173break;
23174case Arg::Index:
23175break;
23176default:
23177break;
23178}
23179break;
23180default:
23181break;
23182}
23183break;
23184default:
23185break;
23186}
23187break;
23188default:
23189break;
23190}
23191break;
23192case 3:
23193switch (args.size()) {
23194case 5:
23195switch (args[0].kind()) {
23196case Arg::StatusCond:
23197switch (args[1].kind()) {
23198case Arg::Tmp:
23199switch (args[2].kind()) {
23200case Arg::Tmp:
23201switch (Arg::Addr) {
23202case Arg::Addr:
23203case Arg::Stack:
23204case Arg::CallArg:
23205switch (args[4].kind()) {
23206case Arg::Tmp:
23207#if CPU(X86) || CPU(X86_64)
23208OPGEN_RETURN(true);
23209#endif
23210break;
23211break;
23212default:
23213break;
23214}
23215break;
23216case Arg::Index:
23217break;
23218default:
23219break;
23220}
23221break;
23222default:
23223break;
23224}
23225break;
23226default:
23227break;
23228}
23229break;
23230default:
23231break;
23232}
23233break;
23234default:
23235break;
23236}
23237break;
23238case 4:
23239OPGEN_RETURN(false);
23240break;
23241default:
23242break;
23243}
23244break;
23245case Opcode::AtomicStrongCAS32:
23246switch (argIndex) {
23247case 0:
23248OPGEN_RETURN(false);
23249break;
23250case 1:
23251OPGEN_RETURN(false);
23252break;
23253case 2:
23254switch (args.size()) {
23255case 3:
23256switch (args[0].kind()) {
23257case Arg::Tmp:
23258switch (args[1].kind()) {
23259case Arg::Tmp:
23260switch (Arg::Addr) {
23261case Arg::Addr:
23262case Arg::Stack:
23263case Arg::CallArg:
23264#if CPU(X86) || CPU(X86_64)
23265OPGEN_RETURN(true);
23266#endif
23267break;
23268break;
23269case Arg::Index:
23270break;
23271default:
23272break;
23273}
23274break;
23275default:
23276break;
23277}
23278break;
23279default:
23280break;
23281}
23282break;
23283default:
23284break;
23285}
23286break;
23287case 3:
23288switch (args.size()) {
23289case 5:
23290switch (args[0].kind()) {
23291case Arg::StatusCond:
23292switch (args[1].kind()) {
23293case Arg::Tmp:
23294switch (args[2].kind()) {
23295case Arg::Tmp:
23296switch (Arg::Addr) {
23297case Arg::Addr:
23298case Arg::Stack:
23299case Arg::CallArg:
23300switch (args[4].kind()) {
23301case Arg::Tmp:
23302#if CPU(X86) || CPU(X86_64)
23303OPGEN_RETURN(true);
23304#endif
23305break;
23306break;
23307default:
23308break;
23309}
23310break;
23311case Arg::Index:
23312break;
23313default:
23314break;
23315}
23316break;
23317default:
23318break;
23319}
23320break;
23321default:
23322break;
23323}
23324break;
23325default:
23326break;
23327}
23328break;
23329default:
23330break;
23331}
23332break;
23333case 4:
23334OPGEN_RETURN(false);
23335break;
23336default:
23337break;
23338}
23339break;
23340case Opcode::AtomicStrongCAS64:
23341switch (argIndex) {
23342case 0:
23343OPGEN_RETURN(false);
23344break;
23345case 1:
23346OPGEN_RETURN(false);
23347break;
23348case 2:
23349switch (args.size()) {
23350case 3:
23351switch (args[0].kind()) {
23352case Arg::Tmp:
23353switch (args[1].kind()) {
23354case Arg::Tmp:
23355switch (Arg::Addr) {
23356case Arg::Addr:
23357case Arg::Stack:
23358case Arg::CallArg:
23359#if CPU(X86_64)
23360OPGEN_RETURN(true);
23361#endif
23362break;
23363break;
23364case Arg::Index:
23365break;
23366default:
23367break;
23368}
23369break;
23370default:
23371break;
23372}
23373break;
23374default:
23375break;
23376}
23377break;
23378default:
23379break;
23380}
23381break;
23382case 3:
23383switch (args.size()) {
23384case 5:
23385switch (args[0].kind()) {
23386case Arg::StatusCond:
23387switch (args[1].kind()) {
23388case Arg::Tmp:
23389switch (args[2].kind()) {
23390case Arg::Tmp:
23391switch (Arg::Addr) {
23392case Arg::Addr:
23393case Arg::Stack:
23394case Arg::CallArg:
23395switch (args[4].kind()) {
23396case Arg::Tmp:
23397#if CPU(X86_64)
23398OPGEN_RETURN(true);
23399#endif
23400break;
23401break;
23402default:
23403break;
23404}
23405break;
23406case Arg::Index:
23407break;
23408default:
23409break;
23410}
23411break;
23412default:
23413break;
23414}
23415break;
23416default:
23417break;
23418}
23419break;
23420default:
23421break;
23422}
23423break;
23424default:
23425break;
23426}
23427break;
23428case 4:
23429OPGEN_RETURN(false);
23430break;
23431default:
23432break;
23433}
23434break;
23435case Opcode::BranchAtomicStrongCAS8:
23436switch (argIndex) {
23437case 0:
23438OPGEN_RETURN(false);
23439break;
23440case 1:
23441OPGEN_RETURN(false);
23442break;
23443case 2:
23444OPGEN_RETURN(false);
23445break;
23446case 3:
23447switch (args[0].kind()) {
23448case Arg::StatusCond:
23449switch (args[1].kind()) {
23450case Arg::Tmp:
23451switch (args[2].kind()) {
23452case Arg::Tmp:
23453switch (Arg::Addr) {
23454case Arg::Addr:
23455case Arg::Stack:
23456case Arg::CallArg:
23457#if CPU(X86) || CPU(X86_64)
23458OPGEN_RETURN(true);
23459#endif
23460break;
23461break;
23462case Arg::Index:
23463break;
23464default:
23465break;
23466}
23467break;
23468default:
23469break;
23470}
23471break;
23472default:
23473break;
23474}
23475break;
23476default:
23477break;
23478}
23479break;
23480default:
23481break;
23482}
23483break;
23484case Opcode::BranchAtomicStrongCAS16:
23485switch (argIndex) {
23486case 0:
23487OPGEN_RETURN(false);
23488break;
23489case 1:
23490OPGEN_RETURN(false);
23491break;
23492case 2:
23493OPGEN_RETURN(false);
23494break;
23495case 3:
23496switch (args[0].kind()) {
23497case Arg::StatusCond:
23498switch (args[1].kind()) {
23499case Arg::Tmp:
23500switch (args[2].kind()) {
23501case Arg::Tmp:
23502switch (Arg::Addr) {
23503case Arg::Addr:
23504case Arg::Stack:
23505case Arg::CallArg:
23506#if CPU(X86) || CPU(X86_64)
23507OPGEN_RETURN(true);
23508#endif
23509break;
23510break;
23511case Arg::Index:
23512break;
23513default:
23514break;
23515}
23516break;
23517default:
23518break;
23519}
23520break;
23521default:
23522break;
23523}
23524break;
23525default:
23526break;
23527}
23528break;
23529default:
23530break;
23531}
23532break;
23533case Opcode::BranchAtomicStrongCAS32:
23534switch (argIndex) {
23535case 0:
23536OPGEN_RETURN(false);
23537break;
23538case 1:
23539OPGEN_RETURN(false);
23540break;
23541case 2:
23542OPGEN_RETURN(false);
23543break;
23544case 3:
23545switch (args[0].kind()) {
23546case Arg::StatusCond:
23547switch (args[1].kind()) {
23548case Arg::Tmp:
23549switch (args[2].kind()) {
23550case Arg::Tmp:
23551switch (Arg::Addr) {
23552case Arg::Addr:
23553case Arg::Stack:
23554case Arg::CallArg:
23555#if CPU(X86) || CPU(X86_64)
23556OPGEN_RETURN(true);
23557#endif
23558break;
23559break;
23560case Arg::Index:
23561break;
23562default:
23563break;
23564}
23565break;
23566default:
23567break;
23568}
23569break;
23570default:
23571break;
23572}
23573break;
23574default:
23575break;
23576}
23577break;
23578default:
23579break;
23580}
23581break;
23582case Opcode::BranchAtomicStrongCAS64:
23583switch (argIndex) {
23584case 0:
23585OPGEN_RETURN(false);
23586break;
23587case 1:
23588OPGEN_RETURN(false);
23589break;
23590case 2:
23591OPGEN_RETURN(false);
23592break;
23593case 3:
23594switch (args[0].kind()) {
23595case Arg::StatusCond:
23596switch (args[1].kind()) {
23597case Arg::Tmp:
23598switch (args[2].kind()) {
23599case Arg::Tmp:
23600switch (Arg::Addr) {
23601case Arg::Addr:
23602case Arg::Stack:
23603case Arg::CallArg:
23604#if CPU(X86_64)
23605OPGEN_RETURN(true);
23606#endif
23607break;
23608break;
23609case Arg::Index:
23610break;
23611default:
23612break;
23613}
23614break;
23615default:
23616break;
23617}
23618break;
23619default:
23620break;
23621}
23622break;
23623default:
23624break;
23625}
23626break;
23627default:
23628break;
23629}
23630break;
23631case Opcode::AtomicAdd8:
23632switch (argIndex) {
23633case 0:
23634OPGEN_RETURN(false);
23635break;
23636case 1:
23637switch (args[0].kind()) {
23638case Arg::Imm:
23639switch (Arg::Addr) {
23640case Arg::Addr:
23641case Arg::Stack:
23642case Arg::CallArg:
23643#if CPU(X86) || CPU(X86_64)
23644OPGEN_RETURN(true);
23645#endif
23646break;
23647break;
23648case Arg::Index:
23649break;
23650default:
23651break;
23652}
23653break;
23654case Arg::Tmp:
23655switch (Arg::Addr) {
23656case Arg::Addr:
23657case Arg::Stack:
23658case Arg::CallArg:
23659#if CPU(X86) || CPU(X86_64)
23660OPGEN_RETURN(true);
23661#endif
23662break;
23663break;
23664case Arg::Index:
23665break;
23666default:
23667break;
23668}
23669break;
23670default:
23671break;
23672}
23673break;
23674default:
23675break;
23676}
23677break;
23678case Opcode::AtomicAdd16:
23679switch (argIndex) {
23680case 0:
23681OPGEN_RETURN(false);
23682break;
23683case 1:
23684switch (args[0].kind()) {
23685case Arg::Imm:
23686switch (Arg::Addr) {
23687case Arg::Addr:
23688case Arg::Stack:
23689case Arg::CallArg:
23690#if CPU(X86) || CPU(X86_64)
23691OPGEN_RETURN(true);
23692#endif
23693break;
23694break;
23695case Arg::Index:
23696break;
23697default:
23698break;
23699}
23700break;
23701case Arg::Tmp:
23702switch (Arg::Addr) {
23703case Arg::Addr:
23704case Arg::Stack:
23705case Arg::CallArg:
23706#if CPU(X86) || CPU(X86_64)
23707OPGEN_RETURN(true);
23708#endif
23709break;
23710break;
23711case Arg::Index:
23712break;
23713default:
23714break;
23715}
23716break;
23717default:
23718break;
23719}
23720break;
23721default:
23722break;
23723}
23724break;
23725case Opcode::AtomicAdd32:
23726switch (argIndex) {
23727case 0:
23728OPGEN_RETURN(false);
23729break;
23730case 1:
23731switch (args[0].kind()) {
23732case Arg::Imm:
23733switch (Arg::Addr) {
23734case Arg::Addr:
23735case Arg::Stack:
23736case Arg::CallArg:
23737#if CPU(X86) || CPU(X86_64)
23738OPGEN_RETURN(true);
23739#endif
23740break;
23741break;
23742case Arg::Index:
23743break;
23744default:
23745break;
23746}
23747break;
23748case Arg::Tmp:
23749switch (Arg::Addr) {
23750case Arg::Addr:
23751case Arg::Stack:
23752case Arg::CallArg:
23753#if CPU(X86) || CPU(X86_64)
23754OPGEN_RETURN(true);
23755#endif
23756break;
23757break;
23758case Arg::Index:
23759break;
23760default:
23761break;
23762}
23763break;
23764default:
23765break;
23766}
23767break;
23768default:
23769break;
23770}
23771break;
23772case Opcode::AtomicAdd64:
23773switch (argIndex) {
23774case 0:
23775OPGEN_RETURN(false);
23776break;
23777case 1:
23778switch (args[0].kind()) {
23779case Arg::Imm:
23780switch (Arg::Addr) {
23781case Arg::Addr:
23782case Arg::Stack:
23783case Arg::CallArg:
23784#if CPU(X86_64)
23785OPGEN_RETURN(true);
23786#endif
23787break;
23788break;
23789case Arg::Index:
23790break;
23791default:
23792break;
23793}
23794break;
23795case Arg::Tmp:
23796switch (Arg::Addr) {
23797case Arg::Addr:
23798case Arg::Stack:
23799case Arg::CallArg:
23800#if CPU(X86_64)
23801OPGEN_RETURN(true);
23802#endif
23803break;
23804break;
23805case Arg::Index:
23806break;
23807default:
23808break;
23809}
23810break;
23811default:
23812break;
23813}
23814break;
23815default:
23816break;
23817}
23818break;
23819case Opcode::AtomicSub8:
23820switch (argIndex) {
23821case 0:
23822OPGEN_RETURN(false);
23823break;
23824case 1:
23825switch (args[0].kind()) {
23826case Arg::Imm:
23827switch (Arg::Addr) {
23828case Arg::Addr:
23829case Arg::Stack:
23830case Arg::CallArg:
23831#if CPU(X86) || CPU(X86_64)
23832OPGEN_RETURN(true);
23833#endif
23834break;
23835break;
23836case Arg::Index:
23837break;
23838default:
23839break;
23840}
23841break;
23842case Arg::Tmp:
23843switch (Arg::Addr) {
23844case Arg::Addr:
23845case Arg::Stack:
23846case Arg::CallArg:
23847#if CPU(X86) || CPU(X86_64)
23848OPGEN_RETURN(true);
23849#endif
23850break;
23851break;
23852case Arg::Index:
23853break;
23854default:
23855break;
23856}
23857break;
23858default:
23859break;
23860}
23861break;
23862default:
23863break;
23864}
23865break;
23866case Opcode::AtomicSub16:
23867switch (argIndex) {
23868case 0:
23869OPGEN_RETURN(false);
23870break;
23871case 1:
23872switch (args[0].kind()) {
23873case Arg::Imm:
23874switch (Arg::Addr) {
23875case Arg::Addr:
23876case Arg::Stack:
23877case Arg::CallArg:
23878#if CPU(X86) || CPU(X86_64)
23879OPGEN_RETURN(true);
23880#endif
23881break;
23882break;
23883case Arg::Index:
23884break;
23885default:
23886break;
23887}
23888break;
23889case Arg::Tmp:
23890switch (Arg::Addr) {
23891case Arg::Addr:
23892case Arg::Stack:
23893case Arg::CallArg:
23894#if CPU(X86) || CPU(X86_64)
23895OPGEN_RETURN(true);
23896#endif
23897break;
23898break;
23899case Arg::Index:
23900break;
23901default:
23902break;
23903}
23904break;
23905default:
23906break;
23907}
23908break;
23909default:
23910break;
23911}
23912break;
23913case Opcode::AtomicSub32:
23914switch (argIndex) {
23915case 0:
23916OPGEN_RETURN(false);
23917break;
23918case 1:
23919switch (args[0].kind()) {
23920case Arg::Imm:
23921switch (Arg::Addr) {
23922case Arg::Addr:
23923case Arg::Stack:
23924case Arg::CallArg:
23925#if CPU(X86) || CPU(X86_64)
23926OPGEN_RETURN(true);
23927#endif
23928break;
23929break;
23930case Arg::Index:
23931break;
23932default:
23933break;
23934}
23935break;
23936case Arg::Tmp:
23937switch (Arg::Addr) {
23938case Arg::Addr:
23939case Arg::Stack:
23940case Arg::CallArg:
23941#if CPU(X86) || CPU(X86_64)
23942OPGEN_RETURN(true);
23943#endif
23944break;
23945break;
23946case Arg::Index:
23947break;
23948default:
23949break;
23950}
23951break;
23952default:
23953break;
23954}
23955break;
23956default:
23957break;
23958}
23959break;
23960case Opcode::AtomicSub64:
23961switch (argIndex) {
23962case 0:
23963OPGEN_RETURN(false);
23964break;
23965case 1:
23966switch (args[0].kind()) {
23967case Arg::Imm:
23968switch (Arg::Addr) {
23969case Arg::Addr:
23970case Arg::Stack:
23971case Arg::CallArg:
23972#if CPU(X86_64)
23973OPGEN_RETURN(true);
23974#endif
23975break;
23976break;
23977case Arg::Index:
23978break;
23979default:
23980break;
23981}
23982break;
23983case Arg::Tmp:
23984switch (Arg::Addr) {
23985case Arg::Addr:
23986case Arg::Stack:
23987case Arg::CallArg:
23988#if CPU(X86_64)
23989OPGEN_RETURN(true);
23990#endif
23991break;
23992break;
23993case Arg::Index:
23994break;
23995default:
23996break;
23997}
23998break;
23999default:
24000break;
24001}
24002break;
24003default:
24004break;
24005}
24006break;
24007case Opcode::AtomicAnd8:
24008switch (argIndex) {
24009case 0:
24010OPGEN_RETURN(false);
24011break;
24012case 1:
24013switch (args[0].kind()) {
24014case Arg::Imm:
24015switch (Arg::Addr) {
24016case Arg::Addr:
24017case Arg::Stack:
24018case Arg::CallArg:
24019#if CPU(X86) || CPU(X86_64)
24020OPGEN_RETURN(true);
24021#endif
24022break;
24023break;
24024case Arg::Index:
24025break;
24026default:
24027break;
24028}
24029break;
24030case Arg::Tmp:
24031switch (Arg::Addr) {
24032case Arg::Addr:
24033case Arg::Stack:
24034case Arg::CallArg:
24035#if CPU(X86) || CPU(X86_64)
24036OPGEN_RETURN(true);
24037#endif
24038break;
24039break;
24040case Arg::Index:
24041break;
24042default:
24043break;
24044}
24045break;
24046default:
24047break;
24048}
24049break;
24050default:
24051break;
24052}
24053break;
24054case Opcode::AtomicAnd16:
24055switch (argIndex) {
24056case 0:
24057OPGEN_RETURN(false);
24058break;
24059case 1:
24060switch (args[0].kind()) {
24061case Arg::Imm:
24062switch (Arg::Addr) {
24063case Arg::Addr:
24064case Arg::Stack:
24065case Arg::CallArg:
24066#if CPU(X86) || CPU(X86_64)
24067OPGEN_RETURN(true);
24068#endif
24069break;
24070break;
24071case Arg::Index:
24072break;
24073default:
24074break;
24075}
24076break;
24077case Arg::Tmp:
24078switch (Arg::Addr) {
24079case Arg::Addr:
24080case Arg::Stack:
24081case Arg::CallArg:
24082#if CPU(X86) || CPU(X86_64)
24083OPGEN_RETURN(true);
24084#endif
24085break;
24086break;
24087case Arg::Index:
24088break;
24089default:
24090break;
24091}
24092break;
24093default:
24094break;
24095}
24096break;
24097default:
24098break;
24099}
24100break;
24101case Opcode::AtomicAnd32:
24102switch (argIndex) {
24103case 0:
24104OPGEN_RETURN(false);
24105break;
24106case 1:
24107switch (args[0].kind()) {
24108case Arg::Imm:
24109switch (Arg::Addr) {
24110case Arg::Addr:
24111case Arg::Stack:
24112case Arg::CallArg:
24113#if CPU(X86) || CPU(X86_64)
24114OPGEN_RETURN(true);
24115#endif
24116break;
24117break;
24118case Arg::Index:
24119break;
24120default:
24121break;
24122}
24123break;
24124case Arg::Tmp:
24125switch (Arg::Addr) {
24126case Arg::Addr:
24127case Arg::Stack:
24128case Arg::CallArg:
24129#if CPU(X86) || CPU(X86_64)
24130OPGEN_RETURN(true);
24131#endif
24132break;
24133break;
24134case Arg::Index:
24135break;
24136default:
24137break;
24138}
24139break;
24140default:
24141break;
24142}
24143break;
24144default:
24145break;
24146}
24147break;
24148case Opcode::AtomicAnd64:
24149switch (argIndex) {
24150case 0:
24151OPGEN_RETURN(false);
24152break;
24153case 1:
24154switch (args[0].kind()) {
24155case Arg::Imm:
24156switch (Arg::Addr) {
24157case Arg::Addr:
24158case Arg::Stack:
24159case Arg::CallArg:
24160#if CPU(X86_64)
24161OPGEN_RETURN(true);
24162#endif
24163break;
24164break;
24165case Arg::Index:
24166break;
24167default:
24168break;
24169}
24170break;
24171case Arg::Tmp:
24172switch (Arg::Addr) {
24173case Arg::Addr:
24174case Arg::Stack:
24175case Arg::CallArg:
24176#if CPU(X86_64)
24177OPGEN_RETURN(true);
24178#endif
24179break;
24180break;
24181case Arg::Index:
24182break;
24183default:
24184break;
24185}
24186break;
24187default:
24188break;
24189}
24190break;
24191default:
24192break;
24193}
24194break;
24195case Opcode::AtomicOr8:
24196switch (argIndex) {
24197case 0:
24198OPGEN_RETURN(false);
24199break;
24200case 1:
24201switch (args[0].kind()) {
24202case Arg::Imm:
24203switch (Arg::Addr) {
24204case Arg::Addr:
24205case Arg::Stack:
24206case Arg::CallArg:
24207#if CPU(X86) || CPU(X86_64)
24208OPGEN_RETURN(true);
24209#endif
24210break;
24211break;
24212case Arg::Index:
24213break;
24214default:
24215break;
24216}
24217break;
24218case Arg::Tmp:
24219switch (Arg::Addr) {
24220case Arg::Addr:
24221case Arg::Stack:
24222case Arg::CallArg:
24223#if CPU(X86) || CPU(X86_64)
24224OPGEN_RETURN(true);
24225#endif
24226break;
24227break;
24228case Arg::Index:
24229break;
24230default:
24231break;
24232}
24233break;
24234default:
24235break;
24236}
24237break;
24238default:
24239break;
24240}
24241break;
24242case Opcode::AtomicOr16:
24243switch (argIndex) {
24244case 0:
24245OPGEN_RETURN(false);
24246break;
24247case 1:
24248switch (args[0].kind()) {
24249case Arg::Imm:
24250switch (Arg::Addr) {
24251case Arg::Addr:
24252case Arg::Stack:
24253case Arg::CallArg:
24254#if CPU(X86) || CPU(X86_64)
24255OPGEN_RETURN(true);
24256#endif
24257break;
24258break;
24259case Arg::Index:
24260break;
24261default:
24262break;
24263}
24264break;
24265case Arg::Tmp:
24266switch (Arg::Addr) {
24267case Arg::Addr:
24268case Arg::Stack:
24269case Arg::CallArg:
24270#if CPU(X86) || CPU(X86_64)
24271OPGEN_RETURN(true);
24272#endif
24273break;
24274break;
24275case Arg::Index:
24276break;
24277default:
24278break;
24279}
24280break;
24281default:
24282break;
24283}
24284break;
24285default:
24286break;
24287}
24288break;
24289case Opcode::AtomicOr32:
24290switch (argIndex) {
24291case 0:
24292OPGEN_RETURN(false);
24293break;
24294case 1:
24295switch (args[0].kind()) {
24296case Arg::Imm:
24297switch (Arg::Addr) {
24298case Arg::Addr:
24299case Arg::Stack:
24300case Arg::CallArg:
24301#if CPU(X86) || CPU(X86_64)
24302OPGEN_RETURN(true);
24303#endif
24304break;
24305break;
24306case Arg::Index:
24307break;
24308default:
24309break;
24310}
24311break;
24312case Arg::Tmp:
24313switch (Arg::Addr) {
24314case Arg::Addr:
24315case Arg::Stack:
24316case Arg::CallArg:
24317#if CPU(X86) || CPU(X86_64)
24318OPGEN_RETURN(true);
24319#endif
24320break;
24321break;
24322case Arg::Index:
24323break;
24324default:
24325break;
24326}
24327break;
24328default:
24329break;
24330}
24331break;
24332default:
24333break;
24334}
24335break;
24336case Opcode::AtomicOr64:
24337switch (argIndex) {
24338case 0:
24339OPGEN_RETURN(false);
24340break;
24341case 1:
24342switch (args[0].kind()) {
24343case Arg::Imm:
24344switch (Arg::Addr) {
24345case Arg::Addr:
24346case Arg::Stack:
24347case Arg::CallArg:
24348#if CPU(X86_64)
24349OPGEN_RETURN(true);
24350#endif
24351break;
24352break;
24353case Arg::Index:
24354break;
24355default:
24356break;
24357}
24358break;
24359case Arg::Tmp:
24360switch (Arg::Addr) {
24361case Arg::Addr:
24362case Arg::Stack:
24363case Arg::CallArg:
24364#if CPU(X86_64)
24365OPGEN_RETURN(true);
24366#endif
24367break;
24368break;
24369case Arg::Index:
24370break;
24371default:
24372break;
24373}
24374break;
24375default:
24376break;
24377}
24378break;
24379default:
24380break;
24381}
24382break;
24383case Opcode::AtomicXor8:
24384switch (argIndex) {
24385case 0:
24386OPGEN_RETURN(false);
24387break;
24388case 1:
24389switch (args[0].kind()) {
24390case Arg::Imm:
24391switch (Arg::Addr) {
24392case Arg::Addr:
24393case Arg::Stack:
24394case Arg::CallArg:
24395#if CPU(X86) || CPU(X86_64)
24396OPGEN_RETURN(true);
24397#endif
24398break;
24399break;
24400case Arg::Index:
24401break;
24402default:
24403break;
24404}
24405break;
24406case Arg::Tmp:
24407switch (Arg::Addr) {
24408case Arg::Addr:
24409case Arg::Stack:
24410case Arg::CallArg:
24411#if CPU(X86) || CPU(X86_64)
24412OPGEN_RETURN(true);
24413#endif
24414break;
24415break;
24416case Arg::Index:
24417break;
24418default:
24419break;
24420}
24421break;
24422default:
24423break;
24424}
24425break;
24426default:
24427break;
24428}
24429break;
24430case Opcode::AtomicXor16:
24431switch (argIndex) {
24432case 0:
24433OPGEN_RETURN(false);
24434break;
24435case 1:
24436switch (args[0].kind()) {
24437case Arg::Imm:
24438switch (Arg::Addr) {
24439case Arg::Addr:
24440case Arg::Stack:
24441case Arg::CallArg:
24442#if CPU(X86) || CPU(X86_64)
24443OPGEN_RETURN(true);
24444#endif
24445break;
24446break;
24447case Arg::Index:
24448break;
24449default:
24450break;
24451}
24452break;
24453case Arg::Tmp:
24454switch (Arg::Addr) {
24455case Arg::Addr:
24456case Arg::Stack:
24457case Arg::CallArg:
24458#if CPU(X86) || CPU(X86_64)
24459OPGEN_RETURN(true);
24460#endif
24461break;
24462break;
24463case Arg::Index:
24464break;
24465default:
24466break;
24467}
24468break;
24469default:
24470break;
24471}
24472break;
24473default:
24474break;
24475}
24476break;
24477case Opcode::AtomicXor32:
24478switch (argIndex) {
24479case 0:
24480OPGEN_RETURN(false);
24481break;
24482case 1:
24483switch (args[0].kind()) {
24484case Arg::Imm:
24485switch (Arg::Addr) {
24486case Arg::Addr:
24487case Arg::Stack:
24488case Arg::CallArg:
24489#if CPU(X86) || CPU(X86_64)
24490OPGEN_RETURN(true);
24491#endif
24492break;
24493break;
24494case Arg::Index:
24495break;
24496default:
24497break;
24498}
24499break;
24500case Arg::Tmp:
24501switch (Arg::Addr) {
24502case Arg::Addr:
24503case Arg::Stack:
24504case Arg::CallArg:
24505#if CPU(X86) || CPU(X86_64)
24506OPGEN_RETURN(true);
24507#endif
24508break;
24509break;
24510case Arg::Index:
24511break;
24512default:
24513break;
24514}
24515break;
24516default:
24517break;
24518}
24519break;
24520default:
24521break;
24522}
24523break;
24524case Opcode::AtomicXor64:
24525switch (argIndex) {
24526case 0:
24527OPGEN_RETURN(false);
24528break;
24529case 1:
24530switch (args[0].kind()) {
24531case Arg::Imm:
24532switch (Arg::Addr) {
24533case Arg::Addr:
24534case Arg::Stack:
24535case Arg::CallArg:
24536#if CPU(X86_64)
24537OPGEN_RETURN(true);
24538#endif
24539break;
24540break;
24541case Arg::Index:
24542break;
24543default:
24544break;
24545}
24546break;
24547case Arg::Tmp:
24548switch (Arg::Addr) {
24549case Arg::Addr:
24550case Arg::Stack:
24551case Arg::CallArg:
24552#if CPU(X86_64)
24553OPGEN_RETURN(true);
24554#endif
24555break;
24556break;
24557case Arg::Index:
24558break;
24559default:
24560break;
24561}
24562break;
24563default:
24564break;
24565}
24566break;
24567default:
24568break;
24569}
24570break;
24571case Opcode::AtomicNeg8:
24572switch (argIndex) {
24573case 0:
24574switch (Arg::Addr) {
24575case Arg::Addr:
24576case Arg::Stack:
24577case Arg::CallArg:
24578#if CPU(X86) || CPU(X86_64)
24579OPGEN_RETURN(true);
24580#endif
24581break;
24582break;
24583case Arg::Index:
24584break;
24585default:
24586break;
24587}
24588break;
24589default:
24590break;
24591}
24592break;
24593case Opcode::AtomicNeg16:
24594switch (argIndex) {
24595case 0:
24596switch (Arg::Addr) {
24597case Arg::Addr:
24598case Arg::Stack:
24599case Arg::CallArg:
24600#if CPU(X86) || CPU(X86_64)
24601OPGEN_RETURN(true);
24602#endif
24603break;
24604break;
24605case Arg::Index:
24606break;
24607default:
24608break;
24609}
24610break;
24611default:
24612break;
24613}
24614break;
24615case Opcode::AtomicNeg32:
24616switch (argIndex) {
24617case 0:
24618switch (Arg::Addr) {
24619case Arg::Addr:
24620case Arg::Stack:
24621case Arg::CallArg:
24622#if CPU(X86) || CPU(X86_64)
24623OPGEN_RETURN(true);
24624#endif
24625break;
24626break;
24627case Arg::Index:
24628break;
24629default:
24630break;
24631}
24632break;
24633default:
24634break;
24635}
24636break;
24637case Opcode::AtomicNeg64:
24638switch (argIndex) {
24639case 0:
24640switch (Arg::Addr) {
24641case Arg::Addr:
24642case Arg::Stack:
24643case Arg::CallArg:
24644#if CPU(X86_64)
24645OPGEN_RETURN(true);
24646#endif
24647break;
24648break;
24649case Arg::Index:
24650break;
24651default:
24652break;
24653}
24654break;
24655default:
24656break;
24657}
24658break;
24659case Opcode::AtomicNot8:
24660switch (argIndex) {
24661case 0:
24662switch (Arg::Addr) {
24663case Arg::Addr:
24664case Arg::Stack:
24665case Arg::CallArg:
24666#if CPU(X86) || CPU(X86_64)
24667OPGEN_RETURN(true);
24668#endif
24669break;
24670break;
24671case Arg::Index:
24672break;
24673default:
24674break;
24675}
24676break;
24677default:
24678break;
24679}
24680break;
24681case Opcode::AtomicNot16:
24682switch (argIndex) {
24683case 0:
24684switch (Arg::Addr) {
24685case Arg::Addr:
24686case Arg::Stack:
24687case Arg::CallArg:
24688#if CPU(X86) || CPU(X86_64)
24689OPGEN_RETURN(true);
24690#endif
24691break;
24692break;
24693case Arg::Index:
24694break;
24695default:
24696break;
24697}
24698break;
24699default:
24700break;
24701}
24702break;
24703case Opcode::AtomicNot32:
24704switch (argIndex) {
24705case 0:
24706switch (Arg::Addr) {
24707case Arg::Addr:
24708case Arg::Stack:
24709case Arg::CallArg:
24710#if CPU(X86) || CPU(X86_64)
24711OPGEN_RETURN(true);
24712#endif
24713break;
24714break;
24715case Arg::Index:
24716break;
24717default:
24718break;
24719}
24720break;
24721default:
24722break;
24723}
24724break;
24725case Opcode::AtomicNot64:
24726switch (argIndex) {
24727case 0:
24728switch (Arg::Addr) {
24729case Arg::Addr:
24730case Arg::Stack:
24731case Arg::CallArg:
24732#if CPU(X86_64)
24733OPGEN_RETURN(true);
24734#endif
24735break;
24736break;
24737case Arg::Index:
24738break;
24739default:
24740break;
24741}
24742break;
24743default:
24744break;
24745}
24746break;
24747case Opcode::AtomicXchgAdd8:
24748switch (argIndex) {
24749case 0:
24750OPGEN_RETURN(false);
24751break;
24752case 1:
24753switch (args[0].kind()) {
24754case Arg::Tmp:
24755switch (Arg::Addr) {
24756case Arg::Addr:
24757case Arg::Stack:
24758case Arg::CallArg:
24759#if CPU(X86) || CPU(X86_64)
24760OPGEN_RETURN(true);
24761#endif
24762break;
24763break;
24764case Arg::Index:
24765break;
24766default:
24767break;
24768}
24769break;
24770default:
24771break;
24772}
24773break;
24774default:
24775break;
24776}
24777break;
24778case Opcode::AtomicXchgAdd16:
24779switch (argIndex) {
24780case 0:
24781OPGEN_RETURN(false);
24782break;
24783case 1:
24784switch (args[0].kind()) {
24785case Arg::Tmp:
24786switch (Arg::Addr) {
24787case Arg::Addr:
24788case Arg::Stack:
24789case Arg::CallArg:
24790#if CPU(X86) || CPU(X86_64)
24791OPGEN_RETURN(true);
24792#endif
24793break;
24794break;
24795case Arg::Index:
24796break;
24797default:
24798break;
24799}
24800break;
24801default:
24802break;
24803}
24804break;
24805default:
24806break;
24807}
24808break;
24809case Opcode::AtomicXchgAdd32:
24810switch (argIndex) {
24811case 0:
24812OPGEN_RETURN(false);
24813break;
24814case 1:
24815switch (args[0].kind()) {
24816case Arg::Tmp:
24817switch (Arg::Addr) {
24818case Arg::Addr:
24819case Arg::Stack:
24820case Arg::CallArg:
24821#if CPU(X86) || CPU(X86_64)
24822OPGEN_RETURN(true);
24823#endif
24824break;
24825break;
24826case Arg::Index:
24827break;
24828default:
24829break;
24830}
24831break;
24832default:
24833break;
24834}
24835break;
24836default:
24837break;
24838}
24839break;
24840case Opcode::AtomicXchgAdd64:
24841switch (argIndex) {
24842case 0:
24843OPGEN_RETURN(false);
24844break;
24845case 1:
24846switch (args[0].kind()) {
24847case Arg::Tmp:
24848switch (Arg::Addr) {
24849case Arg::Addr:
24850case Arg::Stack:
24851case Arg::CallArg:
24852#if CPU(X86_64)
24853OPGEN_RETURN(true);
24854#endif
24855break;
24856break;
24857case Arg::Index:
24858break;
24859default:
24860break;
24861}
24862break;
24863default:
24864break;
24865}
24866break;
24867default:
24868break;
24869}
24870break;
24871case Opcode::AtomicXchg8:
24872switch (argIndex) {
24873case 0:
24874OPGEN_RETURN(false);
24875break;
24876case 1:
24877switch (args[0].kind()) {
24878case Arg::Tmp:
24879switch (Arg::Addr) {
24880case Arg::Addr:
24881case Arg::Stack:
24882case Arg::CallArg:
24883#if CPU(X86) || CPU(X86_64)
24884OPGEN_RETURN(true);
24885#endif
24886break;
24887break;
24888case Arg::Index:
24889break;
24890default:
24891break;
24892}
24893break;
24894default:
24895break;
24896}
24897break;
24898default:
24899break;
24900}
24901break;
24902case Opcode::AtomicXchg16:
24903switch (argIndex) {
24904case 0:
24905OPGEN_RETURN(false);
24906break;
24907case 1:
24908switch (args[0].kind()) {
24909case Arg::Tmp:
24910switch (Arg::Addr) {
24911case Arg::Addr:
24912case Arg::Stack:
24913case Arg::CallArg:
24914#if CPU(X86) || CPU(X86_64)
24915OPGEN_RETURN(true);
24916#endif
24917break;
24918break;
24919case Arg::Index:
24920break;
24921default:
24922break;
24923}
24924break;
24925default:
24926break;
24927}
24928break;
24929default:
24930break;
24931}
24932break;
24933case Opcode::AtomicXchg32:
24934switch (argIndex) {
24935case 0:
24936OPGEN_RETURN(false);
24937break;
24938case 1:
24939switch (args[0].kind()) {
24940case Arg::Tmp:
24941switch (Arg::Addr) {
24942case Arg::Addr:
24943case Arg::Stack:
24944case Arg::CallArg:
24945#if CPU(X86) || CPU(X86_64)
24946OPGEN_RETURN(true);
24947#endif
24948break;
24949break;
24950case Arg::Index:
24951break;
24952default:
24953break;
24954}
24955break;
24956default:
24957break;
24958}
24959break;
24960default:
24961break;
24962}
24963break;
24964case Opcode::AtomicXchg64:
24965switch (argIndex) {
24966case 0:
24967OPGEN_RETURN(false);
24968break;
24969case 1:
24970switch (args[0].kind()) {
24971case Arg::Tmp:
24972switch (Arg::Addr) {
24973case Arg::Addr:
24974case Arg::Stack:
24975case Arg::CallArg:
24976#if CPU(X86_64)
24977OPGEN_RETURN(true);
24978#endif
24979break;
24980break;
24981case Arg::Index:
24982break;
24983default:
24984break;
24985}
24986break;
24987default:
24988break;
24989}
24990break;
24991default:
24992break;
24993}
24994break;
24995case Opcode::LoadLink8:
24996switch (argIndex) {
24997case 0:
24998OPGEN_RETURN(false);
24999break;
25000case 1:
25001OPGEN_RETURN(false);
25002break;
25003default:
25004break;
25005}
25006break;
25007case Opcode::LoadLinkAcq8:
25008switch (argIndex) {
25009case 0:
25010OPGEN_RETURN(false);
25011break;
25012case 1:
25013OPGEN_RETURN(false);
25014break;
25015default:
25016break;
25017}
25018break;
25019case Opcode::StoreCond8:
25020switch (argIndex) {
25021case 0:
25022OPGEN_RETURN(false);
25023break;
25024case 1:
25025OPGEN_RETURN(false);
25026break;
25027case 2:
25028OPGEN_RETURN(false);
25029break;
25030default:
25031break;
25032}
25033break;
25034case Opcode::StoreCondRel8:
25035switch (argIndex) {
25036case 0:
25037OPGEN_RETURN(false);
25038break;
25039case 1:
25040OPGEN_RETURN(false);
25041break;
25042case 2:
25043OPGEN_RETURN(false);
25044break;
25045default:
25046break;
25047}
25048break;
25049case Opcode::LoadLink16:
25050switch (argIndex) {
25051case 0:
25052OPGEN_RETURN(false);
25053break;
25054case 1:
25055OPGEN_RETURN(false);
25056break;
25057default:
25058break;
25059}
25060break;
25061case Opcode::LoadLinkAcq16:
25062switch (argIndex) {
25063case 0:
25064OPGEN_RETURN(false);
25065break;
25066case 1:
25067OPGEN_RETURN(false);
25068break;
25069default:
25070break;
25071}
25072break;
25073case Opcode::StoreCond16:
25074switch (argIndex) {
25075case 0:
25076OPGEN_RETURN(false);
25077break;
25078case 1:
25079OPGEN_RETURN(false);
25080break;
25081case 2:
25082OPGEN_RETURN(false);
25083break;
25084default:
25085break;
25086}
25087break;
25088case Opcode::StoreCondRel16:
25089switch (argIndex) {
25090case 0:
25091OPGEN_RETURN(false);
25092break;
25093case 1:
25094OPGEN_RETURN(false);
25095break;
25096case 2:
25097OPGEN_RETURN(false);
25098break;
25099default:
25100break;
25101}
25102break;
25103case Opcode::LoadLink32:
25104switch (argIndex) {
25105case 0:
25106OPGEN_RETURN(false);
25107break;
25108case 1:
25109OPGEN_RETURN(false);
25110break;
25111default:
25112break;
25113}
25114break;
25115case Opcode::LoadLinkAcq32:
25116switch (argIndex) {
25117case 0:
25118OPGEN_RETURN(false);
25119break;
25120case 1:
25121OPGEN_RETURN(false);
25122break;
25123default:
25124break;
25125}
25126break;
25127case Opcode::StoreCond32:
25128switch (argIndex) {
25129case 0:
25130OPGEN_RETURN(false);
25131break;
25132case 1:
25133OPGEN_RETURN(false);
25134break;
25135case 2:
25136OPGEN_RETURN(false);
25137break;
25138default:
25139break;
25140}
25141break;
25142case Opcode::StoreCondRel32:
25143switch (argIndex) {
25144case 0:
25145OPGEN_RETURN(false);
25146break;
25147case 1:
25148OPGEN_RETURN(false);
25149break;
25150case 2:
25151OPGEN_RETURN(false);
25152break;
25153default:
25154break;
25155}
25156break;
25157case Opcode::LoadLink64:
25158switch (argIndex) {
25159case 0:
25160OPGEN_RETURN(false);
25161break;
25162case 1:
25163OPGEN_RETURN(false);
25164break;
25165default:
25166break;
25167}
25168break;
25169case Opcode::LoadLinkAcq64:
25170switch (argIndex) {
25171case 0:
25172OPGEN_RETURN(false);
25173break;
25174case 1:
25175OPGEN_RETURN(false);
25176break;
25177default:
25178break;
25179}
25180break;
25181case Opcode::StoreCond64:
25182switch (argIndex) {
25183case 0:
25184OPGEN_RETURN(false);
25185break;
25186case 1:
25187OPGEN_RETURN(false);
25188break;
25189case 2:
25190OPGEN_RETURN(false);
25191break;
25192default:
25193break;
25194}
25195break;
25196case Opcode::StoreCondRel64:
25197switch (argIndex) {
25198case 0:
25199OPGEN_RETURN(false);
25200break;
25201case 1:
25202OPGEN_RETURN(false);
25203break;
25204case 2:
25205OPGEN_RETURN(false);
25206break;
25207default:
25208break;
25209}
25210break;
25211case Opcode::Depend32:
25212switch (argIndex) {
25213case 0:
25214OPGEN_RETURN(false);
25215break;
25216case 1:
25217OPGEN_RETURN(false);
25218break;
25219default:
25220break;
25221}
25222break;
25223case Opcode::Depend64:
25224switch (argIndex) {
25225case 0:
25226OPGEN_RETURN(false);
25227break;
25228case 1:
25229OPGEN_RETURN(false);
25230break;
25231default:
25232break;
25233}
25234break;
25235case Opcode::Compare32:
25236switch (argIndex) {
25237case 0:
25238OPGEN_RETURN(false);
25239break;
25240case 1:
25241OPGEN_RETURN(false);
25242break;
25243case 2:
25244OPGEN_RETURN(false);
25245break;
25246case 3:
25247OPGEN_RETURN(false);
25248break;
25249default:
25250break;
25251}
25252break;
25253case Opcode::Compare64:
25254switch (argIndex) {
25255case 0:
25256OPGEN_RETURN(false);
25257break;
25258case 1:
25259OPGEN_RETURN(false);
25260break;
25261case 2:
25262OPGEN_RETURN(false);
25263break;
25264case 3:
25265OPGEN_RETURN(false);
25266break;
25267default:
25268break;
25269}
25270break;
25271case Opcode::Test32:
25272switch (argIndex) {
25273case 0:
25274OPGEN_RETURN(false);
25275break;
25276case 1:
25277switch (args[0].kind()) {
25278case Arg::ResCond:
25279switch (Arg::Addr) {
25280case Arg::Addr:
25281case Arg::Stack:
25282case Arg::CallArg:
25283switch (args[2].kind()) {
25284case Arg::Imm:
25285switch (args[3].kind()) {
25286case Arg::Tmp:
25287#if CPU(X86) || CPU(X86_64)
25288OPGEN_RETURN(true);
25289#endif
25290break;
25291break;
25292default:
25293break;
25294}
25295break;
25296default:
25297break;
25298}
25299break;
25300case Arg::Tmp:
25301break;
25302default:
25303break;
25304}
25305break;
25306default:
25307break;
25308}
25309break;
25310case 2:
25311OPGEN_RETURN(false);
25312break;
25313case 3:
25314OPGEN_RETURN(false);
25315break;
25316default:
25317break;
25318}
25319break;
25320case Opcode::Test64:
25321switch (argIndex) {
25322case 0:
25323OPGEN_RETURN(false);
25324break;
25325case 1:
25326OPGEN_RETURN(false);
25327break;
25328case 2:
25329OPGEN_RETURN(false);
25330break;
25331case 3:
25332OPGEN_RETURN(false);
25333break;
25334default:
25335break;
25336}
25337break;
25338case Opcode::CompareDouble:
25339switch (argIndex) {
25340case 0:
25341OPGEN_RETURN(false);
25342break;
25343case 1:
25344OPGEN_RETURN(false);
25345break;
25346case 2:
25347OPGEN_RETURN(false);
25348break;
25349case 3:
25350OPGEN_RETURN(false);
25351break;
25352default:
25353break;
25354}
25355break;
25356case Opcode::CompareFloat:
25357switch (argIndex) {
25358case 0:
25359OPGEN_RETURN(false);
25360break;
25361case 1:
25362OPGEN_RETURN(false);
25363break;
25364case 2:
25365OPGEN_RETURN(false);
25366break;
25367case 3:
25368OPGEN_RETURN(false);
25369break;
25370default:
25371break;
25372}
25373break;
25374case Opcode::Branch8:
25375switch (argIndex) {
25376case 0:
25377OPGEN_RETURN(false);
25378break;
25379case 1:
25380switch (args[0].kind()) {
25381case Arg::RelCond:
25382switch (Arg::Addr) {
25383case Arg::Addr:
25384case Arg::Stack:
25385case Arg::CallArg:
25386switch (args[2].kind()) {
25387case Arg::Imm:
25388#if CPU(X86) || CPU(X86_64)
25389OPGEN_RETURN(true);
25390#endif
25391break;
25392break;
25393default:
25394break;
25395}
25396break;
25397case Arg::Index:
25398break;
25399default:
25400break;
25401}
25402break;
25403default:
25404break;
25405}
25406break;
25407case 2:
25408OPGEN_RETURN(false);
25409break;
25410default:
25411break;
25412}
25413break;
25414case Opcode::Branch32:
25415switch (argIndex) {
25416case 0:
25417OPGEN_RETURN(false);
25418break;
25419case 1:
25420switch (args[0].kind()) {
25421case Arg::RelCond:
25422switch (Arg::Addr) {
25423case Arg::Addr:
25424case Arg::Stack:
25425case Arg::CallArg:
25426switch (args[2].kind()) {
25427case Arg::Imm:
25428#if CPU(X86) || CPU(X86_64)
25429OPGEN_RETURN(true);
25430#endif
25431break;
25432break;
25433case Arg::Tmp:
25434#if CPU(X86) || CPU(X86_64)
25435OPGEN_RETURN(true);
25436#endif
25437break;
25438break;
25439default:
25440break;
25441}
25442break;
25443case Arg::Tmp:
25444break;
25445case Arg::Index:
25446break;
25447default:
25448break;
25449}
25450break;
25451default:
25452break;
25453}
25454break;
25455case 2:
25456switch (args[0].kind()) {
25457case Arg::RelCond:
25458switch (args[1].kind()) {
25459case Arg::Addr:
25460case Arg::Stack:
25461case Arg::CallArg:
25462break;
25463case Arg::Tmp:
25464switch (Arg::Addr) {
25465case Arg::Tmp:
25466break;
25467case Arg::Imm:
25468break;
25469case Arg::Addr:
25470case Arg::Stack:
25471case Arg::CallArg:
25472#if CPU(X86) || CPU(X86_64)
25473OPGEN_RETURN(true);
25474#endif
25475break;
25476break;
25477default:
25478break;
25479}
25480break;
25481case Arg::Index:
25482break;
25483default:
25484break;
25485}
25486break;
25487default:
25488break;
25489}
25490break;
25491default:
25492break;
25493}
25494break;
25495case Opcode::Branch64:
25496switch (argIndex) {
25497case 0:
25498OPGEN_RETURN(false);
25499break;
25500case 1:
25501switch (args[0].kind()) {
25502case Arg::RelCond:
25503switch (Arg::Addr) {
25504case Arg::Tmp:
25505break;
25506case Arg::Addr:
25507case Arg::Stack:
25508case Arg::CallArg:
25509switch (args[2].kind()) {
25510case Arg::Tmp:
25511#if CPU(X86_64)
25512OPGEN_RETURN(true);
25513#endif
25514break;
25515break;
25516case Arg::Imm:
25517#if CPU(X86_64)
25518OPGEN_RETURN(true);
25519#endif
25520break;
25521break;
25522default:
25523break;
25524}
25525break;
25526case Arg::Index:
25527break;
25528default:
25529break;
25530}
25531break;
25532default:
25533break;
25534}
25535break;
25536case 2:
25537switch (args[0].kind()) {
25538case Arg::RelCond:
25539switch (args[1].kind()) {
25540case Arg::Tmp:
25541switch (Arg::Addr) {
25542case Arg::Tmp:
25543break;
25544case Arg::Imm:
25545break;
25546case Arg::Addr:
25547case Arg::Stack:
25548case Arg::CallArg:
25549#if CPU(X86_64)
25550OPGEN_RETURN(true);
25551#endif
25552break;
25553break;
25554default:
25555break;
25556}
25557break;
25558case Arg::Addr:
25559case Arg::Stack:
25560case Arg::CallArg:
25561break;
25562case Arg::Index:
25563break;
25564default:
25565break;
25566}
25567break;
25568default:
25569break;
25570}
25571break;
25572default:
25573break;
25574}
25575break;
25576case Opcode::BranchTest8:
25577switch (argIndex) {
25578case 0:
25579OPGEN_RETURN(false);
25580break;
25581case 1:
25582switch (args[0].kind()) {
25583case Arg::ResCond:
25584switch (Arg::Addr) {
25585case Arg::Addr:
25586case Arg::Stack:
25587case Arg::CallArg:
25588switch (args[2].kind()) {
25589case Arg::BitImm:
25590#if CPU(X86) || CPU(X86_64)
25591OPGEN_RETURN(true);
25592#endif
25593break;
25594break;
25595default:
25596break;
25597}
25598break;
25599case Arg::Index:
25600break;
25601default:
25602break;
25603}
25604break;
25605default:
25606break;
25607}
25608break;
25609case 2:
25610OPGEN_RETURN(false);
25611break;
25612default:
25613break;
25614}
25615break;
25616case Opcode::BranchTest32:
25617switch (argIndex) {
25618case 0:
25619OPGEN_RETURN(false);
25620break;
25621case 1:
25622switch (args[0].kind()) {
25623case Arg::ResCond:
25624switch (Arg::Addr) {
25625case Arg::Tmp:
25626break;
25627case Arg::Addr:
25628case Arg::Stack:
25629case Arg::CallArg:
25630switch (args[2].kind()) {
25631case Arg::BitImm:
25632#if CPU(X86) || CPU(X86_64)
25633OPGEN_RETURN(true);
25634#endif
25635break;
25636break;
25637default:
25638break;
25639}
25640break;
25641case Arg::Index:
25642break;
25643default:
25644break;
25645}
25646break;
25647default:
25648break;
25649}
25650break;
25651case 2:
25652OPGEN_RETURN(false);
25653break;
25654default:
25655break;
25656}
25657break;
25658case Opcode::BranchTest64:
25659switch (argIndex) {
25660case 0:
25661OPGEN_RETURN(false);
25662break;
25663case 1:
25664switch (args[0].kind()) {
25665case Arg::ResCond:
25666switch (Arg::Addr) {
25667case Arg::Tmp:
25668break;
25669case Arg::Addr:
25670case Arg::Stack:
25671case Arg::CallArg:
25672switch (args[2].kind()) {
25673case Arg::BitImm:
25674#if CPU(X86_64)
25675OPGEN_RETURN(true);
25676#endif
25677break;
25678break;
25679case Arg::Tmp:
25680#if CPU(X86_64)
25681OPGEN_RETURN(true);
25682#endif
25683break;
25684break;
25685default:
25686break;
25687}
25688break;
25689case Arg::Index:
25690break;
25691default:
25692break;
25693}
25694break;
25695default:
25696break;
25697}
25698break;
25699case 2:
25700OPGEN_RETURN(false);
25701break;
25702default:
25703break;
25704}
25705break;
25706case Opcode::BranchTestBit64:
25707switch (argIndex) {
25708case 0:
25709OPGEN_RETURN(false);
25710break;
25711case 1:
25712switch (args[0].kind()) {
25713case Arg::ResCond:
25714switch (Arg::Addr) {
25715case Arg::Tmp:
25716break;
25717case Arg::Addr:
25718case Arg::Stack:
25719case Arg::CallArg:
25720switch (args[2].kind()) {
25721case Arg::Imm:
25722#if CPU(X86_64)
25723OPGEN_RETURN(true);
25724#endif
25725break;
25726break;
25727default:
25728break;
25729}
25730break;
25731default:
25732break;
25733}
25734break;
25735default:
25736break;
25737}
25738break;
25739case 2:
25740OPGEN_RETURN(false);
25741break;
25742default:
25743break;
25744}
25745break;
25746case Opcode::BranchTestBit32:
25747switch (argIndex) {
25748case 0:
25749OPGEN_RETURN(false);
25750break;
25751case 1:
25752switch (args[0].kind()) {
25753case Arg::ResCond:
25754switch (Arg::Addr) {
25755case Arg::Tmp:
25756break;
25757case Arg::Addr:
25758case Arg::Stack:
25759case Arg::CallArg:
25760switch (args[2].kind()) {
25761case Arg::Imm:
25762#if CPU(X86) || CPU(X86_64)
25763OPGEN_RETURN(true);
25764#endif
25765break;
25766break;
25767default:
25768break;
25769}
25770break;
25771default:
25772break;
25773}
25774break;
25775default:
25776break;
25777}
25778break;
25779case 2:
25780OPGEN_RETURN(false);
25781break;
25782default:
25783break;
25784}
25785break;
25786case Opcode::BranchDouble:
25787switch (argIndex) {
25788case 0:
25789OPGEN_RETURN(false);
25790break;
25791case 1:
25792OPGEN_RETURN(false);
25793break;
25794case 2:
25795OPGEN_RETURN(false);
25796break;
25797default:
25798break;
25799}
25800break;
25801case Opcode::BranchFloat:
25802switch (argIndex) {
25803case 0:
25804OPGEN_RETURN(false);
25805break;
25806case 1:
25807OPGEN_RETURN(false);
25808break;
25809case 2:
25810OPGEN_RETURN(false);
25811break;
25812default:
25813break;
25814}
25815break;
25816case Opcode::BranchAdd32:
25817switch (argIndex) {
25818case 0:
25819OPGEN_RETURN(false);
25820break;
25821case 1:
25822switch (args.size()) {
25823case 4:
25824switch (args[0].kind()) {
25825case Arg::ResCond:
25826switch (Arg::Addr) {
25827case Arg::Tmp:
25828break;
25829case Arg::Addr:
25830case Arg::Stack:
25831case Arg::CallArg:
25832switch (args[2].kind()) {
25833case Arg::Tmp:
25834switch (args[3].kind()) {
25835case Arg::Tmp:
25836#if CPU(X86) || CPU(X86_64)
25837OPGEN_RETURN(true);
25838#endif
25839break;
25840break;
25841default:
25842break;
25843}
25844break;
25845default:
25846break;
25847}
25848break;
25849default:
25850break;
25851}
25852break;
25853default:
25854break;
25855}
25856break;
25857case 3:
25858switch (args[0].kind()) {
25859case Arg::ResCond:
25860switch (Arg::Addr) {
25861case Arg::Tmp:
25862break;
25863case Arg::Imm:
25864break;
25865case Arg::Addr:
25866case Arg::Stack:
25867case Arg::CallArg:
25868switch (args[2].kind()) {
25869case Arg::Tmp:
25870#if CPU(X86) || CPU(X86_64)
25871OPGEN_RETURN(true);
25872#endif
25873break;
25874break;
25875default:
25876break;
25877}
25878break;
25879default:
25880break;
25881}
25882break;
25883default:
25884break;
25885}
25886break;
25887default:
25888break;
25889}
25890break;
25891case 2:
25892switch (args.size()) {
25893case 4:
25894switch (args[0].kind()) {
25895case Arg::ResCond:
25896switch (args[1].kind()) {
25897case Arg::Tmp:
25898switch (Arg::Addr) {
25899case Arg::Tmp:
25900break;
25901case Arg::Addr:
25902case Arg::Stack:
25903case Arg::CallArg:
25904switch (args[3].kind()) {
25905case Arg::Tmp:
25906#if CPU(X86) || CPU(X86_64)
25907OPGEN_RETURN(true);
25908#endif
25909break;
25910break;
25911default:
25912break;
25913}
25914break;
25915default:
25916break;
25917}
25918break;
25919case Arg::Addr:
25920case Arg::Stack:
25921case Arg::CallArg:
25922break;
25923default:
25924break;
25925}
25926break;
25927default:
25928break;
25929}
25930break;
25931case 3:
25932switch (args[0].kind()) {
25933case Arg::ResCond:
25934switch (args[1].kind()) {
25935case Arg::Tmp:
25936switch (Arg::Addr) {
25937case Arg::Tmp:
25938break;
25939case Arg::Addr:
25940case Arg::Stack:
25941case Arg::CallArg:
25942#if CPU(X86) || CPU(X86_64)
25943OPGEN_RETURN(true);
25944#endif
25945break;
25946break;
25947default:
25948break;
25949}
25950break;
25951case Arg::Imm:
25952switch (Arg::Addr) {
25953case Arg::Tmp:
25954break;
25955case Arg::Addr:
25956case Arg::Stack:
25957case Arg::CallArg:
25958#if CPU(X86) || CPU(X86_64)
25959OPGEN_RETURN(true);
25960#endif
25961break;
25962break;
25963default:
25964break;
25965}
25966break;
25967case Arg::Addr:
25968case Arg::Stack:
25969case Arg::CallArg:
25970break;
25971default:
25972break;
25973}
25974break;
25975default:
25976break;
25977}
25978break;
25979default:
25980break;
25981}
25982break;
25983case 3:
25984OPGEN_RETURN(false);
25985break;
25986default:
25987break;
25988}
25989break;
25990case Opcode::BranchAdd64:
25991switch (argIndex) {
25992case 0:
25993OPGEN_RETURN(false);
25994break;
25995case 1:
25996switch (args.size()) {
25997case 4:
25998switch (args[0].kind()) {
25999case Arg::ResCond:
26000switch (Arg::Addr) {
26001case Arg::Tmp:
26002break;
26003case Arg::Addr:
26004case Arg::Stack:
26005case Arg::CallArg:
26006switch (args[2].kind()) {
26007case Arg::Tmp:
26008switch (args[3].kind()) {
26009case Arg::Tmp:
26010#if CPU(X86) || CPU(X86_64)
26011OPGEN_RETURN(true);
26012#endif
26013break;
26014break;
26015default:
26016break;
26017}
26018break;
26019default:
26020break;
26021}
26022break;
26023default:
26024break;
26025}
26026break;
26027default:
26028break;
26029}
26030break;
26031case 3:
26032switch (args[0].kind()) {
26033case Arg::ResCond:
26034switch (Arg::Addr) {
26035case Arg::Imm:
26036break;
26037case Arg::Tmp:
26038break;
26039case Arg::Addr:
26040case Arg::Stack:
26041case Arg::CallArg:
26042switch (args[2].kind()) {
26043case Arg::Tmp:
26044#if CPU(X86_64)
26045OPGEN_RETURN(true);
26046#endif
26047break;
26048break;
26049default:
26050break;
26051}
26052break;
26053default:
26054break;
26055}
26056break;
26057default:
26058break;
26059}
26060break;
26061default:
26062break;
26063}
26064break;
26065case 2:
26066switch (args.size()) {
26067case 4:
26068switch (args[0].kind()) {
26069case Arg::ResCond:
26070switch (args[1].kind()) {
26071case Arg::Tmp:
26072switch (Arg::Addr) {
26073case Arg::Tmp:
26074break;
26075case Arg::Addr:
26076case Arg::Stack:
26077case Arg::CallArg:
26078switch (args[3].kind()) {
26079case Arg::Tmp:
26080#if CPU(X86) || CPU(X86_64)
26081OPGEN_RETURN(true);
26082#endif
26083break;
26084break;
26085default:
26086break;
26087}
26088break;
26089default:
26090break;
26091}
26092break;
26093case Arg::Addr:
26094case Arg::Stack:
26095case Arg::CallArg:
26096break;
26097default:
26098break;
26099}
26100break;
26101default:
26102break;
26103}
26104break;
26105default:
26106break;
26107}
26108break;
26109case 3:
26110OPGEN_RETURN(false);
26111break;
26112default:
26113break;
26114}
26115break;
26116case Opcode::BranchMul32:
26117switch (argIndex) {
26118case 0:
26119OPGEN_RETURN(false);
26120break;
26121case 1:
26122switch (args.size()) {
26123case 3:
26124switch (args[0].kind()) {
26125case Arg::ResCond:
26126switch (Arg::Addr) {
26127case Arg::Tmp:
26128break;
26129case Arg::Addr:
26130case Arg::Stack:
26131case Arg::CallArg:
26132switch (args[2].kind()) {
26133case Arg::Tmp:
26134#if CPU(X86) || CPU(X86_64)
26135OPGEN_RETURN(true);
26136#endif
26137break;
26138break;
26139default:
26140break;
26141}
26142break;
26143default:
26144break;
26145}
26146break;
26147default:
26148break;
26149}
26150break;
26151default:
26152break;
26153}
26154break;
26155case 2:
26156OPGEN_RETURN(false);
26157break;
26158case 3:
26159OPGEN_RETURN(false);
26160break;
26161case 4:
26162OPGEN_RETURN(false);
26163break;
26164case 5:
26165OPGEN_RETURN(false);
26166break;
26167default:
26168break;
26169}
26170break;
26171case Opcode::BranchMul64:
26172switch (argIndex) {
26173case 0:
26174OPGEN_RETURN(false);
26175break;
26176case 1:
26177OPGEN_RETURN(false);
26178break;
26179case 2:
26180OPGEN_RETURN(false);
26181break;
26182case 3:
26183OPGEN_RETURN(false);
26184break;
26185case 4:
26186OPGEN_RETURN(false);
26187break;
26188case 5:
26189OPGEN_RETURN(false);
26190break;
26191default:
26192break;
26193}
26194break;
26195case Opcode::BranchSub32:
26196switch (argIndex) {
26197case 0:
26198OPGEN_RETURN(false);
26199break;
26200case 1:
26201switch (args[0].kind()) {
26202case Arg::ResCond:
26203switch (Arg::Addr) {
26204case Arg::Tmp:
26205break;
26206case Arg::Imm:
26207break;
26208case Arg::Addr:
26209case Arg::Stack:
26210case Arg::CallArg:
26211switch (args[2].kind()) {
26212case Arg::Tmp:
26213#if CPU(X86) || CPU(X86_64)
26214OPGEN_RETURN(true);
26215#endif
26216break;
26217break;
26218default:
26219break;
26220}
26221break;
26222default:
26223break;
26224}
26225break;
26226default:
26227break;
26228}
26229break;
26230case 2:
26231switch (args[0].kind()) {
26232case Arg::ResCond:
26233switch (args[1].kind()) {
26234case Arg::Tmp:
26235switch (Arg::Addr) {
26236case Arg::Tmp:
26237break;
26238case Arg::Addr:
26239case Arg::Stack:
26240case Arg::CallArg:
26241#if CPU(X86) || CPU(X86_64)
26242OPGEN_RETURN(true);
26243#endif
26244break;
26245break;
26246default:
26247break;
26248}
26249break;
26250case Arg::Imm:
26251switch (Arg::Addr) {
26252case Arg::Tmp:
26253break;
26254case Arg::Addr:
26255case Arg::Stack:
26256case Arg::CallArg:
26257#if CPU(X86) || CPU(X86_64)
26258OPGEN_RETURN(true);
26259#endif
26260break;
26261break;
26262default:
26263break;
26264}
26265break;
26266case Arg::Addr:
26267case Arg::Stack:
26268case Arg::CallArg:
26269break;
26270default:
26271break;
26272}
26273break;
26274default:
26275break;
26276}
26277break;
26278default:
26279break;
26280}
26281break;
26282case Opcode::BranchSub64:
26283switch (argIndex) {
26284case 0:
26285OPGEN_RETURN(false);
26286break;
26287case 1:
26288OPGEN_RETURN(false);
26289break;
26290case 2:
26291OPGEN_RETURN(false);
26292break;
26293default:
26294break;
26295}
26296break;
26297case Opcode::BranchNeg32:
26298switch (argIndex) {
26299case 0:
26300OPGEN_RETURN(false);
26301break;
26302case 1:
26303OPGEN_RETURN(false);
26304break;
26305default:
26306break;
26307}
26308break;
26309case Opcode::BranchNeg64:
26310switch (argIndex) {
26311case 0:
26312OPGEN_RETURN(false);
26313break;
26314case 1:
26315OPGEN_RETURN(false);
26316break;
26317default:
26318break;
26319}
26320break;
26321case Opcode::MoveConditionally32:
26322switch (argIndex) {
26323case 0:
26324OPGEN_RETURN(false);
26325break;
26326case 1:
26327OPGEN_RETURN(false);
26328break;
26329case 2:
26330OPGEN_RETURN(false);
26331break;
26332case 3:
26333OPGEN_RETURN(false);
26334break;
26335case 4:
26336OPGEN_RETURN(false);
26337break;
26338case 5:
26339OPGEN_RETURN(false);
26340break;
26341default:
26342break;
26343}
26344break;
26345case Opcode::MoveConditionally64:
26346switch (argIndex) {
26347case 0:
26348OPGEN_RETURN(false);
26349break;
26350case 1:
26351OPGEN_RETURN(false);
26352break;
26353case 2:
26354OPGEN_RETURN(false);
26355break;
26356case 3:
26357OPGEN_RETURN(false);
26358break;
26359case 4:
26360OPGEN_RETURN(false);
26361break;
26362case 5:
26363OPGEN_RETURN(false);
26364break;
26365default:
26366break;
26367}
26368break;
26369case Opcode::MoveConditionallyTest32:
26370switch (argIndex) {
26371case 0:
26372OPGEN_RETURN(false);
26373break;
26374case 1:
26375OPGEN_RETURN(false);
26376break;
26377case 2:
26378OPGEN_RETURN(false);
26379break;
26380case 3:
26381OPGEN_RETURN(false);
26382break;
26383case 4:
26384OPGEN_RETURN(false);
26385break;
26386case 5:
26387OPGEN_RETURN(false);
26388break;
26389default:
26390break;
26391}
26392break;
26393case Opcode::MoveConditionallyTest64:
26394switch (argIndex) {
26395case 0:
26396OPGEN_RETURN(false);
26397break;
26398case 1:
26399OPGEN_RETURN(false);
26400break;
26401case 2:
26402OPGEN_RETURN(false);
26403break;
26404case 3:
26405OPGEN_RETURN(false);
26406break;
26407case 4:
26408OPGEN_RETURN(false);
26409break;
26410case 5:
26411OPGEN_RETURN(false);
26412break;
26413default:
26414break;
26415}
26416break;
26417case Opcode::MoveConditionallyDouble:
26418switch (argIndex) {
26419case 0:
26420OPGEN_RETURN(false);
26421break;
26422case 1:
26423OPGEN_RETURN(false);
26424break;
26425case 2:
26426OPGEN_RETURN(false);
26427break;
26428case 3:
26429OPGEN_RETURN(false);
26430break;
26431case 4:
26432OPGEN_RETURN(false);
26433break;
26434case 5:
26435OPGEN_RETURN(false);
26436break;
26437default:
26438break;
26439}
26440break;
26441case Opcode::MoveConditionallyFloat:
26442switch (argIndex) {
26443case 0:
26444OPGEN_RETURN(false);
26445break;
26446case 1:
26447OPGEN_RETURN(false);
26448break;
26449case 2:
26450OPGEN_RETURN(false);
26451break;
26452case 3:
26453OPGEN_RETURN(false);
26454break;
26455case 4:
26456OPGEN_RETURN(false);
26457break;
26458case 5:
26459OPGEN_RETURN(false);
26460break;
26461default:
26462break;
26463}
26464break;
26465case Opcode::MoveDoubleConditionally32:
26466switch (argIndex) {
26467case 0:
26468OPGEN_RETURN(false);
26469break;
26470case 1:
26471switch (args[0].kind()) {
26472case Arg::RelCond:
26473switch (Arg::Addr) {
26474case Arg::Tmp:
26475break;
26476case Arg::Addr:
26477case Arg::Stack:
26478case Arg::CallArg:
26479switch (args[2].kind()) {
26480case Arg::Imm:
26481switch (args[3].kind()) {
26482case Arg::Tmp:
26483switch (args[4].kind()) {
26484case Arg::Tmp:
26485switch (args[5].kind()) {
26486case Arg::Tmp:
26487#if CPU(X86) || CPU(X86_64)
26488OPGEN_RETURN(true);
26489#endif
26490break;
26491break;
26492default:
26493break;
26494}
26495break;
26496default:
26497break;
26498}
26499break;
26500default:
26501break;
26502}
26503break;
26504case Arg::Tmp:
26505switch (args[3].kind()) {
26506case Arg::Tmp:
26507switch (args[4].kind()) {
26508case Arg::Tmp:
26509switch (args[5].kind()) {
26510case Arg::Tmp:
26511#if CPU(X86) || CPU(X86_64)
26512OPGEN_RETURN(true);
26513#endif
26514break;
26515break;
26516default:
26517break;
26518}
26519break;
26520default:
26521break;
26522}
26523break;
26524default:
26525break;
26526}
26527break;
26528default:
26529break;
26530}
26531break;
26532case Arg::Index:
26533break;
26534default:
26535break;
26536}
26537break;
26538default:
26539break;
26540}
26541break;
26542case 2:
26543switch (args[0].kind()) {
26544case Arg::RelCond:
26545switch (args[1].kind()) {
26546case Arg::Tmp:
26547switch (Arg::Addr) {
26548case Arg::Tmp:
26549break;
26550case Arg::Imm:
26551break;
26552case Arg::Addr:
26553case Arg::Stack:
26554case Arg::CallArg:
26555switch (args[3].kind()) {
26556case Arg::Tmp:
26557switch (args[4].kind()) {
26558case Arg::Tmp:
26559switch (args[5].kind()) {
26560case Arg::Tmp:
26561#if CPU(X86) || CPU(X86_64)
26562OPGEN_RETURN(true);
26563#endif
26564break;
26565break;
26566default:
26567break;
26568}
26569break;
26570default:
26571break;
26572}
26573break;
26574default:
26575break;
26576}
26577break;
26578default:
26579break;
26580}
26581break;
26582case Arg::Addr:
26583case Arg::Stack:
26584case Arg::CallArg:
26585break;
26586case Arg::Index:
26587break;
26588default:
26589break;
26590}
26591break;
26592default:
26593break;
26594}
26595break;
26596case 3:
26597OPGEN_RETURN(false);
26598break;
26599case 4:
26600OPGEN_RETURN(false);
26601break;
26602case 5:
26603OPGEN_RETURN(false);
26604break;
26605default:
26606break;
26607}
26608break;
26609case Opcode::MoveDoubleConditionally64:
26610switch (argIndex) {
26611case 0:
26612OPGEN_RETURN(false);
26613break;
26614case 1:
26615switch (args[0].kind()) {
26616case Arg::RelCond:
26617switch (Arg::Addr) {
26618case Arg::Tmp:
26619break;
26620case Arg::Addr:
26621case Arg::Stack:
26622case Arg::CallArg:
26623switch (args[2].kind()) {
26624case Arg::Tmp:
26625switch (args[3].kind()) {
26626case Arg::Tmp:
26627switch (args[4].kind()) {
26628case Arg::Tmp:
26629switch (args[5].kind()) {
26630case Arg::Tmp:
26631#if CPU(X86_64)
26632OPGEN_RETURN(true);
26633#endif
26634break;
26635break;
26636default:
26637break;
26638}
26639break;
26640default:
26641break;
26642}
26643break;
26644default:
26645break;
26646}
26647break;
26648case Arg::Imm:
26649switch (args[3].kind()) {
26650case Arg::Tmp:
26651switch (args[4].kind()) {
26652case Arg::Tmp:
26653switch (args[5].kind()) {
26654case Arg::Tmp:
26655#if CPU(X86_64)
26656OPGEN_RETURN(true);
26657#endif
26658break;
26659break;
26660default:
26661break;
26662}
26663break;
26664default:
26665break;
26666}
26667break;
26668default:
26669break;
26670}
26671break;
26672default:
26673break;
26674}
26675break;
26676case Arg::Index:
26677break;
26678default:
26679break;
26680}
26681break;
26682default:
26683break;
26684}
26685break;
26686case 2:
26687switch (args[0].kind()) {
26688case Arg::RelCond:
26689switch (args[1].kind()) {
26690case Arg::Tmp:
26691switch (Arg::Addr) {
26692case Arg::Tmp:
26693break;
26694case Arg::Imm:
26695break;
26696case Arg::Addr:
26697case Arg::Stack:
26698case Arg::CallArg:
26699switch (args[3].kind()) {
26700case Arg::Tmp:
26701switch (args[4].kind()) {
26702case Arg::Tmp:
26703switch (args[5].kind()) {
26704case Arg::Tmp:
26705#if CPU(X86_64)
26706OPGEN_RETURN(true);
26707#endif
26708break;
26709break;
26710default:
26711break;
26712}
26713break;
26714default:
26715break;
26716}
26717break;
26718default:
26719break;
26720}
26721break;
26722default:
26723break;
26724}
26725break;
26726case Arg::Addr:
26727case Arg::Stack:
26728case Arg::CallArg:
26729break;
26730case Arg::Index:
26731break;
26732default:
26733break;
26734}
26735break;
26736default:
26737break;
26738}
26739break;
26740case 3:
26741OPGEN_RETURN(false);
26742break;
26743case 4:
26744OPGEN_RETURN(false);
26745break;
26746case 5:
26747OPGEN_RETURN(false);
26748break;
26749default:
26750break;
26751}
26752break;
26753case Opcode::MoveDoubleConditionallyTest32:
26754switch (argIndex) {
26755case 0:
26756OPGEN_RETURN(false);
26757break;
26758case 1:
26759switch (args[0].kind()) {
26760case Arg::ResCond:
26761switch (Arg::Addr) {
26762case Arg::Tmp:
26763break;
26764case Arg::Addr:
26765case Arg::Stack:
26766case Arg::CallArg:
26767switch (args[2].kind()) {
26768case Arg::Imm:
26769switch (args[3].kind()) {
26770case Arg::Tmp:
26771switch (args[4].kind()) {
26772case Arg::Tmp:
26773switch (args[5].kind()) {
26774case Arg::Tmp:
26775#if CPU(X86) || CPU(X86_64)
26776OPGEN_RETURN(true);
26777#endif
26778break;
26779break;
26780default:
26781break;
26782}
26783break;
26784default:
26785break;
26786}
26787break;
26788default:
26789break;
26790}
26791break;
26792default:
26793break;
26794}
26795break;
26796case Arg::Index:
26797break;
26798default:
26799break;
26800}
26801break;
26802default:
26803break;
26804}
26805break;
26806case 2:
26807OPGEN_RETURN(false);
26808break;
26809case 3:
26810OPGEN_RETURN(false);
26811break;
26812case 4:
26813OPGEN_RETURN(false);
26814break;
26815case 5:
26816OPGEN_RETURN(false);
26817break;
26818default:
26819break;
26820}
26821break;
26822case Opcode::MoveDoubleConditionallyTest64:
26823switch (argIndex) {
26824case 0:
26825OPGEN_RETURN(false);
26826break;
26827case 1:
26828switch (args[0].kind()) {
26829case Arg::ResCond:
26830switch (Arg::Addr) {
26831case Arg::Tmp:
26832break;
26833case Arg::Addr:
26834case Arg::Stack:
26835case Arg::CallArg:
26836switch (args[2].kind()) {
26837case Arg::Imm:
26838switch (args[3].kind()) {
26839case Arg::Tmp:
26840switch (args[4].kind()) {
26841case Arg::Tmp:
26842switch (args[5].kind()) {
26843case Arg::Tmp:
26844#if CPU(X86_64)
26845OPGEN_RETURN(true);
26846#endif
26847break;
26848break;
26849default:
26850break;
26851}
26852break;
26853default:
26854break;
26855}
26856break;
26857default:
26858break;
26859}
26860break;
26861case Arg::Tmp:
26862switch (args[3].kind()) {
26863case Arg::Tmp:
26864switch (args[4].kind()) {
26865case Arg::Tmp:
26866switch (args[5].kind()) {
26867case Arg::Tmp:
26868#if CPU(X86_64)
26869OPGEN_RETURN(true);
26870#endif
26871break;
26872break;
26873default:
26874break;
26875}
26876break;
26877default:
26878break;
26879}
26880break;
26881default:
26882break;
26883}
26884break;
26885default:
26886break;
26887}
26888break;
26889case Arg::Index:
26890break;
26891default:
26892break;
26893}
26894break;
26895default:
26896break;
26897}
26898break;
26899case 2:
26900OPGEN_RETURN(false);
26901break;
26902case 3:
26903OPGEN_RETURN(false);
26904break;
26905case 4:
26906OPGEN_RETURN(false);
26907break;
26908case 5:
26909OPGEN_RETURN(false);
26910break;
26911default:
26912break;
26913}
26914break;
26915case Opcode::MoveDoubleConditionallyDouble:
26916switch (argIndex) {
26917case 0:
26918OPGEN_RETURN(false);
26919break;
26920case 1:
26921OPGEN_RETURN(false);
26922break;
26923case 2:
26924OPGEN_RETURN(false);
26925break;
26926case 3:
26927OPGEN_RETURN(false);
26928break;
26929case 4:
26930OPGEN_RETURN(false);
26931break;
26932case 5:
26933OPGEN_RETURN(false);
26934break;
26935default:
26936break;
26937}
26938break;
26939case Opcode::MoveDoubleConditionallyFloat:
26940switch (argIndex) {
26941case 0:
26942OPGEN_RETURN(false);
26943break;
26944case 1:
26945OPGEN_RETURN(false);
26946break;
26947case 2:
26948OPGEN_RETURN(false);
26949break;
26950case 3:
26951OPGEN_RETURN(false);
26952break;
26953case 4:
26954OPGEN_RETURN(false);
26955break;
26956case 5:
26957OPGEN_RETURN(false);
26958break;
26959default:
26960break;
26961}
26962break;
26963case Opcode::MemoryFence:
26964switch (argIndex) {
26965default:
26966break;
26967}
26968break;
26969case Opcode::StoreFence:
26970switch (argIndex) {
26971default:
26972break;
26973}
26974break;
26975case Opcode::LoadFence:
26976switch (argIndex) {
26977default:
26978break;
26979}
26980break;
26981case Opcode::Jump:
26982switch (argIndex) {
26983default:
26984break;
26985}
26986break;
26987case Opcode::RetVoid:
26988switch (argIndex) {
26989default:
26990break;
26991}
26992break;
26993case Opcode::Ret32:
26994switch (argIndex) {
26995case 0:
26996OPGEN_RETURN(false);
26997break;
26998default:
26999break;
27000}
27001break;
27002case Opcode::Ret64:
27003switch (argIndex) {
27004case 0:
27005OPGEN_RETURN(false);
27006break;
27007default:
27008break;
27009}
27010break;
27011case Opcode::RetFloat:
27012switch (argIndex) {
27013case 0:
27014OPGEN_RETURN(false);
27015break;
27016default:
27017break;
27018}
27019break;
27020case Opcode::RetDouble:
27021switch (argIndex) {
27022case 0:
27023OPGEN_RETURN(false);
27024break;
27025default:
27026break;
27027}
27028break;
27029case Opcode::Oops:
27030switch (argIndex) {
27031default:
27032break;
27033}
27034break;
27035case Opcode::EntrySwitch:
27036OPGEN_RETURN(EntrySwitchCustom::admitsStack(*this, argIndex));
27037break;
27038case Opcode::Shuffle:
27039OPGEN_RETURN(ShuffleCustom::admitsStack(*this, argIndex));
27040break;
27041case Opcode::Patch:
27042OPGEN_RETURN(PatchCustom::admitsStack(*this, argIndex));
27043break;
27044case Opcode::CCall:
27045OPGEN_RETURN(CCallCustom::admitsStack(*this, argIndex));
27046break;
27047case Opcode::ColdCCall:
27048OPGEN_RETURN(ColdCCallCustom::admitsStack(*this, argIndex));
27049break;
27050case Opcode::WasmBoundsCheck:
27051OPGEN_RETURN(WasmBoundsCheckCustom::admitsStack(*this, argIndex));
27052break;
27053default:
27054break;
27055}
27056return false;
27057}
27058bool Inst::admitsExtendedOffsetAddr(unsigned argIndex)
27059{
27060switch (kind.opcode) {
27061case Opcode::EntrySwitch:
27062OPGEN_RETURN(EntrySwitchCustom::admitsExtendedOffsetAddr(*this, argIndex));
27063break;
27064case Opcode::Shuffle:
27065OPGEN_RETURN(ShuffleCustom::admitsExtendedOffsetAddr(*this, argIndex));
27066break;
27067case Opcode::Patch:
27068OPGEN_RETURN(PatchCustom::admitsExtendedOffsetAddr(*this, argIndex));
27069break;
27070case Opcode::CCall:
27071OPGEN_RETURN(CCallCustom::admitsExtendedOffsetAddr(*this, argIndex));
27072break;
27073case Opcode::ColdCCall:
27074OPGEN_RETURN(ColdCCallCustom::admitsExtendedOffsetAddr(*this, argIndex));
27075break;
27076case Opcode::WasmBoundsCheck:
27077OPGEN_RETURN(WasmBoundsCheckCustom::admitsExtendedOffsetAddr(*this, argIndex));
27078break;
27079default:
27080break;
27081}
27082return false;
27083}
27084bool Inst::isTerminal()
27085{
27086switch (kind.opcode) {
27087case Opcode::BranchAtomicStrongCAS8:
27088case Opcode::BranchAtomicStrongCAS16:
27089case Opcode::BranchAtomicStrongCAS32:
27090case Opcode::BranchAtomicStrongCAS64:
27091case Opcode::Branch8:
27092case Opcode::Branch32:
27093case Opcode::Branch64:
27094case Opcode::BranchTest8:
27095case Opcode::BranchTest32:
27096case Opcode::BranchTest64:
27097case Opcode::BranchTestBit64:
27098case Opcode::BranchTestBit32:
27099case Opcode::BranchDouble:
27100case Opcode::BranchFloat:
27101case Opcode::BranchAdd32:
27102case Opcode::BranchAdd64:
27103case Opcode::BranchMul32:
27104case Opcode::BranchMul64:
27105case Opcode::BranchSub32:
27106case Opcode::BranchSub64:
27107case Opcode::BranchNeg32:
27108case Opcode::BranchNeg64:
27109case Opcode::Jump:
27110case Opcode::RetVoid:
27111case Opcode::Ret32:
27112case Opcode::Ret64:
27113case Opcode::RetFloat:
27114case Opcode::RetDouble:
27115case Opcode::Oops:
27116return true;
27117case Opcode::EntrySwitch:
27118return EntrySwitchCustom::isTerminal(*this);
27119case Opcode::Shuffle:
27120return ShuffleCustom::isTerminal(*this);
27121case Opcode::Patch:
27122return PatchCustom::isTerminal(*this);
27123case Opcode::CCall:
27124return CCallCustom::isTerminal(*this);
27125case Opcode::ColdCCall:
27126return ColdCCallCustom::isTerminal(*this);
27127case Opcode::WasmBoundsCheck:
27128return WasmBoundsCheckCustom::isTerminal(*this);
27129default:
27130return false;
27131}
27132}
27133bool Inst::hasNonArgNonControlEffects()
27134{
27135if (kind.effects)
27136return true;
27137switch (kind.opcode) {
27138case Opcode::LoadAcq8:
27139case Opcode::StoreRel8:
27140case Opcode::LoadAcq8SignedExtendTo32:
27141case Opcode::LoadAcq16:
27142case Opcode::LoadAcq16SignedExtendTo32:
27143case Opcode::StoreRel16:
27144case Opcode::LoadAcq32:
27145case Opcode::StoreRel32:
27146case Opcode::LoadAcq64:
27147case Opcode::StoreRel64:
27148case Opcode::Xchg8:
27149case Opcode::Xchg16:
27150case Opcode::Xchg32:
27151case Opcode::Xchg64:
27152case Opcode::AtomicStrongCAS8:
27153case Opcode::AtomicStrongCAS16:
27154case Opcode::AtomicStrongCAS32:
27155case Opcode::AtomicStrongCAS64:
27156case Opcode::BranchAtomicStrongCAS8:
27157case Opcode::BranchAtomicStrongCAS16:
27158case Opcode::BranchAtomicStrongCAS32:
27159case Opcode::BranchAtomicStrongCAS64:
27160case Opcode::AtomicAdd8:
27161case Opcode::AtomicAdd16:
27162case Opcode::AtomicAdd32:
27163case Opcode::AtomicAdd64:
27164case Opcode::AtomicSub8:
27165case Opcode::AtomicSub16:
27166case Opcode::AtomicSub32:
27167case Opcode::AtomicSub64:
27168case Opcode::AtomicAnd8:
27169case Opcode::AtomicAnd16:
27170case Opcode::AtomicAnd32:
27171case Opcode::AtomicAnd64:
27172case Opcode::AtomicOr8:
27173case Opcode::AtomicOr16:
27174case Opcode::AtomicOr32:
27175case Opcode::AtomicOr64:
27176case Opcode::AtomicXor8:
27177case Opcode::AtomicXor16:
27178case Opcode::AtomicXor32:
27179case Opcode::AtomicXor64:
27180case Opcode::AtomicNeg8:
27181case Opcode::AtomicNeg16:
27182case Opcode::AtomicNeg32:
27183case Opcode::AtomicNeg64:
27184case Opcode::AtomicNot8:
27185case Opcode::AtomicNot16:
27186case Opcode::AtomicNot32:
27187case Opcode::AtomicNot64:
27188case Opcode::AtomicXchgAdd8:
27189case Opcode::AtomicXchgAdd16:
27190case Opcode::AtomicXchgAdd32:
27191case Opcode::AtomicXchgAdd64:
27192case Opcode::AtomicXchg8:
27193case Opcode::AtomicXchg16:
27194case Opcode::AtomicXchg32:
27195case Opcode::AtomicXchg64:
27196case Opcode::LoadLink8:
27197case Opcode::LoadLinkAcq8:
27198case Opcode::StoreCond8:
27199case Opcode::StoreCondRel8:
27200case Opcode::LoadLink16:
27201case Opcode::LoadLinkAcq16:
27202case Opcode::StoreCond16:
27203case Opcode::StoreCondRel16:
27204case Opcode::LoadLink32:
27205case Opcode::LoadLinkAcq32:
27206case Opcode::StoreCond32:
27207case Opcode::StoreCondRel32:
27208case Opcode::LoadLink64:
27209case Opcode::LoadLinkAcq64:
27210case Opcode::StoreCond64:
27211case Opcode::StoreCondRel64:
27212case Opcode::MemoryFence:
27213case Opcode::StoreFence:
27214case Opcode::LoadFence:
27215return true;
27216case Opcode::EntrySwitch:
27217return EntrySwitchCustom::hasNonArgNonControlEffects(*this);
27218case Opcode::Shuffle:
27219return ShuffleCustom::hasNonArgNonControlEffects(*this);
27220case Opcode::Patch:
27221return PatchCustom::hasNonArgNonControlEffects(*this);
27222case Opcode::CCall:
27223return CCallCustom::hasNonArgNonControlEffects(*this);
27224case Opcode::ColdCCall:
27225return ColdCCallCustom::hasNonArgNonControlEffects(*this);
27226case Opcode::WasmBoundsCheck:
27227return WasmBoundsCheckCustom::hasNonArgNonControlEffects(*this);
27228default:
27229return false;
27230}
27231}
27232bool Inst::hasNonArgEffects()
27233{
27234if (kind.effects)
27235return true;
27236switch (kind.opcode) {
27237case Opcode::LoadAcq8:
27238case Opcode::StoreRel8:
27239case Opcode::LoadAcq8SignedExtendTo32:
27240case Opcode::LoadAcq16:
27241case Opcode::LoadAcq16SignedExtendTo32:
27242case Opcode::StoreRel16:
27243case Opcode::LoadAcq32:
27244case Opcode::StoreRel32:
27245case Opcode::LoadAcq64:
27246case Opcode::StoreRel64:
27247case Opcode::Xchg8:
27248case Opcode::Xchg16:
27249case Opcode::Xchg32:
27250case Opcode::Xchg64:
27251case Opcode::AtomicStrongCAS8:
27252case Opcode::AtomicStrongCAS16:
27253case Opcode::AtomicStrongCAS32:
27254case Opcode::AtomicStrongCAS64:
27255case Opcode::BranchAtomicStrongCAS8:
27256case Opcode::BranchAtomicStrongCAS16:
27257case Opcode::BranchAtomicStrongCAS32:
27258case Opcode::BranchAtomicStrongCAS64:
27259case Opcode::AtomicAdd8:
27260case Opcode::AtomicAdd16:
27261case Opcode::AtomicAdd32:
27262case Opcode::AtomicAdd64:
27263case Opcode::AtomicSub8:
27264case Opcode::AtomicSub16:
27265case Opcode::AtomicSub32:
27266case Opcode::AtomicSub64:
27267case Opcode::AtomicAnd8:
27268case Opcode::AtomicAnd16:
27269case Opcode::AtomicAnd32:
27270case Opcode::AtomicAnd64:
27271case Opcode::AtomicOr8:
27272case Opcode::AtomicOr16:
27273case Opcode::AtomicOr32:
27274case Opcode::AtomicOr64:
27275case Opcode::AtomicXor8:
27276case Opcode::AtomicXor16:
27277case Opcode::AtomicXor32:
27278case Opcode::AtomicXor64:
27279case Opcode::AtomicNeg8:
27280case Opcode::AtomicNeg16:
27281case Opcode::AtomicNeg32:
27282case Opcode::AtomicNeg64:
27283case Opcode::AtomicNot8:
27284case Opcode::AtomicNot16:
27285case Opcode::AtomicNot32:
27286case Opcode::AtomicNot64:
27287case Opcode::AtomicXchgAdd8:
27288case Opcode::AtomicXchgAdd16:
27289case Opcode::AtomicXchgAdd32:
27290case Opcode::AtomicXchgAdd64:
27291case Opcode::AtomicXchg8:
27292case Opcode::AtomicXchg16:
27293case Opcode::AtomicXchg32:
27294case Opcode::AtomicXchg64:
27295case Opcode::LoadLink8:
27296case Opcode::LoadLinkAcq8:
27297case Opcode::StoreCond8:
27298case Opcode::StoreCondRel8:
27299case Opcode::LoadLink16:
27300case Opcode::LoadLinkAcq16:
27301case Opcode::StoreCond16:
27302case Opcode::StoreCondRel16:
27303case Opcode::LoadLink32:
27304case Opcode::LoadLinkAcq32:
27305case Opcode::StoreCond32:
27306case Opcode::StoreCondRel32:
27307case Opcode::LoadLink64:
27308case Opcode::LoadLinkAcq64:
27309case Opcode::StoreCond64:
27310case Opcode::StoreCondRel64:
27311case Opcode::Branch8:
27312case Opcode::Branch32:
27313case Opcode::Branch64:
27314case Opcode::BranchTest8:
27315case Opcode::BranchTest32:
27316case Opcode::BranchTest64:
27317case Opcode::BranchTestBit64:
27318case Opcode::BranchTestBit32:
27319case Opcode::BranchDouble:
27320case Opcode::BranchFloat:
27321case Opcode::BranchAdd32:
27322case Opcode::BranchAdd64:
27323case Opcode::BranchMul32:
27324case Opcode::BranchMul64:
27325case Opcode::BranchSub32:
27326case Opcode::BranchSub64:
27327case Opcode::BranchNeg32:
27328case Opcode::BranchNeg64:
27329case Opcode::MemoryFence:
27330case Opcode::StoreFence:
27331case Opcode::LoadFence:
27332case Opcode::Jump:
27333case Opcode::RetVoid:
27334case Opcode::Ret32:
27335case Opcode::Ret64:
27336case Opcode::RetFloat:
27337case Opcode::RetDouble:
27338case Opcode::Oops:
27339return true;
27340case Opcode::EntrySwitch:
27341return EntrySwitchCustom::hasNonArgEffects(*this);
27342case Opcode::Shuffle:
27343return ShuffleCustom::hasNonArgEffects(*this);
27344case Opcode::Patch:
27345return PatchCustom::hasNonArgEffects(*this);
27346case Opcode::CCall:
27347return CCallCustom::hasNonArgEffects(*this);
27348case Opcode::ColdCCall:
27349return ColdCCallCustom::hasNonArgEffects(*this);
27350case Opcode::WasmBoundsCheck:
27351return WasmBoundsCheckCustom::hasNonArgEffects(*this);
27352default:
27353return false;
27354}
27355}
27356CCallHelpers::Jump Inst::generate(CCallHelpers& jit, GenerationContext& context)
27357{
27358UNUSED_PARAM(jit);
27359UNUSED_PARAM(context);
27360CCallHelpers::Jump result;
27361switch (this->kind.opcode) {
27362case Opcode::Nop:
27363jit.nop();
27364OPGEN_RETURN(result);
27365break;
27366break;
27367case Opcode::Add32:
27368switch (this->args.size()) {
27369case 3:
27370switch (this->args[0].kind()) {
27371case Arg::Imm:
27372jit.add32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
27373OPGEN_RETURN(result);
27374break;
27375break;
27376case Arg::Tmp:
27377jit.add32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27378OPGEN_RETURN(result);
27379break;
27380break;
27381default:
27382break;
27383}
27384break;
27385case 2:
27386switch (this->args[0].kind()) {
27387case Arg::Tmp:
27388switch (this->args[1].kind()) {
27389case Arg::Tmp:
27390jit.add32(args[0].gpr(), args[1].gpr());
27391OPGEN_RETURN(result);
27392break;
27393break;
27394case Arg::Addr:
27395case Arg::Stack:
27396case Arg::CallArg:
27397#if CPU(X86) || CPU(X86_64)
27398jit.add32(args[0].gpr(), args[1].asAddress());
27399OPGEN_RETURN(result);
27400#endif
27401break;
27402break;
27403case Arg::Index:
27404#if CPU(X86) || CPU(X86_64)
27405jit.add32(args[0].gpr(), args[1].asBaseIndex());
27406OPGEN_RETURN(result);
27407#endif
27408break;
27409break;
27410default:
27411break;
27412}
27413break;
27414case Arg::Imm:
27415switch (this->args[1].kind()) {
27416case Arg::Addr:
27417case Arg::Stack:
27418case Arg::CallArg:
27419#if CPU(X86) || CPU(X86_64)
27420jit.add32(args[0].asTrustedImm32(), args[1].asAddress());
27421OPGEN_RETURN(result);
27422#endif
27423break;
27424break;
27425case Arg::Index:
27426#if CPU(X86) || CPU(X86_64)
27427jit.add32(args[0].asTrustedImm32(), args[1].asBaseIndex());
27428OPGEN_RETURN(result);
27429#endif
27430break;
27431break;
27432case Arg::Tmp:
27433jit.add32(args[0].asTrustedImm32(), args[1].gpr());
27434OPGEN_RETURN(result);
27435break;
27436break;
27437default:
27438break;
27439}
27440break;
27441case Arg::Addr:
27442case Arg::Stack:
27443case Arg::CallArg:
27444#if CPU(X86) || CPU(X86_64)
27445jit.add32(args[0].asAddress(), args[1].gpr());
27446OPGEN_RETURN(result);
27447#endif
27448break;
27449break;
27450case Arg::Index:
27451#if CPU(X86) || CPU(X86_64)
27452jit.add32(args[0].asBaseIndex(), args[1].gpr());
27453OPGEN_RETURN(result);
27454#endif
27455break;
27456break;
27457default:
27458break;
27459}
27460break;
27461default:
27462break;
27463}
27464break;
27465case Opcode::Add8:
27466switch (this->args[0].kind()) {
27467case Arg::Imm:
27468switch (this->args[1].kind()) {
27469case Arg::Addr:
27470case Arg::Stack:
27471case Arg::CallArg:
27472#if CPU(X86) || CPU(X86_64)
27473jit.add8(args[0].asTrustedImm32(), args[1].asAddress());
27474OPGEN_RETURN(result);
27475#endif
27476break;
27477break;
27478case Arg::Index:
27479#if CPU(X86) || CPU(X86_64)
27480jit.add8(args[0].asTrustedImm32(), args[1].asBaseIndex());
27481OPGEN_RETURN(result);
27482#endif
27483break;
27484break;
27485default:
27486break;
27487}
27488break;
27489case Arg::Tmp:
27490switch (this->args[1].kind()) {
27491case Arg::Addr:
27492case Arg::Stack:
27493case Arg::CallArg:
27494#if CPU(X86) || CPU(X86_64)
27495jit.add8(args[0].gpr(), args[1].asAddress());
27496OPGEN_RETURN(result);
27497#endif
27498break;
27499break;
27500case Arg::Index:
27501#if CPU(X86) || CPU(X86_64)
27502jit.add8(args[0].gpr(), args[1].asBaseIndex());
27503OPGEN_RETURN(result);
27504#endif
27505break;
27506break;
27507default:
27508break;
27509}
27510break;
27511default:
27512break;
27513}
27514break;
27515case Opcode::Add16:
27516switch (this->args[0].kind()) {
27517case Arg::Imm:
27518switch (this->args[1].kind()) {
27519case Arg::Addr:
27520case Arg::Stack:
27521case Arg::CallArg:
27522#if CPU(X86) || CPU(X86_64)
27523jit.add16(args[0].asTrustedImm32(), args[1].asAddress());
27524OPGEN_RETURN(result);
27525#endif
27526break;
27527break;
27528case Arg::Index:
27529#if CPU(X86) || CPU(X86_64)
27530jit.add16(args[0].asTrustedImm32(), args[1].asBaseIndex());
27531OPGEN_RETURN(result);
27532#endif
27533break;
27534break;
27535default:
27536break;
27537}
27538break;
27539case Arg::Tmp:
27540switch (this->args[1].kind()) {
27541case Arg::Addr:
27542case Arg::Stack:
27543case Arg::CallArg:
27544#if CPU(X86) || CPU(X86_64)
27545jit.add16(args[0].gpr(), args[1].asAddress());
27546OPGEN_RETURN(result);
27547#endif
27548break;
27549break;
27550case Arg::Index:
27551#if CPU(X86) || CPU(X86_64)
27552jit.add16(args[0].gpr(), args[1].asBaseIndex());
27553OPGEN_RETURN(result);
27554#endif
27555break;
27556break;
27557default:
27558break;
27559}
27560break;
27561default:
27562break;
27563}
27564break;
27565case Opcode::Add64:
27566switch (this->args.size()) {
27567case 2:
27568switch (this->args[0].kind()) {
27569case Arg::Tmp:
27570switch (this->args[1].kind()) {
27571case Arg::Tmp:
27572#if CPU(X86_64) || CPU(ARM64)
27573jit.add64(args[0].gpr(), args[1].gpr());
27574OPGEN_RETURN(result);
27575#endif
27576break;
27577break;
27578case Arg::Addr:
27579case Arg::Stack:
27580case Arg::CallArg:
27581#if CPU(X86_64)
27582jit.add64(args[0].gpr(), args[1].asAddress());
27583OPGEN_RETURN(result);
27584#endif
27585break;
27586break;
27587case Arg::Index:
27588#if CPU(X86_64)
27589jit.add64(args[0].gpr(), args[1].asBaseIndex());
27590OPGEN_RETURN(result);
27591#endif
27592break;
27593break;
27594default:
27595break;
27596}
27597break;
27598case Arg::Imm:
27599switch (this->args[1].kind()) {
27600case Arg::Addr:
27601case Arg::Stack:
27602case Arg::CallArg:
27603#if CPU(X86_64)
27604jit.add64(args[0].asTrustedImm32(), args[1].asAddress());
27605OPGEN_RETURN(result);
27606#endif
27607break;
27608break;
27609case Arg::Index:
27610#if CPU(X86_64)
27611jit.add64(args[0].asTrustedImm32(), args[1].asBaseIndex());
27612OPGEN_RETURN(result);
27613#endif
27614break;
27615break;
27616case Arg::Tmp:
27617#if CPU(X86_64) || CPU(ARM64)
27618jit.add64(args[0].asTrustedImm32(), args[1].gpr());
27619OPGEN_RETURN(result);
27620#endif
27621break;
27622break;
27623default:
27624break;
27625}
27626break;
27627case Arg::Addr:
27628case Arg::Stack:
27629case Arg::CallArg:
27630#if CPU(X86_64)
27631jit.add64(args[0].asAddress(), args[1].gpr());
27632OPGEN_RETURN(result);
27633#endif
27634break;
27635break;
27636case Arg::Index:
27637#if CPU(X86_64)
27638jit.add64(args[0].asBaseIndex(), args[1].gpr());
27639OPGEN_RETURN(result);
27640#endif
27641break;
27642break;
27643default:
27644break;
27645}
27646break;
27647case 3:
27648switch (this->args[0].kind()) {
27649case Arg::Imm:
27650#if CPU(X86_64) || CPU(ARM64)
27651jit.add64(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
27652OPGEN_RETURN(result);
27653#endif
27654break;
27655break;
27656case Arg::Tmp:
27657#if CPU(X86_64) || CPU(ARM64)
27658jit.add64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27659OPGEN_RETURN(result);
27660#endif
27661break;
27662break;
27663default:
27664break;
27665}
27666break;
27667default:
27668break;
27669}
27670break;
27671case Opcode::AddDouble:
27672switch (this->args.size()) {
27673case 3:
27674switch (this->args[0].kind()) {
27675case Arg::Tmp:
27676switch (this->args[1].kind()) {
27677case Arg::Tmp:
27678jit.addDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
27679OPGEN_RETURN(result);
27680break;
27681break;
27682case Arg::Addr:
27683case Arg::Stack:
27684case Arg::CallArg:
27685#if CPU(X86) || CPU(X86_64)
27686jit.addDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27687OPGEN_RETURN(result);
27688#endif
27689break;
27690break;
27691default:
27692break;
27693}
27694break;
27695case Arg::Addr:
27696case Arg::Stack:
27697case Arg::CallArg:
27698#if CPU(X86) || CPU(X86_64)
27699jit.addDouble(args[0].asAddress(), args[1].fpr(), args[2].fpr());
27700OPGEN_RETURN(result);
27701#endif
27702break;
27703break;
27704case Arg::Index:
27705#if CPU(X86) || CPU(X86_64)
27706jit.addDouble(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
27707OPGEN_RETURN(result);
27708#endif
27709break;
27710break;
27711default:
27712break;
27713}
27714break;
27715case 2:
27716switch (this->args[0].kind()) {
27717case Arg::Tmp:
27718#if CPU(X86) || CPU(X86_64)
27719jit.addDouble(args[0].fpr(), args[1].fpr());
27720OPGEN_RETURN(result);
27721#endif
27722break;
27723break;
27724case Arg::Addr:
27725case Arg::Stack:
27726case Arg::CallArg:
27727#if CPU(X86) || CPU(X86_64)
27728jit.addDouble(args[0].asAddress(), args[1].fpr());
27729OPGEN_RETURN(result);
27730#endif
27731break;
27732break;
27733default:
27734break;
27735}
27736break;
27737default:
27738break;
27739}
27740break;
27741case Opcode::AddFloat:
27742switch (this->args.size()) {
27743case 3:
27744switch (this->args[0].kind()) {
27745case Arg::Tmp:
27746switch (this->args[1].kind()) {
27747case Arg::Tmp:
27748jit.addFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
27749OPGEN_RETURN(result);
27750break;
27751break;
27752case Arg::Addr:
27753case Arg::Stack:
27754case Arg::CallArg:
27755#if CPU(X86) || CPU(X86_64)
27756jit.addFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27757OPGEN_RETURN(result);
27758#endif
27759break;
27760break;
27761default:
27762break;
27763}
27764break;
27765case Arg::Addr:
27766case Arg::Stack:
27767case Arg::CallArg:
27768#if CPU(X86) || CPU(X86_64)
27769jit.addFloat(args[0].asAddress(), args[1].fpr(), args[2].fpr());
27770OPGEN_RETURN(result);
27771#endif
27772break;
27773break;
27774case Arg::Index:
27775#if CPU(X86) || CPU(X86_64)
27776jit.addFloat(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
27777OPGEN_RETURN(result);
27778#endif
27779break;
27780break;
27781default:
27782break;
27783}
27784break;
27785case 2:
27786switch (this->args[0].kind()) {
27787case Arg::Tmp:
27788#if CPU(X86) || CPU(X86_64)
27789jit.addFloat(args[0].fpr(), args[1].fpr());
27790OPGEN_RETURN(result);
27791#endif
27792break;
27793break;
27794case Arg::Addr:
27795case Arg::Stack:
27796case Arg::CallArg:
27797#if CPU(X86) || CPU(X86_64)
27798jit.addFloat(args[0].asAddress(), args[1].fpr());
27799OPGEN_RETURN(result);
27800#endif
27801break;
27802break;
27803default:
27804break;
27805}
27806break;
27807default:
27808break;
27809}
27810break;
27811case Opcode::Sub32:
27812switch (this->args.size()) {
27813case 2:
27814switch (this->args[0].kind()) {
27815case Arg::Tmp:
27816switch (this->args[1].kind()) {
27817case Arg::Tmp:
27818jit.sub32(args[0].gpr(), args[1].gpr());
27819OPGEN_RETURN(result);
27820break;
27821break;
27822case Arg::Addr:
27823case Arg::Stack:
27824case Arg::CallArg:
27825#if CPU(X86) || CPU(X86_64)
27826jit.sub32(args[0].gpr(), args[1].asAddress());
27827OPGEN_RETURN(result);
27828#endif
27829break;
27830break;
27831case Arg::Index:
27832#if CPU(X86) || CPU(X86_64)
27833jit.sub32(args[0].gpr(), args[1].asBaseIndex());
27834OPGEN_RETURN(result);
27835#endif
27836break;
27837break;
27838default:
27839break;
27840}
27841break;
27842case Arg::Imm:
27843switch (this->args[1].kind()) {
27844case Arg::Addr:
27845case Arg::Stack:
27846case Arg::CallArg:
27847#if CPU(X86) || CPU(X86_64)
27848jit.sub32(args[0].asTrustedImm32(), args[1].asAddress());
27849OPGEN_RETURN(result);
27850#endif
27851break;
27852break;
27853case Arg::Index:
27854#if CPU(X86) || CPU(X86_64)
27855jit.sub32(args[0].asTrustedImm32(), args[1].asBaseIndex());
27856OPGEN_RETURN(result);
27857#endif
27858break;
27859break;
27860case Arg::Tmp:
27861jit.sub32(args[0].asTrustedImm32(), args[1].gpr());
27862OPGEN_RETURN(result);
27863break;
27864break;
27865default:
27866break;
27867}
27868break;
27869case Arg::Addr:
27870case Arg::Stack:
27871case Arg::CallArg:
27872#if CPU(X86) || CPU(X86_64)
27873jit.sub32(args[0].asAddress(), args[1].gpr());
27874OPGEN_RETURN(result);
27875#endif
27876break;
27877break;
27878case Arg::Index:
27879#if CPU(X86) || CPU(X86_64)
27880jit.sub32(args[0].asBaseIndex(), args[1].gpr());
27881OPGEN_RETURN(result);
27882#endif
27883break;
27884break;
27885default:
27886break;
27887}
27888break;
27889case 3:
27890#if CPU(ARM64)
27891jit.sub32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27892OPGEN_RETURN(result);
27893#endif
27894break;
27895break;
27896default:
27897break;
27898}
27899break;
27900case Opcode::Sub64:
27901switch (this->args.size()) {
27902case 2:
27903switch (this->args[0].kind()) {
27904case Arg::Tmp:
27905switch (this->args[1].kind()) {
27906case Arg::Tmp:
27907#if CPU(X86_64) || CPU(ARM64)
27908jit.sub64(args[0].gpr(), args[1].gpr());
27909OPGEN_RETURN(result);
27910#endif
27911break;
27912break;
27913case Arg::Addr:
27914case Arg::Stack:
27915case Arg::CallArg:
27916#if CPU(X86_64)
27917jit.sub64(args[0].gpr(), args[1].asAddress());
27918OPGEN_RETURN(result);
27919#endif
27920break;
27921break;
27922case Arg::Index:
27923#if CPU(X86_64)
27924jit.sub64(args[0].gpr(), args[1].asBaseIndex());
27925OPGEN_RETURN(result);
27926#endif
27927break;
27928break;
27929default:
27930break;
27931}
27932break;
27933case Arg::Imm:
27934switch (this->args[1].kind()) {
27935case Arg::Addr:
27936case Arg::Stack:
27937case Arg::CallArg:
27938#if CPU(X86_64)
27939jit.sub64(args[0].asTrustedImm32(), args[1].asAddress());
27940OPGEN_RETURN(result);
27941#endif
27942break;
27943break;
27944case Arg::Index:
27945#if CPU(X86_64)
27946jit.sub64(args[0].asTrustedImm32(), args[1].asBaseIndex());
27947OPGEN_RETURN(result);
27948#endif
27949break;
27950break;
27951case Arg::Tmp:
27952#if CPU(X86_64) || CPU(ARM64)
27953jit.sub64(args[0].asTrustedImm32(), args[1].gpr());
27954OPGEN_RETURN(result);
27955#endif
27956break;
27957break;
27958default:
27959break;
27960}
27961break;
27962case Arg::Addr:
27963case Arg::Stack:
27964case Arg::CallArg:
27965#if CPU(X86_64)
27966jit.sub64(args[0].asAddress(), args[1].gpr());
27967OPGEN_RETURN(result);
27968#endif
27969break;
27970break;
27971case Arg::Index:
27972#if CPU(X86_64)
27973jit.sub64(args[0].asBaseIndex(), args[1].gpr());
27974OPGEN_RETURN(result);
27975#endif
27976break;
27977break;
27978default:
27979break;
27980}
27981break;
27982case 3:
27983#if CPU(ARM64)
27984jit.sub64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27985OPGEN_RETURN(result);
27986#endif
27987break;
27988break;
27989default:
27990break;
27991}
27992break;
27993case Opcode::SubDouble:
27994switch (this->args.size()) {
27995case 3:
27996switch (this->args[1].kind()) {
27997case Arg::Tmp:
27998#if CPU(ARM64)
27999jit.subDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28000OPGEN_RETURN(result);
28001#endif
28002break;
28003break;
28004case Arg::Addr:
28005case Arg::Stack:
28006case Arg::CallArg:
28007#if CPU(X86) || CPU(X86_64)
28008jit.subDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28009OPGEN_RETURN(result);
28010#endif
28011break;
28012break;
28013case Arg::Index:
28014#if CPU(X86) || CPU(X86_64)
28015jit.subDouble(args[0].fpr(), args[1].asBaseIndex(), args[2].fpr());
28016OPGEN_RETURN(result);
28017#endif
28018break;
28019break;
28020default:
28021break;
28022}
28023break;
28024case 2:
28025switch (this->args[0].kind()) {
28026case Arg::Tmp:
28027#if CPU(X86) || CPU(X86_64)
28028jit.subDouble(args[0].fpr(), args[1].fpr());
28029OPGEN_RETURN(result);
28030#endif
28031break;
28032break;
28033case Arg::Addr:
28034case Arg::Stack:
28035case Arg::CallArg:
28036#if CPU(X86) || CPU(X86_64)
28037jit.subDouble(args[0].asAddress(), args[1].fpr());
28038OPGEN_RETURN(result);
28039#endif
28040break;
28041break;
28042default:
28043break;
28044}
28045break;
28046default:
28047break;
28048}
28049break;
28050case Opcode::SubFloat:
28051switch (this->args.size()) {
28052case 3:
28053switch (this->args[1].kind()) {
28054case Arg::Tmp:
28055#if CPU(ARM64)
28056jit.subFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28057OPGEN_RETURN(result);
28058#endif
28059break;
28060break;
28061case Arg::Addr:
28062case Arg::Stack:
28063case Arg::CallArg:
28064#if CPU(X86) || CPU(X86_64)
28065jit.subFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28066OPGEN_RETURN(result);
28067#endif
28068break;
28069break;
28070case Arg::Index:
28071#if CPU(X86) || CPU(X86_64)
28072jit.subFloat(args[0].fpr(), args[1].asBaseIndex(), args[2].fpr());
28073OPGEN_RETURN(result);
28074#endif
28075break;
28076break;
28077default:
28078break;
28079}
28080break;
28081case 2:
28082switch (this->args[0].kind()) {
28083case Arg::Tmp:
28084#if CPU(X86) || CPU(X86_64)
28085jit.subFloat(args[0].fpr(), args[1].fpr());
28086OPGEN_RETURN(result);
28087#endif
28088break;
28089break;
28090case Arg::Addr:
28091case Arg::Stack:
28092case Arg::CallArg:
28093#if CPU(X86) || CPU(X86_64)
28094jit.subFloat(args[0].asAddress(), args[1].fpr());
28095OPGEN_RETURN(result);
28096#endif
28097break;
28098break;
28099default:
28100break;
28101}
28102break;
28103default:
28104break;
28105}
28106break;
28107case Opcode::Neg32:
28108switch (this->args[0].kind()) {
28109case Arg::Tmp:
28110jit.neg32(args[0].gpr());
28111OPGEN_RETURN(result);
28112break;
28113break;
28114case Arg::Addr:
28115case Arg::Stack:
28116case Arg::CallArg:
28117#if CPU(X86) || CPU(X86_64)
28118jit.neg32(args[0].asAddress());
28119OPGEN_RETURN(result);
28120#endif
28121break;
28122break;
28123case Arg::Index:
28124#if CPU(X86) || CPU(X86_64)
28125jit.neg32(args[0].asBaseIndex());
28126OPGEN_RETURN(result);
28127#endif
28128break;
28129break;
28130default:
28131break;
28132}
28133break;
28134case Opcode::Neg64:
28135switch (this->args[0].kind()) {
28136case Arg::Tmp:
28137#if CPU(X86_64) || CPU(ARM64)
28138jit.neg64(args[0].gpr());
28139OPGEN_RETURN(result);
28140#endif
28141break;
28142break;
28143case Arg::Addr:
28144case Arg::Stack:
28145case Arg::CallArg:
28146#if CPU(X86_64)
28147jit.neg64(args[0].asAddress());
28148OPGEN_RETURN(result);
28149#endif
28150break;
28151break;
28152case Arg::Index:
28153#if CPU(X86_64)
28154jit.neg64(args[0].asBaseIndex());
28155OPGEN_RETURN(result);
28156#endif
28157break;
28158break;
28159default:
28160break;
28161}
28162break;
28163case Opcode::NegateDouble:
28164#if CPU(ARM64)
28165jit.negateDouble(args[0].fpr(), args[1].fpr());
28166OPGEN_RETURN(result);
28167#endif
28168break;
28169break;
28170case Opcode::NegateFloat:
28171#if CPU(ARM64)
28172jit.negateFloat(args[0].fpr(), args[1].fpr());
28173OPGEN_RETURN(result);
28174#endif
28175break;
28176break;
28177case Opcode::Mul32:
28178switch (this->args.size()) {
28179case 2:
28180switch (this->args[0].kind()) {
28181case Arg::Tmp:
28182jit.mul32(args[0].gpr(), args[1].gpr());
28183OPGEN_RETURN(result);
28184break;
28185break;
28186case Arg::Addr:
28187case Arg::Stack:
28188case Arg::CallArg:
28189#if CPU(X86) || CPU(X86_64)
28190jit.mul32(args[0].asAddress(), args[1].gpr());
28191OPGEN_RETURN(result);
28192#endif
28193break;
28194break;
28195default:
28196break;
28197}
28198break;
28199case 3:
28200switch (this->args[0].kind()) {
28201case Arg::Tmp:
28202switch (this->args[1].kind()) {
28203case Arg::Tmp:
28204jit.mul32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28205OPGEN_RETURN(result);
28206break;
28207break;
28208case Arg::Addr:
28209case Arg::Stack:
28210case Arg::CallArg:
28211#if CPU(X86) || CPU(X86_64)
28212jit.mul32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
28213OPGEN_RETURN(result);
28214#endif
28215break;
28216break;
28217default:
28218break;
28219}
28220break;
28221case Arg::Addr:
28222case Arg::Stack:
28223case Arg::CallArg:
28224#if CPU(X86) || CPU(X86_64)
28225jit.mul32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
28226OPGEN_RETURN(result);
28227#endif
28228break;
28229break;
28230case Arg::Imm:
28231#if CPU(X86) || CPU(X86_64)
28232jit.mul32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
28233OPGEN_RETURN(result);
28234#endif
28235break;
28236break;
28237default:
28238break;
28239}
28240break;
28241default:
28242break;
28243}
28244break;
28245case Opcode::Mul64:
28246switch (this->args.size()) {
28247case 2:
28248#if CPU(X86_64) || CPU(ARM64)
28249jit.mul64(args[0].gpr(), args[1].gpr());
28250OPGEN_RETURN(result);
28251#endif
28252break;
28253break;
28254case 3:
28255jit.mul64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28256OPGEN_RETURN(result);
28257break;
28258break;
28259default:
28260break;
28261}
28262break;
28263case Opcode::MultiplyAdd32:
28264#if CPU(ARM64)
28265jit.multiplyAdd32(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
28266OPGEN_RETURN(result);
28267#endif
28268break;
28269break;
28270case Opcode::MultiplyAdd64:
28271#if CPU(ARM64)
28272jit.multiplyAdd64(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
28273OPGEN_RETURN(result);
28274#endif
28275break;
28276break;
28277case Opcode::MultiplySub32:
28278#if CPU(ARM64)
28279jit.multiplySub32(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
28280OPGEN_RETURN(result);
28281#endif
28282break;
28283break;
28284case Opcode::MultiplySub64:
28285#if CPU(ARM64)
28286jit.multiplySub64(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
28287OPGEN_RETURN(result);
28288#endif
28289break;
28290break;
28291case Opcode::MultiplyNeg32:
28292#if CPU(ARM64)
28293jit.multiplyNeg32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28294OPGEN_RETURN(result);
28295#endif
28296break;
28297break;
28298case Opcode::MultiplyNeg64:
28299#if CPU(ARM64)
28300jit.multiplyNeg64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28301OPGEN_RETURN(result);
28302#endif
28303break;
28304break;
28305case Opcode::MultiplySignExtend32:
28306#if CPU(ARM64)
28307jit.multiplySignExtend32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28308OPGEN_RETURN(result);
28309#endif
28310break;
28311break;
28312case Opcode::Div32:
28313#if CPU(ARM64)
28314jit.div32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28315OPGEN_RETURN(result);
28316#endif
28317break;
28318break;
28319case Opcode::UDiv32:
28320#if CPU(ARM64)
28321jit.uDiv32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28322OPGEN_RETURN(result);
28323#endif
28324break;
28325break;
28326case Opcode::Div64:
28327#if CPU(ARM64)
28328jit.div64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28329OPGEN_RETURN(result);
28330#endif
28331break;
28332break;
28333case Opcode::UDiv64:
28334#if CPU(ARM64)
28335jit.uDiv64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28336OPGEN_RETURN(result);
28337#endif
28338break;
28339break;
28340case Opcode::MulDouble:
28341switch (this->args.size()) {
28342case 3:
28343switch (this->args[0].kind()) {
28344case Arg::Tmp:
28345switch (this->args[1].kind()) {
28346case Arg::Tmp:
28347jit.mulDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28348OPGEN_RETURN(result);
28349break;
28350break;
28351case Arg::Addr:
28352case Arg::Stack:
28353case Arg::CallArg:
28354#if CPU(X86) || CPU(X86_64)
28355jit.mulDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28356OPGEN_RETURN(result);
28357#endif
28358break;
28359break;
28360default:
28361break;
28362}
28363break;
28364case Arg::Addr:
28365case Arg::Stack:
28366case Arg::CallArg:
28367#if CPU(X86) || CPU(X86_64)
28368jit.mulDouble(args[0].asAddress(), args[1].fpr(), args[2].fpr());
28369OPGEN_RETURN(result);
28370#endif
28371break;
28372break;
28373case Arg::Index:
28374#if CPU(X86) || CPU(X86_64)
28375jit.mulDouble(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
28376OPGEN_RETURN(result);
28377#endif
28378break;
28379break;
28380default:
28381break;
28382}
28383break;
28384case 2:
28385switch (this->args[0].kind()) {
28386case Arg::Tmp:
28387#if CPU(X86) || CPU(X86_64)
28388jit.mulDouble(args[0].fpr(), args[1].fpr());
28389OPGEN_RETURN(result);
28390#endif
28391break;
28392break;
28393case Arg::Addr:
28394case Arg::Stack:
28395case Arg::CallArg:
28396#if CPU(X86) || CPU(X86_64)
28397jit.mulDouble(args[0].asAddress(), args[1].fpr());
28398OPGEN_RETURN(result);
28399#endif
28400break;
28401break;
28402default:
28403break;
28404}
28405break;
28406default:
28407break;
28408}
28409break;
28410case Opcode::MulFloat:
28411switch (this->args.size()) {
28412case 3:
28413switch (this->args[0].kind()) {
28414case Arg::Tmp:
28415switch (this->args[1].kind()) {
28416case Arg::Tmp:
28417jit.mulFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28418OPGEN_RETURN(result);
28419break;
28420break;
28421case Arg::Addr:
28422case Arg::Stack:
28423case Arg::CallArg:
28424#if CPU(X86) || CPU(X86_64)
28425jit.mulFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28426OPGEN_RETURN(result);
28427#endif
28428break;
28429break;
28430default:
28431break;
28432}
28433break;
28434case Arg::Addr:
28435case Arg::Stack:
28436case Arg::CallArg:
28437#if CPU(X86) || CPU(X86_64)
28438jit.mulFloat(args[0].asAddress(), args[1].fpr(), args[2].fpr());
28439OPGEN_RETURN(result);
28440#endif
28441break;
28442break;
28443case Arg::Index:
28444#if CPU(X86) || CPU(X86_64)
28445jit.mulFloat(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
28446OPGEN_RETURN(result);
28447#endif
28448break;
28449break;
28450default:
28451break;
28452}
28453break;
28454case 2:
28455switch (this->args[0].kind()) {
28456case Arg::Tmp:
28457#if CPU(X86) || CPU(X86_64)
28458jit.mulFloat(args[0].fpr(), args[1].fpr());
28459OPGEN_RETURN(result);
28460#endif
28461break;
28462break;
28463case Arg::Addr:
28464case Arg::Stack:
28465case Arg::CallArg:
28466#if CPU(X86) || CPU(X86_64)
28467jit.mulFloat(args[0].asAddress(), args[1].fpr());
28468OPGEN_RETURN(result);
28469#endif
28470break;
28471break;
28472default:
28473break;
28474}
28475break;
28476default:
28477break;
28478}
28479break;
28480case Opcode::DivDouble:
28481switch (this->args.size()) {
28482case 3:
28483#if CPU(ARM64)
28484jit.divDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28485OPGEN_RETURN(result);
28486#endif
28487break;
28488break;
28489case 2:
28490switch (this->args[0].kind()) {
28491case Arg::Tmp:
28492#if CPU(X86) || CPU(X86_64)
28493jit.divDouble(args[0].fpr(), args[1].fpr());
28494OPGEN_RETURN(result);
28495#endif
28496break;
28497break;
28498case Arg::Addr:
28499case Arg::Stack:
28500case Arg::CallArg:
28501#if CPU(X86) || CPU(X86_64)
28502jit.divDouble(args[0].asAddress(), args[1].fpr());
28503OPGEN_RETURN(result);
28504#endif
28505break;
28506break;
28507default:
28508break;
28509}
28510break;
28511default:
28512break;
28513}
28514break;
28515case Opcode::DivFloat:
28516switch (this->args.size()) {
28517case 3:
28518#if CPU(ARM64)
28519jit.divFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28520OPGEN_RETURN(result);
28521#endif
28522break;
28523break;
28524case 2:
28525switch (this->args[0].kind()) {
28526case Arg::Tmp:
28527#if CPU(X86) || CPU(X86_64)
28528jit.divFloat(args[0].fpr(), args[1].fpr());
28529OPGEN_RETURN(result);
28530#endif
28531break;
28532break;
28533case Arg::Addr:
28534case Arg::Stack:
28535case Arg::CallArg:
28536#if CPU(X86) || CPU(X86_64)
28537jit.divFloat(args[0].asAddress(), args[1].fpr());
28538OPGEN_RETURN(result);
28539#endif
28540break;
28541break;
28542default:
28543break;
28544}
28545break;
28546default:
28547break;
28548}
28549break;
28550case Opcode::X86ConvertToDoubleWord32:
28551#if CPU(X86) || CPU(X86_64)
28552jit.x86ConvertToDoubleWord32(args[0].gpr(), args[1].gpr());
28553OPGEN_RETURN(result);
28554#endif
28555break;
28556break;
28557case Opcode::X86ConvertToQuadWord64:
28558#if CPU(X86_64)
28559jit.x86ConvertToQuadWord64(args[0].gpr(), args[1].gpr());
28560OPGEN_RETURN(result);
28561#endif
28562break;
28563break;
28564case Opcode::X86Div32:
28565#if CPU(X86) || CPU(X86_64)
28566jit.x86Div32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28567OPGEN_RETURN(result);
28568#endif
28569break;
28570break;
28571case Opcode::X86UDiv32:
28572#if CPU(X86) || CPU(X86_64)
28573jit.x86UDiv32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28574OPGEN_RETURN(result);
28575#endif
28576break;
28577break;
28578case Opcode::X86Div64:
28579#if CPU(X86_64)
28580jit.x86Div64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28581OPGEN_RETURN(result);
28582#endif
28583break;
28584break;
28585case Opcode::X86UDiv64:
28586#if CPU(X86_64)
28587jit.x86UDiv64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28588OPGEN_RETURN(result);
28589#endif
28590break;
28591break;
28592case Opcode::Lea32:
28593switch (this->args[0].kind()) {
28594case Arg::Addr:
28595case Arg::Stack:
28596case Arg::CallArg:
28597jit.lea32(args[0].asAddress(), args[1].gpr());
28598OPGEN_RETURN(result);
28599break;
28600break;
28601case Arg::Index:
28602#if CPU(X86) || CPU(X86_64)
28603jit.x86Lea32(args[0].asBaseIndex(), args[1].gpr());
28604OPGEN_RETURN(result);
28605#endif
28606break;
28607break;
28608default:
28609break;
28610}
28611break;
28612case Opcode::Lea64:
28613switch (this->args[0].kind()) {
28614case Arg::Addr:
28615case Arg::Stack:
28616case Arg::CallArg:
28617jit.lea64(args[0].asAddress(), args[1].gpr());
28618OPGEN_RETURN(result);
28619break;
28620break;
28621case Arg::Index:
28622#if CPU(X86) || CPU(X86_64)
28623jit.x86Lea64(args[0].asBaseIndex(), args[1].gpr());
28624OPGEN_RETURN(result);
28625#endif
28626break;
28627break;
28628default:
28629break;
28630}
28631break;
28632case Opcode::And32:
28633switch (this->args.size()) {
28634case 3:
28635switch (this->args[0].kind()) {
28636case Arg::Tmp:
28637switch (this->args[1].kind()) {
28638case Arg::Tmp:
28639jit.and32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28640OPGEN_RETURN(result);
28641break;
28642break;
28643case Arg::Addr:
28644case Arg::Stack:
28645case Arg::CallArg:
28646#if CPU(X86) || CPU(X86_64)
28647jit.and32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
28648OPGEN_RETURN(result);
28649#endif
28650break;
28651break;
28652default:
28653break;
28654}
28655break;
28656case Arg::BitImm:
28657#if CPU(ARM64)
28658jit.and32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
28659OPGEN_RETURN(result);
28660#endif
28661break;
28662break;
28663case Arg::Addr:
28664case Arg::Stack:
28665case Arg::CallArg:
28666#if CPU(X86) || CPU(X86_64)
28667jit.and32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
28668OPGEN_RETURN(result);
28669#endif
28670break;
28671break;
28672default:
28673break;
28674}
28675break;
28676case 2:
28677switch (this->args[0].kind()) {
28678case Arg::Tmp:
28679switch (this->args[1].kind()) {
28680case Arg::Tmp:
28681jit.and32(args[0].gpr(), args[1].gpr());
28682OPGEN_RETURN(result);
28683break;
28684break;
28685case Arg::Addr:
28686case Arg::Stack:
28687case Arg::CallArg:
28688#if CPU(X86) || CPU(X86_64)
28689jit.and32(args[0].gpr(), args[1].asAddress());
28690OPGEN_RETURN(result);
28691#endif
28692break;
28693break;
28694case Arg::Index:
28695#if CPU(X86) || CPU(X86_64)
28696jit.and32(args[0].gpr(), args[1].asBaseIndex());
28697OPGEN_RETURN(result);
28698#endif
28699break;
28700break;
28701default:
28702break;
28703}
28704break;
28705case Arg::Imm:
28706switch (this->args[1].kind()) {
28707case Arg::Tmp:
28708#if CPU(X86) || CPU(X86_64)
28709jit.and32(args[0].asTrustedImm32(), args[1].gpr());
28710OPGEN_RETURN(result);
28711#endif
28712break;
28713break;
28714case Arg::Addr:
28715case Arg::Stack:
28716case Arg::CallArg:
28717#if CPU(X86) || CPU(X86_64)
28718jit.and32(args[0].asTrustedImm32(), args[1].asAddress());
28719OPGEN_RETURN(result);
28720#endif
28721break;
28722break;
28723case Arg::Index:
28724#if CPU(X86) || CPU(X86_64)
28725jit.and32(args[0].asTrustedImm32(), args[1].asBaseIndex());
28726OPGEN_RETURN(result);
28727#endif
28728break;
28729break;
28730default:
28731break;
28732}
28733break;
28734case Arg::Addr:
28735case Arg::Stack:
28736case Arg::CallArg:
28737#if CPU(X86) || CPU(X86_64)
28738jit.and32(args[0].asAddress(), args[1].gpr());
28739OPGEN_RETURN(result);
28740#endif
28741break;
28742break;
28743case Arg::Index:
28744#if CPU(X86) || CPU(X86_64)
28745jit.and32(args[0].asBaseIndex(), args[1].gpr());
28746OPGEN_RETURN(result);
28747#endif
28748break;
28749break;
28750default:
28751break;
28752}
28753break;
28754default:
28755break;
28756}
28757break;
28758case Opcode::And64:
28759switch (this->args.size()) {
28760case 3:
28761switch (this->args[0].kind()) {
28762case Arg::Tmp:
28763#if CPU(X86_64) || CPU(ARM64)
28764jit.and64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28765OPGEN_RETURN(result);
28766#endif
28767break;
28768break;
28769#if USE(JSVALUE64)
28770case Arg::BitImm64:
28771#if CPU(ARM64)
28772jit.and64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
28773OPGEN_RETURN(result);
28774#endif
28775break;
28776break;
28777#endif // USE(JSVALUE64)
28778default:
28779break;
28780}
28781break;
28782case 2:
28783switch (this->args[0].kind()) {
28784case Arg::Tmp:
28785switch (this->args[1].kind()) {
28786case Arg::Tmp:
28787#if CPU(X86_64)
28788jit.and64(args[0].gpr(), args[1].gpr());
28789OPGEN_RETURN(result);
28790#endif
28791break;
28792break;
28793case Arg::Addr:
28794case Arg::Stack:
28795case Arg::CallArg:
28796#if CPU(X86_64)
28797jit.and64(args[0].gpr(), args[1].asAddress());
28798OPGEN_RETURN(result);
28799#endif
28800break;
28801break;
28802case Arg::Index:
28803#if CPU(X86_64)
28804jit.and64(args[0].gpr(), args[1].asBaseIndex());
28805OPGEN_RETURN(result);
28806#endif
28807break;
28808break;
28809default:
28810break;
28811}
28812break;
28813case Arg::Imm:
28814switch (this->args[1].kind()) {
28815case Arg::Tmp:
28816#if CPU(X86_64)
28817jit.and64(args[0].asTrustedImm32(), args[1].gpr());
28818OPGEN_RETURN(result);
28819#endif
28820break;
28821break;
28822case Arg::Addr:
28823case Arg::Stack:
28824case Arg::CallArg:
28825#if CPU(X86_64)
28826jit.and64(args[0].asTrustedImm32(), args[1].asAddress());
28827OPGEN_RETURN(result);
28828#endif
28829break;
28830break;
28831case Arg::Index:
28832#if CPU(X86_64)
28833jit.and64(args[0].asTrustedImm32(), args[1].asBaseIndex());
28834OPGEN_RETURN(result);
28835#endif
28836break;
28837break;
28838default:
28839break;
28840}
28841break;
28842case Arg::Addr:
28843case Arg::Stack:
28844case Arg::CallArg:
28845#if CPU(X86_64)
28846jit.and64(args[0].asAddress(), args[1].gpr());
28847OPGEN_RETURN(result);
28848#endif
28849break;
28850break;
28851case Arg::Index:
28852#if CPU(X86_64)
28853jit.and64(args[0].asBaseIndex(), args[1].gpr());
28854OPGEN_RETURN(result);
28855#endif
28856break;
28857break;
28858default:
28859break;
28860}
28861break;
28862default:
28863break;
28864}
28865break;
28866case Opcode::AndDouble:
28867switch (this->args.size()) {
28868case 3:
28869jit.andDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28870OPGEN_RETURN(result);
28871break;
28872break;
28873case 2:
28874#if CPU(X86) || CPU(X86_64)
28875jit.andDouble(args[0].fpr(), args[1].fpr());
28876OPGEN_RETURN(result);
28877#endif
28878break;
28879break;
28880default:
28881break;
28882}
28883break;
28884case Opcode::AndFloat:
28885switch (this->args.size()) {
28886case 3:
28887jit.andFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28888OPGEN_RETURN(result);
28889break;
28890break;
28891case 2:
28892#if CPU(X86) || CPU(X86_64)
28893jit.andFloat(args[0].fpr(), args[1].fpr());
28894OPGEN_RETURN(result);
28895#endif
28896break;
28897break;
28898default:
28899break;
28900}
28901break;
28902case Opcode::OrDouble:
28903switch (this->args.size()) {
28904case 3:
28905jit.orDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28906OPGEN_RETURN(result);
28907break;
28908break;
28909case 2:
28910#if CPU(X86) || CPU(X86_64)
28911jit.orDouble(args[0].fpr(), args[1].fpr());
28912OPGEN_RETURN(result);
28913#endif
28914break;
28915break;
28916default:
28917break;
28918}
28919break;
28920case Opcode::OrFloat:
28921switch (this->args.size()) {
28922case 3:
28923jit.orFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28924OPGEN_RETURN(result);
28925break;
28926break;
28927case 2:
28928#if CPU(X86) || CPU(X86_64)
28929jit.orFloat(args[0].fpr(), args[1].fpr());
28930OPGEN_RETURN(result);
28931#endif
28932break;
28933break;
28934default:
28935break;
28936}
28937break;
28938case Opcode::XorDouble:
28939switch (this->args.size()) {
28940case 3:
28941#if CPU(X86) || CPU(X86_64)
28942jit.xorDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28943OPGEN_RETURN(result);
28944#endif
28945break;
28946break;
28947case 2:
28948#if CPU(X86) || CPU(X86_64)
28949jit.xorDouble(args[0].fpr(), args[1].fpr());
28950OPGEN_RETURN(result);
28951#endif
28952break;
28953break;
28954default:
28955break;
28956}
28957break;
28958case Opcode::XorFloat:
28959switch (this->args.size()) {
28960case 3:
28961#if CPU(X86) || CPU(X86_64)
28962jit.xorFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28963OPGEN_RETURN(result);
28964#endif
28965break;
28966break;
28967case 2:
28968#if CPU(X86) || CPU(X86_64)
28969jit.xorFloat(args[0].fpr(), args[1].fpr());
28970OPGEN_RETURN(result);
28971#endif
28972break;
28973break;
28974default:
28975break;
28976}
28977break;
28978case Opcode::Lshift32:
28979switch (this->args.size()) {
28980case 3:
28981switch (this->args[1].kind()) {
28982case Arg::Tmp:
28983#if CPU(ARM64)
28984jit.lshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28985OPGEN_RETURN(result);
28986#endif
28987break;
28988break;
28989case Arg::Imm:
28990#if CPU(ARM64)
28991jit.lshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28992OPGEN_RETURN(result);
28993#endif
28994break;
28995break;
28996default:
28997break;
28998}
28999break;
29000case 2:
29001switch (this->args[0].kind()) {
29002case Arg::Tmp:
29003#if CPU(X86) || CPU(X86_64)
29004jit.lshift32(args[0].gpr(), args[1].gpr());
29005OPGEN_RETURN(result);
29006#endif
29007break;
29008break;
29009case Arg::Imm:
29010#if CPU(X86) || CPU(X86_64)
29011jit.lshift32(args[0].asTrustedImm32(), args[1].gpr());
29012OPGEN_RETURN(result);
29013#endif
29014break;
29015break;
29016default:
29017break;
29018}
29019break;
29020default:
29021break;
29022}
29023break;
29024case Opcode::Lshift64:
29025switch (this->args.size()) {
29026case 3:
29027switch (this->args[1].kind()) {
29028case Arg::Tmp:
29029#if CPU(ARM64)
29030jit.lshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29031OPGEN_RETURN(result);
29032#endif
29033break;
29034break;
29035case Arg::Imm:
29036#if CPU(ARM64)
29037jit.lshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29038OPGEN_RETURN(result);
29039#endif
29040break;
29041break;
29042default:
29043break;
29044}
29045break;
29046case 2:
29047switch (this->args[0].kind()) {
29048case Arg::Tmp:
29049#if CPU(X86_64)
29050jit.lshift64(args[0].gpr(), args[1].gpr());
29051OPGEN_RETURN(result);
29052#endif
29053break;
29054break;
29055case Arg::Imm:
29056#if CPU(X86_64)
29057jit.lshift64(args[0].asTrustedImm32(), args[1].gpr());
29058OPGEN_RETURN(result);
29059#endif
29060break;
29061break;
29062default:
29063break;
29064}
29065break;
29066default:
29067break;
29068}
29069break;
29070case Opcode::Rshift32:
29071switch (this->args.size()) {
29072case 3:
29073switch (this->args[1].kind()) {
29074case Arg::Tmp:
29075#if CPU(ARM64)
29076jit.rshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29077OPGEN_RETURN(result);
29078#endif
29079break;
29080break;
29081case Arg::Imm:
29082#if CPU(ARM64)
29083jit.rshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29084OPGEN_RETURN(result);
29085#endif
29086break;
29087break;
29088default:
29089break;
29090}
29091break;
29092case 2:
29093switch (this->args[0].kind()) {
29094case Arg::Tmp:
29095#if CPU(X86) || CPU(X86_64)
29096jit.rshift32(args[0].gpr(), args[1].gpr());
29097OPGEN_RETURN(result);
29098#endif
29099break;
29100break;
29101case Arg::Imm:
29102#if CPU(X86) || CPU(X86_64)
29103jit.rshift32(args[0].asTrustedImm32(), args[1].gpr());
29104OPGEN_RETURN(result);
29105#endif
29106break;
29107break;
29108default:
29109break;
29110}
29111break;
29112default:
29113break;
29114}
29115break;
29116case Opcode::Rshift64:
29117switch (this->args.size()) {
29118case 3:
29119switch (this->args[1].kind()) {
29120case Arg::Tmp:
29121#if CPU(ARM64)
29122jit.rshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29123OPGEN_RETURN(result);
29124#endif
29125break;
29126break;
29127case Arg::Imm:
29128#if CPU(ARM64)
29129jit.rshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29130OPGEN_RETURN(result);
29131#endif
29132break;
29133break;
29134default:
29135break;
29136}
29137break;
29138case 2:
29139switch (this->args[0].kind()) {
29140case Arg::Tmp:
29141#if CPU(X86_64)
29142jit.rshift64(args[0].gpr(), args[1].gpr());
29143OPGEN_RETURN(result);
29144#endif
29145break;
29146break;
29147case Arg::Imm:
29148#if CPU(X86_64)
29149jit.rshift64(args[0].asTrustedImm32(), args[1].gpr());
29150OPGEN_RETURN(result);
29151#endif
29152break;
29153break;
29154default:
29155break;
29156}
29157break;
29158default:
29159break;
29160}
29161break;
29162case Opcode::Urshift32:
29163switch (this->args.size()) {
29164case 3:
29165switch (this->args[1].kind()) {
29166case Arg::Tmp:
29167#if CPU(ARM64)
29168jit.urshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29169OPGEN_RETURN(result);
29170#endif
29171break;
29172break;
29173case Arg::Imm:
29174#if CPU(ARM64)
29175jit.urshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29176OPGEN_RETURN(result);
29177#endif
29178break;
29179break;
29180default:
29181break;
29182}
29183break;
29184case 2:
29185switch (this->args[0].kind()) {
29186case Arg::Tmp:
29187#if CPU(X86) || CPU(X86_64)
29188jit.urshift32(args[0].gpr(), args[1].gpr());
29189OPGEN_RETURN(result);
29190#endif
29191break;
29192break;
29193case Arg::Imm:
29194#if CPU(X86) || CPU(X86_64)
29195jit.urshift32(args[0].asTrustedImm32(), args[1].gpr());
29196OPGEN_RETURN(result);
29197#endif
29198break;
29199break;
29200default:
29201break;
29202}
29203break;
29204default:
29205break;
29206}
29207break;
29208case Opcode::Urshift64:
29209switch (this->args.size()) {
29210case 3:
29211switch (this->args[1].kind()) {
29212case Arg::Tmp:
29213#if CPU(ARM64)
29214jit.urshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29215OPGEN_RETURN(result);
29216#endif
29217break;
29218break;
29219case Arg::Imm:
29220#if CPU(ARM64)
29221jit.urshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29222OPGEN_RETURN(result);
29223#endif
29224break;
29225break;
29226default:
29227break;
29228}
29229break;
29230case 2:
29231switch (this->args[0].kind()) {
29232case Arg::Tmp:
29233#if CPU(X86_64)
29234jit.urshift64(args[0].gpr(), args[1].gpr());
29235OPGEN_RETURN(result);
29236#endif
29237break;
29238break;
29239case Arg::Imm:
29240#if CPU(X86_64)
29241jit.urshift64(args[0].asTrustedImm32(), args[1].gpr());
29242OPGEN_RETURN(result);
29243#endif
29244break;
29245break;
29246default:
29247break;
29248}
29249break;
29250default:
29251break;
29252}
29253break;
29254case Opcode::RotateRight32:
29255switch (this->args.size()) {
29256case 2:
29257switch (this->args[0].kind()) {
29258case Arg::Tmp:
29259#if CPU(X86_64)
29260jit.rotateRight32(args[0].gpr(), args[1].gpr());
29261OPGEN_RETURN(result);
29262#endif
29263break;
29264break;
29265case Arg::Imm:
29266#if CPU(X86_64)
29267jit.rotateRight32(args[0].asTrustedImm32(), args[1].gpr());
29268OPGEN_RETURN(result);
29269#endif
29270break;
29271break;
29272default:
29273break;
29274}
29275break;
29276case 3:
29277switch (this->args[1].kind()) {
29278case Arg::Tmp:
29279#if CPU(ARM64)
29280jit.rotateRight32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29281OPGEN_RETURN(result);
29282#endif
29283break;
29284break;
29285case Arg::Imm:
29286#if CPU(ARM64)
29287jit.rotateRight32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29288OPGEN_RETURN(result);
29289#endif
29290break;
29291break;
29292default:
29293break;
29294}
29295break;
29296default:
29297break;
29298}
29299break;
29300case Opcode::RotateRight64:
29301switch (this->args.size()) {
29302case 2:
29303switch (this->args[0].kind()) {
29304case Arg::Tmp:
29305#if CPU(X86_64)
29306jit.rotateRight64(args[0].gpr(), args[1].gpr());
29307OPGEN_RETURN(result);
29308#endif
29309break;
29310break;
29311case Arg::Imm:
29312#if CPU(X86_64)
29313jit.rotateRight64(args[0].asTrustedImm32(), args[1].gpr());
29314OPGEN_RETURN(result);
29315#endif
29316break;
29317break;
29318default:
29319break;
29320}
29321break;
29322case 3:
29323switch (this->args[1].kind()) {
29324case Arg::Tmp:
29325#if CPU(ARM64)
29326jit.rotateRight64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29327OPGEN_RETURN(result);
29328#endif
29329break;
29330break;
29331case Arg::Imm:
29332#if CPU(ARM64)
29333jit.rotateRight64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29334OPGEN_RETURN(result);
29335#endif
29336break;
29337break;
29338default:
29339break;
29340}
29341break;
29342default:
29343break;
29344}
29345break;
29346case Opcode::RotateLeft32:
29347switch (this->args[0].kind()) {
29348case Arg::Tmp:
29349#if CPU(X86_64)
29350jit.rotateLeft32(args[0].gpr(), args[1].gpr());
29351OPGEN_RETURN(result);
29352#endif
29353break;
29354break;
29355case Arg::Imm:
29356#if CPU(X86_64)
29357jit.rotateLeft32(args[0].asTrustedImm32(), args[1].gpr());
29358OPGEN_RETURN(result);
29359#endif
29360break;
29361break;
29362default:
29363break;
29364}
29365break;
29366case Opcode::RotateLeft64:
29367switch (this->args[0].kind()) {
29368case Arg::Tmp:
29369#if CPU(X86_64)
29370jit.rotateLeft64(args[0].gpr(), args[1].gpr());
29371OPGEN_RETURN(result);
29372#endif
29373break;
29374break;
29375case Arg::Imm:
29376#if CPU(X86_64)
29377jit.rotateLeft64(args[0].asTrustedImm32(), args[1].gpr());
29378OPGEN_RETURN(result);
29379#endif
29380break;
29381break;
29382default:
29383break;
29384}
29385break;
29386case Opcode::Or32:
29387switch (this->args.size()) {
29388case 3:
29389switch (this->args[0].kind()) {
29390case Arg::Tmp:
29391switch (this->args[1].kind()) {
29392case Arg::Tmp:
29393jit.or32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29394OPGEN_RETURN(result);
29395break;
29396break;
29397case Arg::Addr:
29398case Arg::Stack:
29399case Arg::CallArg:
29400#if CPU(X86) || CPU(X86_64)
29401jit.or32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
29402OPGEN_RETURN(result);
29403#endif
29404break;
29405break;
29406default:
29407break;
29408}
29409break;
29410case Arg::BitImm:
29411#if CPU(ARM64)
29412jit.or32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
29413OPGEN_RETURN(result);
29414#endif
29415break;
29416break;
29417case Arg::Addr:
29418case Arg::Stack:
29419case Arg::CallArg:
29420#if CPU(X86) || CPU(X86_64)
29421jit.or32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
29422OPGEN_RETURN(result);
29423#endif
29424break;
29425break;
29426default:
29427break;
29428}
29429break;
29430case 2:
29431switch (this->args[0].kind()) {
29432case Arg::Tmp:
29433switch (this->args[1].kind()) {
29434case Arg::Tmp:
29435jit.or32(args[0].gpr(), args[1].gpr());
29436OPGEN_RETURN(result);
29437break;
29438break;
29439case Arg::Addr:
29440case Arg::Stack:
29441case Arg::CallArg:
29442#if CPU(X86) || CPU(X86_64)
29443jit.or32(args[0].gpr(), args[1].asAddress());
29444OPGEN_RETURN(result);
29445#endif
29446break;
29447break;
29448case Arg::Index:
29449#if CPU(X86) || CPU(X86_64)
29450jit.or32(args[0].gpr(), args[1].asBaseIndex());
29451OPGEN_RETURN(result);
29452#endif
29453break;
29454break;
29455default:
29456break;
29457}
29458break;
29459case Arg::Imm:
29460switch (this->args[1].kind()) {
29461case Arg::Tmp:
29462#if CPU(X86) || CPU(X86_64)
29463jit.or32(args[0].asTrustedImm32(), args[1].gpr());
29464OPGEN_RETURN(result);
29465#endif
29466break;
29467break;
29468case Arg::Addr:
29469case Arg::Stack:
29470case Arg::CallArg:
29471#if CPU(X86) || CPU(X86_64)
29472jit.or32(args[0].asTrustedImm32(), args[1].asAddress());
29473OPGEN_RETURN(result);
29474#endif
29475break;
29476break;
29477case Arg::Index:
29478#if CPU(X86) || CPU(X86_64)
29479jit.or32(args[0].asTrustedImm32(), args[1].asBaseIndex());
29480OPGEN_RETURN(result);
29481#endif
29482break;
29483break;
29484default:
29485break;
29486}
29487break;
29488case Arg::Addr:
29489case Arg::Stack:
29490case Arg::CallArg:
29491#if CPU(X86) || CPU(X86_64)
29492jit.or32(args[0].asAddress(), args[1].gpr());
29493OPGEN_RETURN(result);
29494#endif
29495break;
29496break;
29497case Arg::Index:
29498#if CPU(X86) || CPU(X86_64)
29499jit.or32(args[0].asBaseIndex(), args[1].gpr());
29500OPGEN_RETURN(result);
29501#endif
29502break;
29503break;
29504default:
29505break;
29506}
29507break;
29508default:
29509break;
29510}
29511break;
29512case Opcode::Or64:
29513switch (this->args.size()) {
29514case 3:
29515switch (this->args[0].kind()) {
29516case Arg::Tmp:
29517#if CPU(X86_64) || CPU(ARM64)
29518jit.or64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29519OPGEN_RETURN(result);
29520#endif
29521break;
29522break;
29523#if USE(JSVALUE64)
29524case Arg::BitImm64:
29525#if CPU(ARM64)
29526jit.or64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
29527OPGEN_RETURN(result);
29528#endif
29529break;
29530break;
29531#endif // USE(JSVALUE64)
29532default:
29533break;
29534}
29535break;
29536case 2:
29537switch (this->args[0].kind()) {
29538case Arg::Tmp:
29539switch (this->args[1].kind()) {
29540case Arg::Tmp:
29541#if CPU(X86_64) || CPU(ARM64)
29542jit.or64(args[0].gpr(), args[1].gpr());
29543OPGEN_RETURN(result);
29544#endif
29545break;
29546break;
29547case Arg::Addr:
29548case Arg::Stack:
29549case Arg::CallArg:
29550#if CPU(X86_64)
29551jit.or64(args[0].gpr(), args[1].asAddress());
29552OPGEN_RETURN(result);
29553#endif
29554break;
29555break;
29556case Arg::Index:
29557#if CPU(X86_64)
29558jit.or64(args[0].gpr(), args[1].asBaseIndex());
29559OPGEN_RETURN(result);
29560#endif
29561break;
29562break;
29563default:
29564break;
29565}
29566break;
29567case Arg::Imm:
29568switch (this->args[1].kind()) {
29569case Arg::Tmp:
29570#if CPU(X86_64)
29571jit.or64(args[0].asTrustedImm32(), args[1].gpr());
29572OPGEN_RETURN(result);
29573#endif
29574break;
29575break;
29576case Arg::Addr:
29577case Arg::Stack:
29578case Arg::CallArg:
29579#if CPU(X86_64)
29580jit.or64(args[0].asTrustedImm32(), args[1].asAddress());
29581OPGEN_RETURN(result);
29582#endif
29583break;
29584break;
29585case Arg::Index:
29586#if CPU(X86_64)
29587jit.or64(args[0].asTrustedImm32(), args[1].asBaseIndex());
29588OPGEN_RETURN(result);
29589#endif
29590break;
29591break;
29592default:
29593break;
29594}
29595break;
29596case Arg::Addr:
29597case Arg::Stack:
29598case Arg::CallArg:
29599#if CPU(X86_64)
29600jit.or64(args[0].asAddress(), args[1].gpr());
29601OPGEN_RETURN(result);
29602#endif
29603break;
29604break;
29605case Arg::Index:
29606#if CPU(X86_64)
29607jit.or64(args[0].asBaseIndex(), args[1].gpr());
29608OPGEN_RETURN(result);
29609#endif
29610break;
29611break;
29612default:
29613break;
29614}
29615break;
29616default:
29617break;
29618}
29619break;
29620case Opcode::Xor32:
29621switch (this->args.size()) {
29622case 3:
29623switch (this->args[0].kind()) {
29624case Arg::Tmp:
29625switch (this->args[1].kind()) {
29626case Arg::Tmp:
29627jit.xor32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29628OPGEN_RETURN(result);
29629break;
29630break;
29631case Arg::Addr:
29632case Arg::Stack:
29633case Arg::CallArg:
29634#if CPU(X86) || CPU(X86_64)
29635jit.xor32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
29636OPGEN_RETURN(result);
29637#endif
29638break;
29639break;
29640default:
29641break;
29642}
29643break;
29644case Arg::BitImm:
29645#if CPU(ARM64)
29646jit.xor32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
29647OPGEN_RETURN(result);
29648#endif
29649break;
29650break;
29651case Arg::Addr:
29652case Arg::Stack:
29653case Arg::CallArg:
29654#if CPU(X86) || CPU(X86_64)
29655jit.xor32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
29656OPGEN_RETURN(result);
29657#endif
29658break;
29659break;
29660default:
29661break;
29662}
29663break;
29664case 2:
29665switch (this->args[0].kind()) {
29666case Arg::Tmp:
29667switch (this->args[1].kind()) {
29668case Arg::Tmp:
29669jit.xor32(args[0].gpr(), args[1].gpr());
29670OPGEN_RETURN(result);
29671break;
29672break;
29673case Arg::Addr:
29674case Arg::Stack:
29675case Arg::CallArg:
29676#if CPU(X86) || CPU(X86_64)
29677jit.xor32(args[0].gpr(), args[1].asAddress());
29678OPGEN_RETURN(result);
29679#endif
29680break;
29681break;
29682case Arg::Index:
29683#if CPU(X86) || CPU(X86_64)
29684jit.xor32(args[0].gpr(), args[1].asBaseIndex());
29685OPGEN_RETURN(result);
29686#endif
29687break;
29688break;
29689default:
29690break;
29691}
29692break;
29693case Arg::Imm:
29694switch (this->args[1].kind()) {
29695case Arg::Tmp:
29696#if CPU(X86) || CPU(X86_64)
29697jit.xor32(args[0].asTrustedImm32(), args[1].gpr());
29698OPGEN_RETURN(result);
29699#endif
29700break;
29701break;
29702case Arg::Addr:
29703case Arg::Stack:
29704case Arg::CallArg:
29705#if CPU(X86) || CPU(X86_64)
29706jit.xor32(args[0].asTrustedImm32(), args[1].asAddress());
29707OPGEN_RETURN(result);
29708#endif
29709break;
29710break;
29711case Arg::Index:
29712#if CPU(X86) || CPU(X86_64)
29713jit.xor32(args[0].asTrustedImm32(), args[1].asBaseIndex());
29714OPGEN_RETURN(result);
29715#endif
29716break;
29717break;
29718default:
29719break;
29720}
29721break;
29722case Arg::Addr:
29723case Arg::Stack:
29724case Arg::CallArg:
29725#if CPU(X86) || CPU(X86_64)
29726jit.xor32(args[0].asAddress(), args[1].gpr());
29727OPGEN_RETURN(result);
29728#endif
29729break;
29730break;
29731case Arg::Index:
29732#if CPU(X86) || CPU(X86_64)
29733jit.xor32(args[0].asBaseIndex(), args[1].gpr());
29734OPGEN_RETURN(result);
29735#endif
29736break;
29737break;
29738default:
29739break;
29740}
29741break;
29742default:
29743break;
29744}
29745break;
29746case Opcode::Xor64:
29747switch (this->args.size()) {
29748case 3:
29749switch (this->args[0].kind()) {
29750case Arg::Tmp:
29751#if CPU(X86_64) || CPU(ARM64)
29752jit.xor64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29753OPGEN_RETURN(result);
29754#endif
29755break;
29756break;
29757#if USE(JSVALUE64)
29758case Arg::BitImm64:
29759#if CPU(ARM64)
29760jit.xor64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
29761OPGEN_RETURN(result);
29762#endif
29763break;
29764break;
29765#endif // USE(JSVALUE64)
29766default:
29767break;
29768}
29769break;
29770case 2:
29771switch (this->args[0].kind()) {
29772case Arg::Tmp:
29773switch (this->args[1].kind()) {
29774case Arg::Tmp:
29775#if CPU(X86_64) || CPU(ARM64)
29776jit.xor64(args[0].gpr(), args[1].gpr());
29777OPGEN_RETURN(result);
29778#endif
29779break;
29780break;
29781case Arg::Addr:
29782case Arg::Stack:
29783case Arg::CallArg:
29784#if CPU(X86_64)
29785jit.xor64(args[0].gpr(), args[1].asAddress());
29786OPGEN_RETURN(result);
29787#endif
29788break;
29789break;
29790case Arg::Index:
29791#if CPU(X86_64)
29792jit.xor64(args[0].gpr(), args[1].asBaseIndex());
29793OPGEN_RETURN(result);
29794#endif
29795break;
29796break;
29797default:
29798break;
29799}
29800break;
29801case Arg::Addr:
29802case Arg::Stack:
29803case Arg::CallArg:
29804#if CPU(X86_64)
29805jit.xor64(args[0].asAddress(), args[1].gpr());
29806OPGEN_RETURN(result);
29807#endif
29808break;
29809break;
29810case Arg::Index:
29811#if CPU(X86_64)
29812jit.xor64(args[0].asBaseIndex(), args[1].gpr());
29813OPGEN_RETURN(result);
29814#endif
29815break;
29816break;
29817case Arg::Imm:
29818switch (this->args[1].kind()) {
29819case Arg::Addr:
29820case Arg::Stack:
29821case Arg::CallArg:
29822#if CPU(X86_64)
29823jit.xor64(args[0].asTrustedImm32(), args[1].asAddress());
29824OPGEN_RETURN(result);
29825#endif
29826break;
29827break;
29828case Arg::Index:
29829#if CPU(X86_64)
29830jit.xor64(args[0].asTrustedImm32(), args[1].asBaseIndex());
29831OPGEN_RETURN(result);
29832#endif
29833break;
29834break;
29835case Arg::Tmp:
29836#if CPU(X86_64)
29837jit.xor64(args[0].asTrustedImm32(), args[1].gpr());
29838OPGEN_RETURN(result);
29839#endif
29840break;
29841break;
29842default:
29843break;
29844}
29845break;
29846default:
29847break;
29848}
29849break;
29850default:
29851break;
29852}
29853break;
29854case Opcode::Not32:
29855switch (this->args.size()) {
29856case 2:
29857#if CPU(ARM64)
29858jit.not32(args[0].gpr(), args[1].gpr());
29859OPGEN_RETURN(result);
29860#endif
29861break;
29862break;
29863case 1:
29864switch (this->args[0].kind()) {
29865case Arg::Tmp:
29866#if CPU(X86) || CPU(X86_64)
29867jit.not32(args[0].gpr());
29868OPGEN_RETURN(result);
29869#endif
29870break;
29871break;
29872case Arg::Addr:
29873case Arg::Stack:
29874case Arg::CallArg:
29875#if CPU(X86) || CPU(X86_64)
29876jit.not32(args[0].asAddress());
29877OPGEN_RETURN(result);
29878#endif
29879break;
29880break;
29881case Arg::Index:
29882#if CPU(X86) || CPU(X86_64)
29883jit.not32(args[0].asBaseIndex());
29884OPGEN_RETURN(result);
29885#endif
29886break;
29887break;
29888default:
29889break;
29890}
29891break;
29892default:
29893break;
29894}
29895break;
29896case Opcode::Not64:
29897switch (this->args.size()) {
29898case 2:
29899#if CPU(ARM64)
29900jit.not64(args[0].gpr(), args[1].gpr());
29901OPGEN_RETURN(result);
29902#endif
29903break;
29904break;
29905case 1:
29906switch (this->args[0].kind()) {
29907case Arg::Tmp:
29908#if CPU(X86_64)
29909jit.not64(args[0].gpr());
29910OPGEN_RETURN(result);
29911#endif
29912break;
29913break;
29914case Arg::Addr:
29915case Arg::Stack:
29916case Arg::CallArg:
29917#if CPU(X86_64)
29918jit.not64(args[0].asAddress());
29919OPGEN_RETURN(result);
29920#endif
29921break;
29922break;
29923case Arg::Index:
29924#if CPU(X86_64)
29925jit.not64(args[0].asBaseIndex());
29926OPGEN_RETURN(result);
29927#endif
29928break;
29929break;
29930default:
29931break;
29932}
29933break;
29934default:
29935break;
29936}
29937break;
29938case Opcode::AbsDouble:
29939#if CPU(ARM64)
29940jit.absDouble(args[0].fpr(), args[1].fpr());
29941OPGEN_RETURN(result);
29942#endif
29943break;
29944break;
29945case Opcode::AbsFloat:
29946#if CPU(ARM64)
29947jit.absFloat(args[0].fpr(), args[1].fpr());
29948OPGEN_RETURN(result);
29949#endif
29950break;
29951break;
29952case Opcode::CeilDouble:
29953switch (this->args[0].kind()) {
29954case Arg::Tmp:
29955jit.ceilDouble(args[0].fpr(), args[1].fpr());
29956OPGEN_RETURN(result);
29957break;
29958break;
29959case Arg::Addr:
29960case Arg::Stack:
29961case Arg::CallArg:
29962#if CPU(X86) || CPU(X86_64)
29963jit.ceilDouble(args[0].asAddress(), args[1].fpr());
29964OPGEN_RETURN(result);
29965#endif
29966break;
29967break;
29968default:
29969break;
29970}
29971break;
29972case Opcode::CeilFloat:
29973switch (this->args[0].kind()) {
29974case Arg::Tmp:
29975jit.ceilFloat(args[0].fpr(), args[1].fpr());
29976OPGEN_RETURN(result);
29977break;
29978break;
29979case Arg::Addr:
29980case Arg::Stack:
29981case Arg::CallArg:
29982#if CPU(X86) || CPU(X86_64)
29983jit.ceilFloat(args[0].asAddress(), args[1].fpr());
29984OPGEN_RETURN(result);
29985#endif
29986break;
29987break;
29988default:
29989break;
29990}
29991break;
29992case Opcode::FloorDouble:
29993switch (this->args[0].kind()) {
29994case Arg::Tmp:
29995jit.floorDouble(args[0].fpr(), args[1].fpr());
29996OPGEN_RETURN(result);
29997break;
29998break;
29999case Arg::Addr:
30000case Arg::Stack:
30001case Arg::CallArg:
30002#if CPU(X86) || CPU(X86_64)
30003jit.floorDouble(args[0].asAddress(), args[1].fpr());
30004OPGEN_RETURN(result);
30005#endif
30006break;
30007break;
30008default:
30009break;
30010}
30011break;
30012case Opcode::FloorFloat:
30013switch (this->args[0].kind()) {
30014case Arg::Tmp:
30015jit.floorFloat(args[0].fpr(), args[1].fpr());
30016OPGEN_RETURN(result);
30017break;
30018break;
30019case Arg::Addr:
30020case Arg::Stack:
30021case Arg::CallArg:
30022#if CPU(X86) || CPU(X86_64)
30023jit.floorFloat(args[0].asAddress(), args[1].fpr());
30024OPGEN_RETURN(result);
30025#endif
30026break;
30027break;
30028default:
30029break;
30030}
30031break;
30032case Opcode::SqrtDouble:
30033switch (this->args[0].kind()) {
30034case Arg::Tmp:
30035jit.sqrtDouble(args[0].fpr(), args[1].fpr());
30036OPGEN_RETURN(result);
30037break;
30038break;
30039case Arg::Addr:
30040case Arg::Stack:
30041case Arg::CallArg:
30042#if CPU(X86) || CPU(X86_64)
30043jit.sqrtDouble(args[0].asAddress(), args[1].fpr());
30044OPGEN_RETURN(result);
30045#endif
30046break;
30047break;
30048default:
30049break;
30050}
30051break;
30052case Opcode::SqrtFloat:
30053switch (this->args[0].kind()) {
30054case Arg::Tmp:
30055jit.sqrtFloat(args[0].fpr(), args[1].fpr());
30056OPGEN_RETURN(result);
30057break;
30058break;
30059case Arg::Addr:
30060case Arg::Stack:
30061case Arg::CallArg:
30062#if CPU(X86) || CPU(X86_64)
30063jit.sqrtFloat(args[0].asAddress(), args[1].fpr());
30064OPGEN_RETURN(result);
30065#endif
30066break;
30067break;
30068default:
30069break;
30070}
30071break;
30072case Opcode::ConvertInt32ToDouble:
30073switch (this->args[0].kind()) {
30074case Arg::Tmp:
30075jit.convertInt32ToDouble(args[0].gpr(), args[1].fpr());
30076OPGEN_RETURN(result);
30077break;
30078break;
30079case Arg::Addr:
30080case Arg::Stack:
30081case Arg::CallArg:
30082#if CPU(X86) || CPU(X86_64)
30083jit.convertInt32ToDouble(args[0].asAddress(), args[1].fpr());
30084OPGEN_RETURN(result);
30085#endif
30086break;
30087break;
30088default:
30089break;
30090}
30091break;
30092case Opcode::ConvertInt64ToDouble:
30093switch (this->args[0].kind()) {
30094case Arg::Tmp:
30095#if CPU(X86_64) || CPU(ARM64)
30096jit.convertInt64ToDouble(args[0].gpr(), args[1].fpr());
30097OPGEN_RETURN(result);
30098#endif
30099break;
30100break;
30101case Arg::Addr:
30102case Arg::Stack:
30103case Arg::CallArg:
30104#if CPU(X86_64)
30105jit.convertInt64ToDouble(args[0].asAddress(), args[1].fpr());
30106OPGEN_RETURN(result);
30107#endif
30108break;
30109break;
30110default:
30111break;
30112}
30113break;
30114case Opcode::ConvertInt32ToFloat:
30115switch (this->args[0].kind()) {
30116case Arg::Tmp:
30117jit.convertInt32ToFloat(args[0].gpr(), args[1].fpr());
30118OPGEN_RETURN(result);
30119break;
30120break;
30121case Arg::Addr:
30122case Arg::Stack:
30123case Arg::CallArg:
30124#if CPU(X86) || CPU(X86_64)
30125jit.convertInt32ToFloat(args[0].asAddress(), args[1].fpr());
30126OPGEN_RETURN(result);
30127#endif
30128break;
30129break;
30130default:
30131break;
30132}
30133break;
30134case Opcode::ConvertInt64ToFloat:
30135switch (this->args[0].kind()) {
30136case Arg::Tmp:
30137#if CPU(X86_64) || CPU(ARM64)
30138jit.convertInt64ToFloat(args[0].gpr(), args[1].fpr());
30139OPGEN_RETURN(result);
30140#endif
30141break;
30142break;
30143case Arg::Addr:
30144case Arg::Stack:
30145case Arg::CallArg:
30146#if CPU(X86_64)
30147jit.convertInt64ToFloat(args[0].asAddress(), args[1].fpr());
30148OPGEN_RETURN(result);
30149#endif
30150break;
30151break;
30152default:
30153break;
30154}
30155break;
30156case Opcode::CountLeadingZeros32:
30157switch (this->args[0].kind()) {
30158case Arg::Tmp:
30159jit.countLeadingZeros32(args[0].gpr(), args[1].gpr());
30160OPGEN_RETURN(result);
30161break;
30162break;
30163case Arg::Addr:
30164case Arg::Stack:
30165case Arg::CallArg:
30166#if CPU(X86) || CPU(X86_64)
30167jit.countLeadingZeros32(args[0].asAddress(), args[1].gpr());
30168OPGEN_RETURN(result);
30169#endif
30170break;
30171break;
30172default:
30173break;
30174}
30175break;
30176case Opcode::CountLeadingZeros64:
30177switch (this->args[0].kind()) {
30178case Arg::Tmp:
30179#if CPU(X86_64) || CPU(ARM64)
30180jit.countLeadingZeros64(args[0].gpr(), args[1].gpr());
30181OPGEN_RETURN(result);
30182#endif
30183break;
30184break;
30185case Arg::Addr:
30186case Arg::Stack:
30187case Arg::CallArg:
30188#if CPU(X86_64)
30189jit.countLeadingZeros64(args[0].asAddress(), args[1].gpr());
30190OPGEN_RETURN(result);
30191#endif
30192break;
30193break;
30194default:
30195break;
30196}
30197break;
30198case Opcode::ConvertDoubleToFloat:
30199switch (this->args[0].kind()) {
30200case Arg::Tmp:
30201jit.convertDoubleToFloat(args[0].fpr(), args[1].fpr());
30202OPGEN_RETURN(result);
30203break;
30204break;
30205case Arg::Addr:
30206case Arg::Stack:
30207case Arg::CallArg:
30208#if CPU(X86) || CPU(X86_64)
30209jit.convertDoubleToFloat(args[0].asAddress(), args[1].fpr());
30210OPGEN_RETURN(result);
30211#endif
30212break;
30213break;
30214default:
30215break;
30216}
30217break;
30218case Opcode::ConvertFloatToDouble:
30219switch (this->args[0].kind()) {
30220case Arg::Tmp:
30221jit.convertFloatToDouble(args[0].fpr(), args[1].fpr());
30222OPGEN_RETURN(result);
30223break;
30224break;
30225case Arg::Addr:
30226case Arg::Stack:
30227case Arg::CallArg:
30228#if CPU(X86) || CPU(X86_64)
30229jit.convertFloatToDouble(args[0].asAddress(), args[1].fpr());
30230OPGEN_RETURN(result);
30231#endif
30232break;
30233break;
30234default:
30235break;
30236}
30237break;
30238case Opcode::Move:
30239switch (this->args.size()) {
30240case 2:
30241switch (this->args[0].kind()) {
30242case Arg::Tmp:
30243switch (this->args[1].kind()) {
30244case Arg::Tmp:
30245jit.move(args[0].gpr(), args[1].gpr());
30246OPGEN_RETURN(result);
30247break;
30248break;
30249case Arg::Addr:
30250case Arg::Stack:
30251case Arg::CallArg:
30252jit.storePtr(args[0].gpr(), args[1].asAddress());
30253OPGEN_RETURN(result);
30254break;
30255break;
30256case Arg::Index:
30257jit.storePtr(args[0].gpr(), args[1].asBaseIndex());
30258OPGEN_RETURN(result);
30259break;
30260break;
30261default:
30262break;
30263}
30264break;
30265case Arg::Imm:
30266switch (this->args[1].kind()) {
30267case Arg::Tmp:
30268jit.signExtend32ToPtr(args[0].asTrustedImm32(), args[1].gpr());
30269OPGEN_RETURN(result);
30270break;
30271break;
30272case Arg::Addr:
30273case Arg::Stack:
30274case Arg::CallArg:
30275#if CPU(X86) || CPU(X86_64)
30276jit.storePtr(args[0].asTrustedImm32(), args[1].asAddress());
30277OPGEN_RETURN(result);
30278#endif
30279break;
30280break;
30281default:
30282break;
30283}
30284break;
30285#if USE(JSVALUE64)
30286case Arg::BigImm:
30287jit.move(args[0].asTrustedImm64(), args[1].gpr());
30288OPGEN_RETURN(result);
30289break;
30290break;
30291#endif // USE(JSVALUE64)
30292case Arg::Addr:
30293case Arg::Stack:
30294case Arg::CallArg:
30295jit.loadPtr(args[0].asAddress(), args[1].gpr());
30296OPGEN_RETURN(result);
30297break;
30298break;
30299case Arg::Index:
30300jit.loadPtr(args[0].asBaseIndex(), args[1].gpr());
30301OPGEN_RETURN(result);
30302break;
30303break;
30304default:
30305break;
30306}
30307break;
30308case 3:
30309jit.move(args[0].asAddress(), args[1].asAddress(), args[2].gpr());
30310OPGEN_RETURN(result);
30311break;
30312break;
30313default:
30314break;
30315}
30316break;
30317case Opcode::Swap32:
30318switch (this->args[1].kind()) {
30319case Arg::Tmp:
30320#if CPU(X86) || CPU(X86_64)
30321jit.swap32(args[0].gpr(), args[1].gpr());
30322OPGEN_RETURN(result);
30323#endif
30324break;
30325break;
30326case Arg::Addr:
30327case Arg::Stack:
30328case Arg::CallArg:
30329#if CPU(X86) || CPU(X86_64)
30330jit.swap32(args[0].gpr(), args[1].asAddress());
30331OPGEN_RETURN(result);
30332#endif
30333break;
30334break;
30335default:
30336break;
30337}
30338break;
30339case Opcode::Swap64:
30340switch (this->args[1].kind()) {
30341case Arg::Tmp:
30342#if CPU(X86_64)
30343jit.swap64(args[0].gpr(), args[1].gpr());
30344OPGEN_RETURN(result);
30345#endif
30346break;
30347break;
30348case Arg::Addr:
30349case Arg::Stack:
30350case Arg::CallArg:
30351#if CPU(X86_64)
30352jit.swap64(args[0].gpr(), args[1].asAddress());
30353OPGEN_RETURN(result);
30354#endif
30355break;
30356break;
30357default:
30358break;
30359}
30360break;
30361case Opcode::Move32:
30362switch (this->args.size()) {
30363case 2:
30364switch (this->args[0].kind()) {
30365case Arg::Tmp:
30366switch (this->args[1].kind()) {
30367case Arg::Tmp:
30368jit.zeroExtend32ToPtr(args[0].gpr(), args[1].gpr());
30369OPGEN_RETURN(result);
30370break;
30371break;
30372case Arg::Addr:
30373case Arg::Stack:
30374case Arg::CallArg:
30375jit.store32(args[0].gpr(), args[1].asAddress());
30376OPGEN_RETURN(result);
30377break;
30378break;
30379case Arg::Index:
30380jit.store32(args[0].gpr(), args[1].asBaseIndex());
30381OPGEN_RETURN(result);
30382break;
30383break;
30384default:
30385break;
30386}
30387break;
30388case Arg::Addr:
30389case Arg::Stack:
30390case Arg::CallArg:
30391jit.load32(args[0].asAddress(), args[1].gpr());
30392OPGEN_RETURN(result);
30393break;
30394break;
30395case Arg::Index:
30396jit.load32(args[0].asBaseIndex(), args[1].gpr());
30397OPGEN_RETURN(result);
30398break;
30399break;
30400case Arg::Imm:
30401switch (this->args[1].kind()) {
30402case Arg::Tmp:
30403#if CPU(X86) || CPU(X86_64)
30404jit.zeroExtend32ToPtr(args[0].asTrustedImm32(), args[1].gpr());
30405OPGEN_RETURN(result);
30406#endif
30407break;
30408break;
30409case Arg::Addr:
30410case Arg::Stack:
30411case Arg::CallArg:
30412#if CPU(X86) || CPU(X86_64)
30413jit.store32(args[0].asTrustedImm32(), args[1].asAddress());
30414OPGEN_RETURN(result);
30415#endif
30416break;
30417break;
30418case Arg::Index:
30419#if CPU(X86) || CPU(X86_64)
30420jit.store32(args[0].asTrustedImm32(), args[1].asBaseIndex());
30421OPGEN_RETURN(result);
30422#endif
30423break;
30424break;
30425default:
30426break;
30427}
30428break;
30429default:
30430break;
30431}
30432break;
30433case 3:
30434jit.move32(args[0].asAddress(), args[1].asAddress(), args[2].gpr());
30435OPGEN_RETURN(result);
30436break;
30437break;
30438default:
30439break;
30440}
30441break;
30442case Opcode::StoreZero32:
30443switch (this->args[0].kind()) {
30444case Arg::Addr:
30445case Arg::Stack:
30446case Arg::CallArg:
30447jit.storeZero32(args[0].asAddress());
30448OPGEN_RETURN(result);
30449break;
30450break;
30451case Arg::Index:
30452jit.storeZero32(args[0].asBaseIndex());
30453OPGEN_RETURN(result);
30454break;
30455break;
30456default:
30457break;
30458}
30459break;
30460case Opcode::StoreZero64:
30461switch (this->args[0].kind()) {
30462case Arg::Addr:
30463case Arg::Stack:
30464case Arg::CallArg:
30465#if CPU(X86_64) || CPU(ARM64)
30466jit.storeZero64(args[0].asAddress());
30467OPGEN_RETURN(result);
30468#endif
30469break;
30470break;
30471case Arg::Index:
30472#if CPU(X86_64) || CPU(ARM64)
30473jit.storeZero64(args[0].asBaseIndex());
30474OPGEN_RETURN(result);
30475#endif
30476break;
30477break;
30478default:
30479break;
30480}
30481break;
30482case Opcode::SignExtend32ToPtr:
30483jit.signExtend32ToPtr(args[0].gpr(), args[1].gpr());
30484OPGEN_RETURN(result);
30485break;
30486break;
30487case Opcode::ZeroExtend8To32:
30488switch (this->args[0].kind()) {
30489case Arg::Tmp:
30490jit.zeroExtend8To32(args[0].gpr(), args[1].gpr());
30491OPGEN_RETURN(result);
30492break;
30493break;
30494case Arg::Addr:
30495case Arg::Stack:
30496case Arg::CallArg:
30497#if CPU(X86) || CPU(X86_64)
30498jit.load8(args[0].asAddress(), args[1].gpr());
30499OPGEN_RETURN(result);
30500#endif
30501break;
30502break;
30503case Arg::Index:
30504#if CPU(X86) || CPU(X86_64)
30505jit.load8(args[0].asBaseIndex(), args[1].gpr());
30506OPGEN_RETURN(result);
30507#endif
30508break;
30509break;
30510default:
30511break;
30512}
30513break;
30514case Opcode::SignExtend8To32:
30515switch (this->args[0].kind()) {
30516case Arg::Tmp:
30517jit.signExtend8To32(args[0].gpr(), args[1].gpr());
30518OPGEN_RETURN(result);
30519break;
30520break;
30521case Arg::Addr:
30522case Arg::Stack:
30523case Arg::CallArg:
30524#if CPU(X86) || CPU(X86_64)
30525jit.load8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30526OPGEN_RETURN(result);
30527#endif
30528break;
30529break;
30530case Arg::Index:
30531#if CPU(X86) || CPU(X86_64)
30532jit.load8SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30533OPGEN_RETURN(result);
30534#endif
30535break;
30536break;
30537default:
30538break;
30539}
30540break;
30541case Opcode::ZeroExtend16To32:
30542switch (this->args[0].kind()) {
30543case Arg::Tmp:
30544jit.zeroExtend16To32(args[0].gpr(), args[1].gpr());
30545OPGEN_RETURN(result);
30546break;
30547break;
30548case Arg::Addr:
30549case Arg::Stack:
30550case Arg::CallArg:
30551#if CPU(X86) || CPU(X86_64)
30552jit.load16(args[0].asAddress(), args[1].gpr());
30553OPGEN_RETURN(result);
30554#endif
30555break;
30556break;
30557case Arg::Index:
30558#if CPU(X86) || CPU(X86_64)
30559jit.load16(args[0].asBaseIndex(), args[1].gpr());
30560OPGEN_RETURN(result);
30561#endif
30562break;
30563break;
30564default:
30565break;
30566}
30567break;
30568case Opcode::SignExtend16To32:
30569switch (this->args[0].kind()) {
30570case Arg::Tmp:
30571jit.signExtend16To32(args[0].gpr(), args[1].gpr());
30572OPGEN_RETURN(result);
30573break;
30574break;
30575case Arg::Addr:
30576case Arg::Stack:
30577case Arg::CallArg:
30578#if CPU(X86) || CPU(X86_64)
30579jit.load16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30580OPGEN_RETURN(result);
30581#endif
30582break;
30583break;
30584case Arg::Index:
30585#if CPU(X86) || CPU(X86_64)
30586jit.load16SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30587OPGEN_RETURN(result);
30588#endif
30589break;
30590break;
30591default:
30592break;
30593}
30594break;
30595case Opcode::MoveFloat:
30596switch (this->args.size()) {
30597case 2:
30598switch (this->args[0].kind()) {
30599case Arg::Tmp:
30600switch (this->args[1].kind()) {
30601case Arg::Tmp:
30602jit.moveDouble(args[0].fpr(), args[1].fpr());
30603OPGEN_RETURN(result);
30604break;
30605break;
30606case Arg::Addr:
30607case Arg::Stack:
30608case Arg::CallArg:
30609jit.storeFloat(args[0].fpr(), args[1].asAddress());
30610OPGEN_RETURN(result);
30611break;
30612break;
30613case Arg::Index:
30614jit.storeFloat(args[0].fpr(), args[1].asBaseIndex());
30615OPGEN_RETURN(result);
30616break;
30617break;
30618default:
30619break;
30620}
30621break;
30622case Arg::Addr:
30623case Arg::Stack:
30624case Arg::CallArg:
30625jit.loadFloat(args[0].asAddress(), args[1].fpr());
30626OPGEN_RETURN(result);
30627break;
30628break;
30629case Arg::Index:
30630jit.loadFloat(args[0].asBaseIndex(), args[1].fpr());
30631OPGEN_RETURN(result);
30632break;
30633break;
30634default:
30635break;
30636}
30637break;
30638case 3:
30639jit.moveFloat(args[0].asAddress(), args[1].asAddress(), args[2].fpr());
30640OPGEN_RETURN(result);
30641break;
30642break;
30643default:
30644break;
30645}
30646break;
30647case Opcode::MoveDouble:
30648switch (this->args.size()) {
30649case 2:
30650switch (this->args[0].kind()) {
30651case Arg::Tmp:
30652switch (this->args[1].kind()) {
30653case Arg::Tmp:
30654jit.moveDouble(args[0].fpr(), args[1].fpr());
30655OPGEN_RETURN(result);
30656break;
30657break;
30658case Arg::Addr:
30659case Arg::Stack:
30660case Arg::CallArg:
30661jit.storeDouble(args[0].fpr(), args[1].asAddress());
30662OPGEN_RETURN(result);
30663break;
30664break;
30665case Arg::Index:
30666jit.storeDouble(args[0].fpr(), args[1].asBaseIndex());
30667OPGEN_RETURN(result);
30668break;
30669break;
30670default:
30671break;
30672}
30673break;
30674case Arg::Addr:
30675case Arg::Stack:
30676case Arg::CallArg:
30677jit.loadDouble(args[0].asAddress(), args[1].fpr());
30678OPGEN_RETURN(result);
30679break;
30680break;
30681case Arg::Index:
30682jit.loadDouble(args[0].asBaseIndex(), args[1].fpr());
30683OPGEN_RETURN(result);
30684break;
30685break;
30686default:
30687break;
30688}
30689break;
30690case 3:
30691jit.moveDouble(args[0].asAddress(), args[1].asAddress(), args[2].fpr());
30692OPGEN_RETURN(result);
30693break;
30694break;
30695default:
30696break;
30697}
30698break;
30699case Opcode::MoveZeroToDouble:
30700jit.moveZeroToDouble(args[0].fpr());
30701OPGEN_RETURN(result);
30702break;
30703break;
30704case Opcode::Move64ToDouble:
30705switch (this->args[0].kind()) {
30706case Arg::Tmp:
30707#if CPU(X86_64) || CPU(ARM64)
30708jit.move64ToDouble(args[0].gpr(), args[1].fpr());
30709OPGEN_RETURN(result);
30710#endif
30711break;
30712break;
30713case Arg::Addr:
30714case Arg::Stack:
30715case Arg::CallArg:
30716#if CPU(X86_64)
30717jit.loadDouble(args[0].asAddress(), args[1].fpr());
30718OPGEN_RETURN(result);
30719#endif
30720break;
30721break;
30722case Arg::Index:
30723#if CPU(X86_64) || CPU(ARM64)
30724jit.loadDouble(args[0].asBaseIndex(), args[1].fpr());
30725OPGEN_RETURN(result);
30726#endif
30727break;
30728break;
30729default:
30730break;
30731}
30732break;
30733case Opcode::Move32ToFloat:
30734switch (this->args[0].kind()) {
30735case Arg::Tmp:
30736jit.move32ToFloat(args[0].gpr(), args[1].fpr());
30737OPGEN_RETURN(result);
30738break;
30739break;
30740case Arg::Addr:
30741case Arg::Stack:
30742case Arg::CallArg:
30743#if CPU(X86) || CPU(X86_64)
30744jit.loadFloat(args[0].asAddress(), args[1].fpr());
30745OPGEN_RETURN(result);
30746#endif
30747break;
30748break;
30749case Arg::Index:
30750jit.loadFloat(args[0].asBaseIndex(), args[1].fpr());
30751OPGEN_RETURN(result);
30752break;
30753break;
30754default:
30755break;
30756}
30757break;
30758case Opcode::MoveDoubleTo64:
30759switch (this->args[0].kind()) {
30760case Arg::Tmp:
30761#if CPU(X86_64) || CPU(ARM64)
30762jit.moveDoubleTo64(args[0].fpr(), args[1].gpr());
30763OPGEN_RETURN(result);
30764#endif
30765break;
30766break;
30767case Arg::Addr:
30768case Arg::Stack:
30769case Arg::CallArg:
30770#if CPU(X86_64) || CPU(ARM64)
30771jit.load64(args[0].asAddress(), args[1].gpr());
30772OPGEN_RETURN(result);
30773#endif
30774break;
30775break;
30776case Arg::Index:
30777#if CPU(X86_64) || CPU(ARM64)
30778jit.load64(args[0].asBaseIndex(), args[1].gpr());
30779OPGEN_RETURN(result);
30780#endif
30781break;
30782break;
30783default:
30784break;
30785}
30786break;
30787case Opcode::MoveFloatTo32:
30788switch (this->args[0].kind()) {
30789case Arg::Tmp:
30790jit.moveFloatTo32(args[0].fpr(), args[1].gpr());
30791OPGEN_RETURN(result);
30792break;
30793break;
30794case Arg::Addr:
30795case Arg::Stack:
30796case Arg::CallArg:
30797jit.load32(args[0].asAddress(), args[1].gpr());
30798OPGEN_RETURN(result);
30799break;
30800break;
30801case Arg::Index:
30802jit.load32(args[0].asBaseIndex(), args[1].gpr());
30803OPGEN_RETURN(result);
30804break;
30805break;
30806default:
30807break;
30808}
30809break;
30810case Opcode::Load8:
30811switch (this->args[0].kind()) {
30812case Arg::Addr:
30813case Arg::Stack:
30814case Arg::CallArg:
30815jit.load8(args[0].asAddress(), args[1].gpr());
30816OPGEN_RETURN(result);
30817break;
30818break;
30819case Arg::Index:
30820jit.load8(args[0].asBaseIndex(), args[1].gpr());
30821OPGEN_RETURN(result);
30822break;
30823break;
30824default:
30825break;
30826}
30827break;
30828case Opcode::LoadAcq8:
30829#if CPU(ARMv7) || CPU(ARM64)
30830jit.loadAcq8(args[0].asAddress(), args[1].gpr());
30831OPGEN_RETURN(result);
30832#endif
30833break;
30834break;
30835case Opcode::Store8:
30836switch (this->args[0].kind()) {
30837case Arg::Tmp:
30838switch (this->args[1].kind()) {
30839case Arg::Index:
30840jit.store8(args[0].gpr(), args[1].asBaseIndex());
30841OPGEN_RETURN(result);
30842break;
30843break;
30844case Arg::Addr:
30845case Arg::Stack:
30846case Arg::CallArg:
30847jit.store8(args[0].gpr(), args[1].asAddress());
30848OPGEN_RETURN(result);
30849break;
30850break;
30851default:
30852break;
30853}
30854break;
30855case Arg::Imm:
30856switch (this->args[1].kind()) {
30857case Arg::Index:
30858#if CPU(X86) || CPU(X86_64)
30859jit.store8(args[0].asTrustedImm32(), args[1].asBaseIndex());
30860OPGEN_RETURN(result);
30861#endif
30862break;
30863break;
30864case Arg::Addr:
30865case Arg::Stack:
30866case Arg::CallArg:
30867#if CPU(X86) || CPU(X86_64)
30868jit.store8(args[0].asTrustedImm32(), args[1].asAddress());
30869OPGEN_RETURN(result);
30870#endif
30871break;
30872break;
30873default:
30874break;
30875}
30876break;
30877default:
30878break;
30879}
30880break;
30881case Opcode::StoreRel8:
30882#if CPU(ARMv7) || CPU(ARM64)
30883jit.storeRel8(args[0].gpr(), args[1].asAddress());
30884OPGEN_RETURN(result);
30885#endif
30886break;
30887break;
30888case Opcode::Load8SignedExtendTo32:
30889switch (this->args[0].kind()) {
30890case Arg::Addr:
30891case Arg::Stack:
30892case Arg::CallArg:
30893jit.load8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30894OPGEN_RETURN(result);
30895break;
30896break;
30897case Arg::Index:
30898jit.load8SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30899OPGEN_RETURN(result);
30900break;
30901break;
30902default:
30903break;
30904}
30905break;
30906case Opcode::LoadAcq8SignedExtendTo32:
30907#if CPU(ARMv7) || CPU(ARM64)
30908jit.loadAcq8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30909OPGEN_RETURN(result);
30910#endif
30911break;
30912break;
30913case Opcode::Load16:
30914switch (this->args[0].kind()) {
30915case Arg::Addr:
30916case Arg::Stack:
30917case Arg::CallArg:
30918jit.load16(args[0].asAddress(), args[1].gpr());
30919OPGEN_RETURN(result);
30920break;
30921break;
30922case Arg::Index:
30923jit.load16(args[0].asBaseIndex(), args[1].gpr());
30924OPGEN_RETURN(result);
30925break;
30926break;
30927default:
30928break;
30929}
30930break;
30931case Opcode::LoadAcq16:
30932#if CPU(ARMv7) || CPU(ARM64)
30933jit.loadAcq16(args[0].asAddress(), args[1].gpr());
30934OPGEN_RETURN(result);
30935#endif
30936break;
30937break;
30938case Opcode::Load16SignedExtendTo32:
30939switch (this->args[0].kind()) {
30940case Arg::Addr:
30941case Arg::Stack:
30942case Arg::CallArg:
30943jit.load16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30944OPGEN_RETURN(result);
30945break;
30946break;
30947case Arg::Index:
30948jit.load16SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30949OPGEN_RETURN(result);
30950break;
30951break;
30952default:
30953break;
30954}
30955break;
30956case Opcode::LoadAcq16SignedExtendTo32:
30957#if CPU(ARMv7) || CPU(ARM64)
30958jit.loadAcq16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30959OPGEN_RETURN(result);
30960#endif
30961break;
30962break;
30963case Opcode::Store16:
30964switch (this->args[0].kind()) {
30965case Arg::Tmp:
30966switch (this->args[1].kind()) {
30967case Arg::Index:
30968jit.store16(args[0].gpr(), args[1].asBaseIndex());
30969OPGEN_RETURN(result);
30970break;
30971break;
30972case Arg::Addr:
30973case Arg::Stack:
30974case Arg::CallArg:
30975jit.store16(args[0].gpr(), args[1].asAddress());
30976OPGEN_RETURN(result);
30977break;
30978break;
30979default:
30980break;
30981}
30982break;
30983case Arg::Imm:
30984switch (this->args[1].kind()) {
30985case Arg::Index:
30986#if CPU(X86) || CPU(X86_64)
30987jit.store16(args[0].asTrustedImm32(), args[1].asBaseIndex());
30988OPGEN_RETURN(result);
30989#endif
30990break;
30991break;
30992case Arg::Addr:
30993case Arg::Stack:
30994case Arg::CallArg:
30995#if CPU(X86) || CPU(X86_64)
30996jit.store16(args[0].asTrustedImm32(), args[1].asAddress());
30997OPGEN_RETURN(result);
30998#endif
30999break;
31000break;
31001default:
31002break;
31003}
31004break;
31005default:
31006break;
31007}
31008break;
31009case Opcode::StoreRel16:
31010#if CPU(ARMv7) || CPU(ARM64)
31011jit.storeRel16(args[0].gpr(), args[1].asAddress());
31012OPGEN_RETURN(result);
31013#endif
31014break;
31015break;
31016case Opcode::LoadAcq32:
31017#if CPU(ARMv7) || CPU(ARM64)
31018jit.loadAcq32(args[0].asAddress(), args[1].gpr());
31019OPGEN_RETURN(result);
31020#endif
31021break;
31022break;
31023case Opcode::StoreRel32:
31024#if CPU(ARMv7) || CPU(ARM64)
31025jit.storeRel32(args[0].gpr(), args[1].asAddress());
31026OPGEN_RETURN(result);
31027#endif
31028break;
31029break;
31030case Opcode::LoadAcq64:
31031#if CPU(ARM64)
31032jit.loadAcq64(args[0].asAddress(), args[1].gpr());
31033OPGEN_RETURN(result);
31034#endif
31035break;
31036break;
31037case Opcode::StoreRel64:
31038#if CPU(ARM64)
31039jit.storeRel64(args[0].gpr(), args[1].asAddress());
31040OPGEN_RETURN(result);
31041#endif
31042break;
31043break;
31044case Opcode::Xchg8:
31045switch (this->args[1].kind()) {
31046case Arg::Addr:
31047case Arg::Stack:
31048case Arg::CallArg:
31049#if CPU(X86) || CPU(X86_64)
31050jit.xchg8(args[0].gpr(), args[1].asAddress());
31051OPGEN_RETURN(result);
31052#endif
31053break;
31054break;
31055case Arg::Index:
31056#if CPU(X86) || CPU(X86_64)
31057jit.xchg8(args[0].gpr(), args[1].asBaseIndex());
31058OPGEN_RETURN(result);
31059#endif
31060break;
31061break;
31062default:
31063break;
31064}
31065break;
31066case Opcode::Xchg16:
31067switch (this->args[1].kind()) {
31068case Arg::Addr:
31069case Arg::Stack:
31070case Arg::CallArg:
31071#if CPU(X86) || CPU(X86_64)
31072jit.xchg16(args[0].gpr(), args[1].asAddress());
31073OPGEN_RETURN(result);
31074#endif
31075break;
31076break;
31077case Arg::Index:
31078#if CPU(X86) || CPU(X86_64)
31079jit.xchg16(args[0].gpr(), args[1].asBaseIndex());
31080OPGEN_RETURN(result);
31081#endif
31082break;
31083break;
31084default:
31085break;
31086}
31087break;
31088case Opcode::Xchg32:
31089switch (this->args[1].kind()) {
31090case Arg::Addr:
31091case Arg::Stack:
31092case Arg::CallArg:
31093#if CPU(X86) || CPU(X86_64)
31094jit.xchg32(args[0].gpr(), args[1].asAddress());
31095OPGEN_RETURN(result);
31096#endif
31097break;
31098break;
31099case Arg::Index:
31100#if CPU(X86) || CPU(X86_64)
31101jit.xchg32(args[0].gpr(), args[1].asBaseIndex());
31102OPGEN_RETURN(result);
31103#endif
31104break;
31105break;
31106default:
31107break;
31108}
31109break;
31110case Opcode::Xchg64:
31111switch (this->args[1].kind()) {
31112case Arg::Addr:
31113case Arg::Stack:
31114case Arg::CallArg:
31115#if CPU(X86_64)
31116jit.xchg64(args[0].gpr(), args[1].asAddress());
31117OPGEN_RETURN(result);
31118#endif
31119break;
31120break;
31121case Arg::Index:
31122#if CPU(X86_64)
31123jit.xchg64(args[0].gpr(), args[1].asBaseIndex());
31124OPGEN_RETURN(result);
31125#endif
31126break;
31127break;
31128default:
31129break;
31130}
31131break;
31132case Opcode::AtomicStrongCAS8:
31133switch (this->args.size()) {
31134case 5:
31135switch (this->args[3].kind()) {
31136case Arg::Addr:
31137case Arg::Stack:
31138case Arg::CallArg:
31139#if CPU(X86) || CPU(X86_64)
31140jit.atomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
31141OPGEN_RETURN(result);
31142#endif
31143break;
31144break;
31145case Arg::Index:
31146#if CPU(X86) || CPU(X86_64)
31147jit.atomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
31148OPGEN_RETURN(result);
31149#endif
31150break;
31151break;
31152default:
31153break;
31154}
31155break;
31156case 3:
31157switch (this->args[2].kind()) {
31158case Arg::Addr:
31159case Arg::Stack:
31160case Arg::CallArg:
31161#if CPU(X86) || CPU(X86_64)
31162jit.atomicStrongCAS8(args[0].gpr(), args[1].gpr(), args[2].asAddress());
31163OPGEN_RETURN(result);
31164#endif
31165break;
31166break;
31167case Arg::Index:
31168#if CPU(X86) || CPU(X86_64)
31169jit.atomicStrongCAS8(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
31170OPGEN_RETURN(result);
31171#endif
31172break;
31173break;
31174default:
31175break;
31176}
31177break;
31178default:
31179break;
31180}
31181break;
31182case Opcode::AtomicStrongCAS16:
31183switch (this->args.size()) {
31184case 5:
31185switch (this->args[3].kind()) {
31186case Arg::Addr:
31187case Arg::Stack:
31188case Arg::CallArg:
31189#if CPU(X86) || CPU(X86_64)
31190jit.atomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
31191OPGEN_RETURN(result);
31192#endif
31193break;
31194break;
31195case Arg::Index:
31196#if CPU(X86) || CPU(X86_64)
31197jit.atomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
31198OPGEN_RETURN(result);
31199#endif
31200break;
31201break;
31202default:
31203break;
31204}
31205break;
31206case 3:
31207switch (this->args[2].kind()) {
31208case Arg::Addr:
31209case Arg::Stack:
31210case Arg::CallArg:
31211#if CPU(X86) || CPU(X86_64)
31212jit.atomicStrongCAS16(args[0].gpr(), args[1].gpr(), args[2].asAddress());
31213OPGEN_RETURN(result);
31214#endif
31215break;
31216break;
31217case Arg::Index:
31218#if CPU(X86) || CPU(X86_64)
31219jit.atomicStrongCAS16(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
31220OPGEN_RETURN(result);
31221#endif
31222break;
31223break;
31224default:
31225break;
31226}
31227break;
31228default:
31229break;
31230}
31231break;
31232case Opcode::AtomicStrongCAS32:
31233switch (this->args.size()) {
31234case 5:
31235switch (this->args[3].kind()) {
31236case Arg::Addr:
31237case Arg::Stack:
31238case Arg::CallArg:
31239#if CPU(X86) || CPU(X86_64)
31240jit.atomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
31241OPGEN_RETURN(result);
31242#endif
31243break;
31244break;
31245case Arg::Index:
31246#if CPU(X86) || CPU(X86_64)
31247jit.atomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
31248OPGEN_RETURN(result);
31249#endif
31250break;
31251break;
31252default:
31253break;
31254}
31255break;
31256case 3:
31257switch (this->args[2].kind()) {
31258case Arg::Addr:
31259case Arg::Stack:
31260case Arg::CallArg:
31261#if CPU(X86) || CPU(X86_64)
31262jit.atomicStrongCAS32(args[0].gpr(), args[1].gpr(), args[2].asAddress());
31263OPGEN_RETURN(result);
31264#endif
31265break;
31266break;
31267case Arg::Index:
31268#if CPU(X86) || CPU(X86_64)
31269jit.atomicStrongCAS32(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
31270OPGEN_RETURN(result);
31271#endif
31272break;
31273break;
31274default:
31275break;
31276}
31277break;
31278default:
31279break;
31280}
31281break;
31282case Opcode::AtomicStrongCAS64:
31283switch (this->args.size()) {
31284case 5:
31285switch (this->args[3].kind()) {
31286case Arg::Addr:
31287case Arg::Stack:
31288case Arg::CallArg:
31289#if CPU(X86_64)
31290jit.atomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
31291OPGEN_RETURN(result);
31292#endif
31293break;
31294break;
31295case Arg::Index:
31296#if CPU(X86_64)
31297jit.atomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
31298OPGEN_RETURN(result);
31299#endif
31300break;
31301break;
31302default:
31303break;
31304}
31305break;
31306case 3:
31307switch (this->args[2].kind()) {
31308case Arg::Addr:
31309case Arg::Stack:
31310case Arg::CallArg:
31311#if CPU(X86_64)
31312jit.atomicStrongCAS64(args[0].gpr(), args[1].gpr(), args[2].asAddress());
31313OPGEN_RETURN(result);
31314#endif
31315break;
31316break;
31317case Arg::Index:
31318#if CPU(X86_64)
31319jit.atomicStrongCAS64(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
31320OPGEN_RETURN(result);
31321#endif
31322break;
31323break;
31324default:
31325break;
31326}
31327break;
31328default:
31329break;
31330}
31331break;
31332case Opcode::BranchAtomicStrongCAS8:
31333switch (this->args[3].kind()) {
31334case Arg::Addr:
31335case Arg::Stack:
31336case Arg::CallArg:
31337#if CPU(X86) || CPU(X86_64)
31338result = jit.branchAtomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31339OPGEN_RETURN(result);
31340#endif
31341break;
31342break;
31343case Arg::Index:
31344#if CPU(X86) || CPU(X86_64)
31345result = jit.branchAtomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31346OPGEN_RETURN(result);
31347#endif
31348break;
31349break;
31350default:
31351break;
31352}
31353break;
31354case Opcode::BranchAtomicStrongCAS16:
31355switch (this->args[3].kind()) {
31356case Arg::Addr:
31357case Arg::Stack:
31358case Arg::CallArg:
31359#if CPU(X86) || CPU(X86_64)
31360result = jit.branchAtomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31361OPGEN_RETURN(result);
31362#endif
31363break;
31364break;
31365case Arg::Index:
31366#if CPU(X86) || CPU(X86_64)
31367result = jit.branchAtomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31368OPGEN_RETURN(result);
31369#endif
31370break;
31371break;
31372default:
31373break;
31374}
31375break;
31376case Opcode::BranchAtomicStrongCAS32:
31377switch (this->args[3].kind()) {
31378case Arg::Addr:
31379case Arg::Stack:
31380case Arg::CallArg:
31381#if CPU(X86) || CPU(X86_64)
31382result = jit.branchAtomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31383OPGEN_RETURN(result);
31384#endif
31385break;
31386break;
31387case Arg::Index:
31388#if CPU(X86) || CPU(X86_64)
31389result = jit.branchAtomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31390OPGEN_RETURN(result);
31391#endif
31392break;
31393break;
31394default:
31395break;
31396}
31397break;
31398case Opcode::BranchAtomicStrongCAS64:
31399switch (this->args[3].kind()) {
31400case Arg::Addr:
31401case Arg::Stack:
31402case Arg::CallArg:
31403#if CPU(X86_64)
31404result = jit.branchAtomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31405OPGEN_RETURN(result);
31406#endif
31407break;
31408break;
31409case Arg::Index:
31410#if CPU(X86_64)
31411result = jit.branchAtomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31412OPGEN_RETURN(result);
31413#endif
31414break;
31415break;
31416default:
31417break;
31418}
31419break;
31420case Opcode::AtomicAdd8:
31421switch (this->args[0].kind()) {
31422case Arg::Imm:
31423switch (this->args[1].kind()) {
31424case Arg::Addr:
31425case Arg::Stack:
31426case Arg::CallArg:
31427#if CPU(X86) || CPU(X86_64)
31428jit.atomicAdd8(args[0].asTrustedImm32(), args[1].asAddress());
31429OPGEN_RETURN(result);
31430#endif
31431break;
31432break;
31433case Arg::Index:
31434#if CPU(X86) || CPU(X86_64)
31435jit.atomicAdd8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31436OPGEN_RETURN(result);
31437#endif
31438break;
31439break;
31440default:
31441break;
31442}
31443break;
31444case Arg::Tmp:
31445switch (this->args[1].kind()) {
31446case Arg::Addr:
31447case Arg::Stack:
31448case Arg::CallArg:
31449#if CPU(X86) || CPU(X86_64)
31450jit.atomicAdd8(args[0].gpr(), args[1].asAddress());
31451OPGEN_RETURN(result);
31452#endif
31453break;
31454break;
31455case Arg::Index:
31456#if CPU(X86) || CPU(X86_64)
31457jit.atomicAdd8(args[0].gpr(), args[1].asBaseIndex());
31458OPGEN_RETURN(result);
31459#endif
31460break;
31461break;
31462default:
31463break;
31464}
31465break;
31466default:
31467break;
31468}
31469break;
31470case Opcode::AtomicAdd16:
31471switch (this->args[0].kind()) {
31472case Arg::Imm:
31473switch (this->args[1].kind()) {
31474case Arg::Addr:
31475case Arg::Stack:
31476case Arg::CallArg:
31477#if CPU(X86) || CPU(X86_64)
31478jit.atomicAdd16(args[0].asTrustedImm32(), args[1].asAddress());
31479OPGEN_RETURN(result);
31480#endif
31481break;
31482break;
31483case Arg::Index:
31484#if CPU(X86) || CPU(X86_64)
31485jit.atomicAdd16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31486OPGEN_RETURN(result);
31487#endif
31488break;
31489break;
31490default:
31491break;
31492}
31493break;
31494case Arg::Tmp:
31495switch (this->args[1].kind()) {
31496case Arg::Addr:
31497case Arg::Stack:
31498case Arg::CallArg:
31499#if CPU(X86) || CPU(X86_64)
31500jit.atomicAdd16(args[0].gpr(), args[1].asAddress());
31501OPGEN_RETURN(result);
31502#endif
31503break;
31504break;
31505case Arg::Index:
31506#if CPU(X86) || CPU(X86_64)
31507jit.atomicAdd16(args[0].gpr(), args[1].asBaseIndex());
31508OPGEN_RETURN(result);
31509#endif
31510break;
31511break;
31512default:
31513break;
31514}
31515break;
31516default:
31517break;
31518}
31519break;
31520case Opcode::AtomicAdd32:
31521switch (this->args[0].kind()) {
31522case Arg::Imm:
31523switch (this->args[1].kind()) {
31524case Arg::Addr:
31525case Arg::Stack:
31526case Arg::CallArg:
31527#if CPU(X86) || CPU(X86_64)
31528jit.atomicAdd32(args[0].asTrustedImm32(), args[1].asAddress());
31529OPGEN_RETURN(result);
31530#endif
31531break;
31532break;
31533case Arg::Index:
31534#if CPU(X86) || CPU(X86_64)
31535jit.atomicAdd32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31536OPGEN_RETURN(result);
31537#endif
31538break;
31539break;
31540default:
31541break;
31542}
31543break;
31544case Arg::Tmp:
31545switch (this->args[1].kind()) {
31546case Arg::Addr:
31547case Arg::Stack:
31548case Arg::CallArg:
31549#if CPU(X86) || CPU(X86_64)
31550jit.atomicAdd32(args[0].gpr(), args[1].asAddress());
31551OPGEN_RETURN(result);
31552#endif
31553break;
31554break;
31555case Arg::Index:
31556#if CPU(X86) || CPU(X86_64)
31557jit.atomicAdd32(args[0].gpr(), args[1].asBaseIndex());
31558OPGEN_RETURN(result);
31559#endif
31560break;
31561break;
31562default:
31563break;
31564}
31565break;
31566default:
31567break;
31568}
31569break;
31570case Opcode::AtomicAdd64:
31571switch (this->args[0].kind()) {
31572case Arg::Imm:
31573switch (this->args[1].kind()) {
31574case Arg::Addr:
31575case Arg::Stack:
31576case Arg::CallArg:
31577#if CPU(X86_64)
31578jit.atomicAdd64(args[0].asTrustedImm32(), args[1].asAddress());
31579OPGEN_RETURN(result);
31580#endif
31581break;
31582break;
31583case Arg::Index:
31584#if CPU(X86_64)
31585jit.atomicAdd64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31586OPGEN_RETURN(result);
31587#endif
31588break;
31589break;
31590default:
31591break;
31592}
31593break;
31594case Arg::Tmp:
31595switch (this->args[1].kind()) {
31596case Arg::Addr:
31597case Arg::Stack:
31598case Arg::CallArg:
31599#if CPU(X86_64)
31600jit.atomicAdd64(args[0].gpr(), args[1].asAddress());
31601OPGEN_RETURN(result);
31602#endif
31603break;
31604break;
31605case Arg::Index:
31606#if CPU(X86_64)
31607jit.atomicAdd64(args[0].gpr(), args[1].asBaseIndex());
31608OPGEN_RETURN(result);
31609#endif
31610break;
31611break;
31612default:
31613break;
31614}
31615break;
31616default:
31617break;
31618}
31619break;
31620case Opcode::AtomicSub8:
31621switch (this->args[0].kind()) {
31622case Arg::Imm:
31623switch (this->args[1].kind()) {
31624case Arg::Addr:
31625case Arg::Stack:
31626case Arg::CallArg:
31627#if CPU(X86) || CPU(X86_64)
31628jit.atomicSub8(args[0].asTrustedImm32(), args[1].asAddress());
31629OPGEN_RETURN(result);
31630#endif
31631break;
31632break;
31633case Arg::Index:
31634#if CPU(X86) || CPU(X86_64)
31635jit.atomicSub8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31636OPGEN_RETURN(result);
31637#endif
31638break;
31639break;
31640default:
31641break;
31642}
31643break;
31644case Arg::Tmp:
31645switch (this->args[1].kind()) {
31646case Arg::Addr:
31647case Arg::Stack:
31648case Arg::CallArg:
31649#if CPU(X86) || CPU(X86_64)
31650jit.atomicSub8(args[0].gpr(), args[1].asAddress());
31651OPGEN_RETURN(result);
31652#endif
31653break;
31654break;
31655case Arg::Index:
31656#if CPU(X86) || CPU(X86_64)
31657jit.atomicSub8(args[0].gpr(), args[1].asBaseIndex());
31658OPGEN_RETURN(result);
31659#endif
31660break;
31661break;
31662default:
31663break;
31664}
31665break;
31666default:
31667break;
31668}
31669break;
31670case Opcode::AtomicSub16:
31671switch (this->args[0].kind()) {
31672case Arg::Imm:
31673switch (this->args[1].kind()) {
31674case Arg::Addr:
31675case Arg::Stack:
31676case Arg::CallArg:
31677#if CPU(X86) || CPU(X86_64)
31678jit.atomicSub16(args[0].asTrustedImm32(), args[1].asAddress());
31679OPGEN_RETURN(result);
31680#endif
31681break;
31682break;
31683case Arg::Index:
31684#if CPU(X86) || CPU(X86_64)
31685jit.atomicSub16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31686OPGEN_RETURN(result);
31687#endif
31688break;
31689break;
31690default:
31691break;
31692}
31693break;
31694case Arg::Tmp:
31695switch (this->args[1].kind()) {
31696case Arg::Addr:
31697case Arg::Stack:
31698case Arg::CallArg:
31699#if CPU(X86) || CPU(X86_64)
31700jit.atomicSub16(args[0].gpr(), args[1].asAddress());
31701OPGEN_RETURN(result);
31702#endif
31703break;
31704break;
31705case Arg::Index:
31706#if CPU(X86) || CPU(X86_64)
31707jit.atomicSub16(args[0].gpr(), args[1].asBaseIndex());
31708OPGEN_RETURN(result);
31709#endif
31710break;
31711break;
31712default:
31713break;
31714}
31715break;
31716default:
31717break;
31718}
31719break;
31720case Opcode::AtomicSub32:
31721switch (this->args[0].kind()) {
31722case Arg::Imm:
31723switch (this->args[1].kind()) {
31724case Arg::Addr:
31725case Arg::Stack:
31726case Arg::CallArg:
31727#if CPU(X86) || CPU(X86_64)
31728jit.atomicSub32(args[0].asTrustedImm32(), args[1].asAddress());
31729OPGEN_RETURN(result);
31730#endif
31731break;
31732break;
31733case Arg::Index:
31734#if CPU(X86) || CPU(X86_64)
31735jit.atomicSub32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31736OPGEN_RETURN(result);
31737#endif
31738break;
31739break;
31740default:
31741break;
31742}
31743break;
31744case Arg::Tmp:
31745switch (this->args[1].kind()) {
31746case Arg::Addr:
31747case Arg::Stack:
31748case Arg::CallArg:
31749#if CPU(X86) || CPU(X86_64)
31750jit.atomicSub32(args[0].gpr(), args[1].asAddress());
31751OPGEN_RETURN(result);
31752#endif
31753break;
31754break;
31755case Arg::Index:
31756#if CPU(X86) || CPU(X86_64)
31757jit.atomicSub32(args[0].gpr(), args[1].asBaseIndex());
31758OPGEN_RETURN(result);
31759#endif
31760break;
31761break;
31762default:
31763break;
31764}
31765break;
31766default:
31767break;
31768}
31769break;
31770case Opcode::AtomicSub64:
31771switch (this->args[0].kind()) {
31772case Arg::Imm:
31773switch (this->args[1].kind()) {
31774case Arg::Addr:
31775case Arg::Stack:
31776case Arg::CallArg:
31777#if CPU(X86_64)
31778jit.atomicSub64(args[0].asTrustedImm32(), args[1].asAddress());
31779OPGEN_RETURN(result);
31780#endif
31781break;
31782break;
31783case Arg::Index:
31784#if CPU(X86_64)
31785jit.atomicSub64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31786OPGEN_RETURN(result);
31787#endif
31788break;
31789break;
31790default:
31791break;
31792}
31793break;
31794case Arg::Tmp:
31795switch (this->args[1].kind()) {
31796case Arg::Addr:
31797case Arg::Stack:
31798case Arg::CallArg:
31799#if CPU(X86_64)
31800jit.atomicSub64(args[0].gpr(), args[1].asAddress());
31801OPGEN_RETURN(result);
31802#endif
31803break;
31804break;
31805case Arg::Index:
31806#if CPU(X86_64)
31807jit.atomicSub64(args[0].gpr(), args[1].asBaseIndex());
31808OPGEN_RETURN(result);
31809#endif
31810break;
31811break;
31812default:
31813break;
31814}
31815break;
31816default:
31817break;
31818}
31819break;
31820case Opcode::AtomicAnd8:
31821switch (this->args[0].kind()) {
31822case Arg::Imm:
31823switch (this->args[1].kind()) {
31824case Arg::Addr:
31825case Arg::Stack:
31826case Arg::CallArg:
31827#if CPU(X86) || CPU(X86_64)
31828jit.atomicAnd8(args[0].asTrustedImm32(), args[1].asAddress());
31829OPGEN_RETURN(result);
31830#endif
31831break;
31832break;
31833case Arg::Index:
31834#if CPU(X86) || CPU(X86_64)
31835jit.atomicAnd8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31836OPGEN_RETURN(result);
31837#endif
31838break;
31839break;
31840default:
31841break;
31842}
31843break;
31844case Arg::Tmp:
31845switch (this->args[1].kind()) {
31846case Arg::Addr:
31847case Arg::Stack:
31848case Arg::CallArg:
31849#if CPU(X86) || CPU(X86_64)
31850jit.atomicAnd8(args[0].gpr(), args[1].asAddress());
31851OPGEN_RETURN(result);
31852#endif
31853break;
31854break;
31855case Arg::Index:
31856#if CPU(X86) || CPU(X86_64)
31857jit.atomicAnd8(args[0].gpr(), args[1].asBaseIndex());
31858OPGEN_RETURN(result);
31859#endif
31860break;
31861break;
31862default:
31863break;
31864}
31865break;
31866default:
31867break;
31868}
31869break;
31870case Opcode::AtomicAnd16:
31871switch (this->args[0].kind()) {
31872case Arg::Imm:
31873switch (this->args[1].kind()) {
31874case Arg::Addr:
31875case Arg::Stack:
31876case Arg::CallArg:
31877#if CPU(X86) || CPU(X86_64)
31878jit.atomicAnd16(args[0].asTrustedImm32(), args[1].asAddress());
31879OPGEN_RETURN(result);
31880#endif
31881break;
31882break;
31883case Arg::Index:
31884#if CPU(X86) || CPU(X86_64)
31885jit.atomicAnd16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31886OPGEN_RETURN(result);
31887#endif
31888break;
31889break;
31890default:
31891break;
31892}
31893break;
31894case Arg::Tmp:
31895switch (this->args[1].kind()) {
31896case Arg::Addr:
31897case Arg::Stack:
31898case Arg::CallArg:
31899#if CPU(X86) || CPU(X86_64)
31900jit.atomicAnd16(args[0].gpr(), args[1].asAddress());
31901OPGEN_RETURN(result);
31902#endif
31903break;
31904break;
31905case Arg::Index:
31906#if CPU(X86) || CPU(X86_64)
31907jit.atomicAnd16(args[0].gpr(), args[1].asBaseIndex());
31908OPGEN_RETURN(result);
31909#endif
31910break;
31911break;
31912default:
31913break;
31914}
31915break;
31916default:
31917break;
31918}
31919break;
31920case Opcode::AtomicAnd32:
31921switch (this->args[0].kind()) {
31922case Arg::Imm:
31923switch (this->args[1].kind()) {
31924case Arg::Addr:
31925case Arg::Stack:
31926case Arg::CallArg:
31927#if CPU(X86) || CPU(X86_64)
31928jit.atomicAnd32(args[0].asTrustedImm32(), args[1].asAddress());
31929OPGEN_RETURN(result);
31930#endif
31931break;
31932break;
31933case Arg::Index:
31934#if CPU(X86) || CPU(X86_64)
31935jit.atomicAnd32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31936OPGEN_RETURN(result);
31937#endif
31938break;
31939break;
31940default:
31941break;
31942}
31943break;
31944case Arg::Tmp:
31945switch (this->args[1].kind()) {
31946case Arg::Addr:
31947case Arg::Stack:
31948case Arg::CallArg:
31949#if CPU(X86) || CPU(X86_64)
31950jit.atomicAnd32(args[0].gpr(), args[1].asAddress());
31951OPGEN_RETURN(result);
31952#endif
31953break;
31954break;
31955case Arg::Index:
31956#if CPU(X86) || CPU(X86_64)
31957jit.atomicAnd32(args[0].gpr(), args[1].asBaseIndex());
31958OPGEN_RETURN(result);
31959#endif
31960break;
31961break;
31962default:
31963break;
31964}
31965break;
31966default:
31967break;
31968}
31969break;
31970case Opcode::AtomicAnd64:
31971switch (this->args[0].kind()) {
31972case Arg::Imm:
31973switch (this->args[1].kind()) {
31974case Arg::Addr:
31975case Arg::Stack:
31976case Arg::CallArg:
31977#if CPU(X86_64)
31978jit.atomicAnd64(args[0].asTrustedImm32(), args[1].asAddress());
31979OPGEN_RETURN(result);
31980#endif
31981break;
31982break;
31983case Arg::Index:
31984#if CPU(X86_64)
31985jit.atomicAnd64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31986OPGEN_RETURN(result);
31987#endif
31988break;
31989break;
31990default:
31991break;
31992}
31993break;
31994case Arg::Tmp:
31995switch (this->args[1].kind()) {
31996case Arg::Addr:
31997case Arg::Stack:
31998case Arg::CallArg:
31999#if CPU(X86_64)
32000jit.atomicAnd64(args[0].gpr(), args[1].asAddress());
32001OPGEN_RETURN(result);
32002#endif
32003break;
32004break;
32005case Arg::Index:
32006#if CPU(X86_64)
32007jit.atomicAnd64(args[0].gpr(), args[1].asBaseIndex());
32008OPGEN_RETURN(result);
32009#endif
32010break;
32011break;
32012default:
32013break;
32014}
32015break;
32016default:
32017break;
32018}
32019break;
32020case Opcode::AtomicOr8:
32021switch (this->args[0].kind()) {
32022case Arg::Imm:
32023switch (this->args[1].kind()) {
32024case Arg::Addr:
32025case Arg::Stack:
32026case Arg::CallArg:
32027#if CPU(X86) || CPU(X86_64)
32028jit.atomicOr8(args[0].asTrustedImm32(), args[1].asAddress());
32029OPGEN_RETURN(result);
32030#endif
32031break;
32032break;
32033case Arg::Index:
32034#if CPU(X86) || CPU(X86_64)
32035jit.atomicOr8(args[0].asTrustedImm32(), args[1].asBaseIndex());
32036OPGEN_RETURN(result);
32037#endif
32038break;
32039break;
32040default:
32041break;
32042}
32043break;
32044case Arg::Tmp:
32045switch (this->args[1].kind()) {
32046case Arg::Addr:
32047case Arg::Stack:
32048case Arg::CallArg:
32049#if CPU(X86) || CPU(X86_64)
32050jit.atomicOr8(args[0].gpr(), args[1].asAddress());
32051OPGEN_RETURN(result);
32052#endif
32053break;
32054break;
32055case Arg::Index:
32056#if CPU(X86) || CPU(X86_64)
32057jit.atomicOr8(args[0].gpr(), args[1].asBaseIndex());
32058OPGEN_RETURN(result);
32059#endif
32060break;
32061break;
32062default:
32063break;
32064}
32065break;
32066default:
32067break;
32068}
32069break;
32070case Opcode::AtomicOr16:
32071switch (this->args[0].kind()) {
32072case Arg::Imm:
32073switch (this->args[1].kind()) {
32074case Arg::Addr:
32075case Arg::Stack:
32076case Arg::CallArg:
32077#if CPU(X86) || CPU(X86_64)
32078jit.atomicOr16(args[0].asTrustedImm32(), args[1].asAddress());
32079OPGEN_RETURN(result);
32080#endif
32081break;
32082break;
32083case Arg::Index:
32084#if CPU(X86) || CPU(X86_64)
32085jit.atomicOr16(args[0].asTrustedImm32(), args[1].asBaseIndex());
32086OPGEN_RETURN(result);
32087#endif
32088break;
32089break;
32090default:
32091break;
32092}
32093break;
32094case Arg::Tmp:
32095switch (this->args[1].kind()) {
32096case Arg::Addr:
32097case Arg::Stack:
32098case Arg::CallArg:
32099#if CPU(X86) || CPU(X86_64)
32100jit.atomicOr16(args[0].gpr(), args[1].asAddress());
32101OPGEN_RETURN(result);
32102#endif
32103break;
32104break;
32105case Arg::Index:
32106#if CPU(X86) || CPU(X86_64)
32107jit.atomicOr16(args[0].gpr(), args[1].asBaseIndex());
32108OPGEN_RETURN(result);
32109#endif
32110break;
32111break;
32112default:
32113break;
32114}
32115break;
32116default:
32117break;
32118}
32119break;
32120case Opcode::AtomicOr32:
32121switch (this->args[0].kind()) {
32122case Arg::Imm:
32123switch (this->args[1].kind()) {
32124case Arg::Addr:
32125case Arg::Stack:
32126case Arg::CallArg:
32127#if CPU(X86) || CPU(X86_64)
32128jit.atomicOr32(args[0].asTrustedImm32(), args[1].asAddress());
32129OPGEN_RETURN(result);
32130#endif
32131break;
32132break;
32133case Arg::Index:
32134#if CPU(X86) || CPU(X86_64)
32135jit.atomicOr32(args[0].asTrustedImm32(), args[1].asBaseIndex());
32136OPGEN_RETURN(result);
32137#endif
32138break;
32139break;
32140default:
32141break;
32142}
32143break;
32144case Arg::Tmp:
32145switch (this->args[1].kind()) {
32146case Arg::Addr:
32147case Arg::Stack:
32148case Arg::CallArg:
32149#if CPU(X86) || CPU(X86_64)
32150jit.atomicOr32(args[0].gpr(), args[1].asAddress());
32151OPGEN_RETURN(result);
32152#endif
32153break;
32154break;
32155case Arg::Index:
32156#if CPU(X86) || CPU(X86_64)
32157jit.atomicOr32(args[0].gpr(), args[1].asBaseIndex());
32158OPGEN_RETURN(result);
32159#endif
32160break;
32161break;
32162default:
32163break;
32164}
32165break;
32166default:
32167break;
32168}
32169break;
32170case Opcode::AtomicOr64:
32171switch (this->args[0].kind()) {
32172case Arg::Imm:
32173switch (this->args[1].kind()) {
32174case Arg::Addr:
32175case Arg::Stack:
32176case Arg::CallArg:
32177#if CPU(X86_64)
32178jit.atomicOr64(args[0].asTrustedImm32(), args[1].asAddress());
32179OPGEN_RETURN(result);
32180#endif
32181break;
32182break;
32183case Arg::Index:
32184#if CPU(X86_64)
32185jit.atomicOr64(args[0].asTrustedImm32(), args[1].asBaseIndex());
32186OPGEN_RETURN(result);
32187#endif
32188break;
32189break;
32190default:
32191break;
32192}
32193break;
32194case Arg::Tmp:
32195switch (this->args[1].kind()) {
32196case Arg::Addr:
32197case Arg::Stack:
32198case Arg::CallArg:
32199#if CPU(X86_64)
32200jit.atomicOr64(args[0].gpr(), args[1].asAddress());
32201OPGEN_RETURN(result);
32202#endif
32203break;
32204break;
32205case Arg::Index:
32206#if CPU(X86_64)
32207jit.atomicOr64(args[0].gpr(), args[1].asBaseIndex());
32208OPGEN_RETURN(result);
32209#endif
32210break;
32211break;
32212default:
32213break;
32214}
32215break;
32216default:
32217break;
32218}
32219break;
32220case Opcode::AtomicXor8:
32221switch (this->args[0].kind()) {
32222case Arg::Imm:
32223switch (this->args[1].kind()) {
32224case Arg::Addr:
32225case Arg::Stack:
32226case Arg::CallArg:
32227#if CPU(X86) || CPU(X86_64)
32228jit.atomicXor8(args[0].asTrustedImm32(), args[1].asAddress());
32229OPGEN_RETURN(result);
32230#endif
32231break;
32232break;
32233case Arg::Index:
32234#if CPU(X86) || CPU(X86_64)
32235jit.atomicXor8(args[0].asTrustedImm32(), args[1].asBaseIndex());
32236OPGEN_RETURN(result);
32237#endif
32238break;
32239break;
32240default:
32241break;
32242}
32243break;
32244case Arg::Tmp:
32245switch (this->args[1].kind()) {
32246case Arg::Addr:
32247case Arg::Stack:
32248case Arg::CallArg:
32249#if CPU(X86) || CPU(X86_64)
32250jit.atomicXor8(args[0].gpr(), args[1].asAddress());
32251OPGEN_RETURN(result);
32252#endif
32253break;
32254break;
32255case Arg::Index:
32256#if CPU(X86) || CPU(X86_64)
32257jit.atomicXor8(args[0].gpr(), args[1].asBaseIndex());
32258OPGEN_RETURN(result);
32259#endif
32260break;
32261break;
32262default:
32263break;
32264}
32265break;
32266default:
32267break;
32268}
32269break;
32270case Opcode::AtomicXor16:
32271switch (this->args[0].kind()) {
32272case Arg::Imm:
32273switch (this->args[1].kind()) {
32274case Arg::Addr:
32275case Arg::Stack:
32276case Arg::CallArg:
32277#if CPU(X86) || CPU(X86_64)
32278jit.atomicXor16(args[0].asTrustedImm32(), args[1].asAddress());
32279OPGEN_RETURN(result);
32280#endif
32281break;
32282break;
32283case Arg::Index:
32284#if CPU(X86) || CPU(X86_64)
32285jit.atomicXor16(args[0].asTrustedImm32(), args[1].asBaseIndex());
32286OPGEN_RETURN(result);
32287#endif
32288break;
32289break;
32290default:
32291break;
32292}
32293break;
32294case Arg::Tmp:
32295switch (this->args[1].kind()) {
32296case Arg::Addr:
32297case Arg::Stack:
32298case Arg::CallArg:
32299#if CPU(X86) || CPU(X86_64)
32300jit.atomicXor16(args[0].gpr(), args[1].asAddress());
32301OPGEN_RETURN(result);
32302#endif
32303break;
32304break;
32305case Arg::Index:
32306#if CPU(X86) || CPU(X86_64)
32307jit.atomicXor16(args[0].gpr(), args[1].asBaseIndex());
32308OPGEN_RETURN(result);
32309#endif
32310break;
32311break;
32312default:
32313break;
32314}
32315break;
32316default:
32317break;
32318}
32319break;
32320case Opcode::AtomicXor32:
32321switch (this->args[0].kind()) {
32322case Arg::Imm:
32323switch (this->args[1].kind()) {
32324case Arg::Addr:
32325case Arg::Stack:
32326case Arg::CallArg:
32327#if CPU(X86) || CPU(X86_64)
32328jit.atomicXor32(args[0].asTrustedImm32(), args[1].asAddress());
32329OPGEN_RETURN(result);
32330#endif
32331break;
32332break;
32333case Arg::Index:
32334#if CPU(X86) || CPU(X86_64)
32335jit.atomicXor32(args[0].asTrustedImm32(), args[1].asBaseIndex());
32336OPGEN_RETURN(result);
32337#endif
32338break;
32339break;
32340default:
32341break;
32342}
32343break;
32344case Arg::Tmp:
32345switch (this->args[1].kind()) {
32346case Arg::Addr:
32347case Arg::Stack:
32348case Arg::CallArg:
32349#if CPU(X86) || CPU(X86_64)
32350jit.atomicXor32(args[0].gpr(), args[1].asAddress());
32351OPGEN_RETURN(result);
32352#endif
32353break;
32354break;
32355case Arg::Index:
32356#if CPU(X86) || CPU(X86_64)
32357jit.atomicXor32(args[0].gpr(), args[1].asBaseIndex());
32358OPGEN_RETURN(result);
32359#endif
32360break;
32361break;
32362default:
32363break;
32364}
32365break;
32366default:
32367break;
32368}
32369break;
32370case Opcode::AtomicXor64:
32371switch (this->args[0].kind()) {
32372case Arg::Imm:
32373switch (this->args[1].kind()) {
32374case Arg::Addr:
32375case Arg::Stack:
32376case Arg::CallArg:
32377#if CPU(X86_64)
32378jit.atomicXor64(args[0].asTrustedImm32(), args[1].asAddress());
32379OPGEN_RETURN(result);
32380#endif
32381break;
32382break;
32383case Arg::Index:
32384#if CPU(X86_64)
32385jit.atomicXor64(args[0].asTrustedImm32(), args[1].asBaseIndex());
32386OPGEN_RETURN(result);
32387#endif
32388break;
32389break;
32390default:
32391break;
32392}
32393break;
32394case Arg::Tmp:
32395switch (this->args[1].kind()) {
32396case Arg::Addr:
32397case Arg::Stack:
32398case Arg::CallArg:
32399#if CPU(X86_64)
32400jit.atomicXor64(args[0].gpr(), args[1].asAddress());
32401OPGEN_RETURN(result);
32402#endif
32403break;
32404break;
32405case Arg::Index:
32406#if CPU(X86_64)
32407jit.atomicXor64(args[0].gpr(), args[1].asBaseIndex());
32408OPGEN_RETURN(result);
32409#endif
32410break;
32411break;
32412default:
32413break;
32414}
32415break;
32416default:
32417break;
32418}
32419break;
32420case Opcode::AtomicNeg8:
32421switch (this->args[0].kind()) {
32422case Arg::Addr:
32423case Arg::Stack:
32424case Arg::CallArg:
32425#if CPU(X86) || CPU(X86_64)
32426jit.atomicNeg8(args[0].asAddress());
32427OPGEN_RETURN(result);
32428#endif
32429break;
32430break;
32431case Arg::Index:
32432#if CPU(X86) || CPU(X86_64)
32433jit.atomicNeg8(args[0].asBaseIndex());
32434OPGEN_RETURN(result);
32435#endif
32436break;
32437break;
32438default:
32439break;
32440}
32441break;
32442case Opcode::AtomicNeg16:
32443switch (this->args[0].kind()) {
32444case Arg::Addr:
32445case Arg::Stack:
32446case Arg::CallArg:
32447#if CPU(X86) || CPU(X86_64)
32448jit.atomicNeg16(args[0].asAddress());
32449OPGEN_RETURN(result);
32450#endif
32451break;
32452break;
32453case Arg::Index:
32454#if CPU(X86) || CPU(X86_64)
32455jit.atomicNeg16(args[0].asBaseIndex());
32456OPGEN_RETURN(result);
32457#endif
32458break;
32459break;
32460default:
32461break;
32462}
32463break;
32464case Opcode::AtomicNeg32:
32465switch (this->args[0].kind()) {
32466case Arg::Addr:
32467case Arg::Stack:
32468case Arg::CallArg:
32469#if CPU(X86) || CPU(X86_64)
32470jit.atomicNeg32(args[0].asAddress());
32471OPGEN_RETURN(result);
32472#endif
32473break;
32474break;
32475case Arg::Index:
32476#if CPU(X86) || CPU(X86_64)
32477jit.atomicNeg32(args[0].asBaseIndex());
32478OPGEN_RETURN(result);
32479#endif
32480break;
32481break;
32482default:
32483break;
32484}
32485break;
32486case Opcode::AtomicNeg64:
32487switch (this->args[0].kind()) {
32488case Arg::Addr:
32489case Arg::Stack:
32490case Arg::CallArg:
32491#if CPU(X86_64)
32492jit.atomicNeg64(args[0].asAddress());
32493OPGEN_RETURN(result);
32494#endif
32495break;
32496break;
32497case Arg::Index:
32498#if CPU(X86_64)
32499jit.atomicNeg64(args[0].asBaseIndex());
32500OPGEN_RETURN(result);
32501#endif
32502break;
32503break;
32504default:
32505break;
32506}
32507break;
32508case Opcode::AtomicNot8:
32509switch (this->args[0].kind()) {
32510case Arg::Addr:
32511case Arg::Stack:
32512case Arg::CallArg:
32513#if CPU(X86) || CPU(X86_64)
32514jit.atomicNot8(args[0].asAddress());
32515OPGEN_RETURN(result);
32516#endif
32517break;
32518break;
32519case Arg::Index:
32520#if CPU(X86) || CPU(X86_64)
32521jit.atomicNot8(args[0].asBaseIndex());
32522OPGEN_RETURN(result);
32523#endif
32524break;
32525break;
32526default:
32527break;
32528}
32529break;
32530case Opcode::AtomicNot16:
32531switch (this->args[0].kind()) {
32532case Arg::Addr:
32533case Arg::Stack:
32534case Arg::CallArg:
32535#if CPU(X86) || CPU(X86_64)
32536jit.atomicNot16(args[0].asAddress());
32537OPGEN_RETURN(result);
32538#endif
32539break;
32540break;
32541case Arg::Index:
32542#if CPU(X86) || CPU(X86_64)
32543jit.atomicNot16(args[0].asBaseIndex());
32544OPGEN_RETURN(result);
32545#endif
32546break;
32547break;
32548default:
32549break;
32550}
32551break;
32552case Opcode::AtomicNot32:
32553switch (this->args[0].kind()) {
32554case Arg::Addr:
32555case Arg::Stack:
32556case Arg::CallArg:
32557#if CPU(X86) || CPU(X86_64)
32558jit.atomicNot32(args[0].asAddress());
32559OPGEN_RETURN(result);
32560#endif
32561break;
32562break;
32563case Arg::Index:
32564#if CPU(X86) || CPU(X86_64)
32565jit.atomicNot32(args[0].asBaseIndex());
32566OPGEN_RETURN(result);
32567#endif
32568break;
32569break;
32570default:
32571break;
32572}
32573break;
32574case Opcode::AtomicNot64:
32575switch (this->args[0].kind()) {
32576case Arg::Addr:
32577case Arg::Stack:
32578case Arg::CallArg:
32579#if CPU(X86_64)
32580jit.atomicNot64(args[0].asAddress());
32581OPGEN_RETURN(result);
32582#endif
32583break;
32584break;
32585case Arg::Index:
32586#if CPU(X86_64)
32587jit.atomicNot64(args[0].asBaseIndex());
32588OPGEN_RETURN(result);
32589#endif
32590break;
32591break;
32592default:
32593break;
32594}
32595break;
32596case Opcode::AtomicXchgAdd8:
32597switch (this->args[1].kind()) {
32598case Arg::Addr:
32599case Arg::Stack:
32600case Arg::CallArg:
32601#if CPU(X86) || CPU(X86_64)
32602jit.atomicXchgAdd8(args[0].gpr(), args[1].asAddress());
32603OPGEN_RETURN(result);
32604#endif
32605break;
32606break;
32607case Arg::Index:
32608#if CPU(X86) || CPU(X86_64)
32609jit.atomicXchgAdd8(args[0].gpr(), args[1].asBaseIndex());
32610OPGEN_RETURN(result);
32611#endif
32612break;
32613break;
32614default:
32615break;
32616}
32617break;
32618case Opcode::AtomicXchgAdd16:
32619switch (this->args[1].kind()) {
32620case Arg::Addr:
32621case Arg::Stack:
32622case Arg::CallArg:
32623#if CPU(X86) || CPU(X86_64)
32624jit.atomicXchgAdd16(args[0].gpr(), args[1].asAddress());
32625OPGEN_RETURN(result);
32626#endif
32627break;
32628break;
32629case Arg::Index:
32630#if CPU(X86) || CPU(X86_64)
32631jit.atomicXchgAdd16(args[0].gpr(), args[1].asBaseIndex());
32632OPGEN_RETURN(result);
32633#endif
32634break;
32635break;
32636default:
32637break;
32638}
32639break;
32640case Opcode::AtomicXchgAdd32:
32641switch (this->args[1].kind()) {
32642case Arg::Addr:
32643case Arg::Stack:
32644case Arg::CallArg:
32645#if CPU(X86) || CPU(X86_64)
32646jit.atomicXchgAdd32(args[0].gpr(), args[1].asAddress());
32647OPGEN_RETURN(result);
32648#endif
32649break;
32650break;
32651case Arg::Index:
32652#if CPU(X86) || CPU(X86_64)
32653jit.atomicXchgAdd32(args[0].gpr(), args[1].asBaseIndex());
32654OPGEN_RETURN(result);
32655#endif
32656break;
32657break;
32658default:
32659break;
32660}
32661break;
32662case Opcode::AtomicXchgAdd64:
32663switch (this->args[1].kind()) {
32664case Arg::Addr:
32665case Arg::Stack:
32666case Arg::CallArg:
32667#if CPU(X86_64)
32668jit.atomicXchgAdd64(args[0].gpr(), args[1].asAddress());
32669OPGEN_RETURN(result);
32670#endif
32671break;
32672break;
32673case Arg::Index:
32674#if CPU(X86_64)
32675jit.atomicXchgAdd64(args[0].gpr(), args[1].asBaseIndex());
32676OPGEN_RETURN(result);
32677#endif
32678break;
32679break;
32680default:
32681break;
32682}
32683break;
32684case Opcode::AtomicXchg8:
32685switch (this->args[1].kind()) {
32686case Arg::Addr:
32687case Arg::Stack:
32688case Arg::CallArg:
32689#if CPU(X86) || CPU(X86_64)
32690jit.atomicXchg8(args[0].gpr(), args[1].asAddress());
32691OPGEN_RETURN(result);
32692#endif
32693break;
32694break;
32695case Arg::Index:
32696#if CPU(X86) || CPU(X86_64)
32697jit.atomicXchg8(args[0].gpr(), args[1].asBaseIndex());
32698OPGEN_RETURN(result);
32699#endif
32700break;
32701break;
32702default:
32703break;
32704}
32705break;
32706case Opcode::AtomicXchg16:
32707switch (this->args[1].kind()) {
32708case Arg::Addr:
32709case Arg::Stack:
32710case Arg::CallArg:
32711#if CPU(X86) || CPU(X86_64)
32712jit.atomicXchg16(args[0].gpr(), args[1].asAddress());
32713OPGEN_RETURN(result);
32714#endif
32715break;
32716break;
32717case Arg::Index:
32718#if CPU(X86) || CPU(X86_64)
32719jit.atomicXchg16(args[0].gpr(), args[1].asBaseIndex());
32720OPGEN_RETURN(result);
32721#endif
32722break;
32723break;
32724default:
32725break;
32726}
32727break;
32728case Opcode::AtomicXchg32:
32729switch (this->args[1].kind()) {
32730case Arg::Addr:
32731case Arg::Stack:
32732case Arg::CallArg:
32733#if CPU(X86) || CPU(X86_64)
32734jit.atomicXchg32(args[0].gpr(), args[1].asAddress());
32735OPGEN_RETURN(result);
32736#endif
32737break;
32738break;
32739case Arg::Index:
32740#if CPU(X86) || CPU(X86_64)
32741jit.atomicXchg32(args[0].gpr(), args[1].asBaseIndex());
32742OPGEN_RETURN(result);
32743#endif
32744break;
32745break;
32746default:
32747break;
32748}
32749break;
32750case Opcode::AtomicXchg64:
32751switch (this->args[1].kind()) {
32752case Arg::Addr:
32753case Arg::Stack:
32754case Arg::CallArg:
32755#if CPU(X86_64)
32756jit.atomicXchg64(args[0].gpr(), args[1].asAddress());
32757OPGEN_RETURN(result);
32758#endif
32759break;
32760break;
32761case Arg::Index:
32762#if CPU(X86_64)
32763jit.atomicXchg64(args[0].gpr(), args[1].asBaseIndex());
32764OPGEN_RETURN(result);
32765#endif
32766break;
32767break;
32768default:
32769break;
32770}
32771break;
32772case Opcode::LoadLink8:
32773#if CPU(ARM64)
32774jit.loadLink8(args[0].asAddress(), args[1].gpr());
32775OPGEN_RETURN(result);
32776#endif
32777break;
32778break;
32779case Opcode::LoadLinkAcq8:
32780#if CPU(ARM64)
32781jit.loadLinkAcq8(args[0].asAddress(), args[1].gpr());
32782OPGEN_RETURN(result);
32783#endif
32784break;
32785break;
32786case Opcode::StoreCond8:
32787#if CPU(ARM64)
32788jit.storeCond8(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32789OPGEN_RETURN(result);
32790#endif
32791break;
32792break;
32793case Opcode::StoreCondRel8:
32794#if CPU(ARM64)
32795jit.storeCondRel8(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32796OPGEN_RETURN(result);
32797#endif
32798break;
32799break;
32800case Opcode::LoadLink16:
32801#if CPU(ARM64)
32802jit.loadLink16(args[0].asAddress(), args[1].gpr());
32803OPGEN_RETURN(result);
32804#endif
32805break;
32806break;
32807case Opcode::LoadLinkAcq16:
32808#if CPU(ARM64)
32809jit.loadLinkAcq16(args[0].asAddress(), args[1].gpr());
32810OPGEN_RETURN(result);
32811#endif
32812break;
32813break;
32814case Opcode::StoreCond16:
32815#if CPU(ARM64)
32816jit.storeCond16(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32817OPGEN_RETURN(result);
32818#endif
32819break;
32820break;
32821case Opcode::StoreCondRel16:
32822#if CPU(ARM64)
32823jit.storeCondRel16(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32824OPGEN_RETURN(result);
32825#endif
32826break;
32827break;
32828case Opcode::LoadLink32:
32829#if CPU(ARM64)
32830jit.loadLink32(args[0].asAddress(), args[1].gpr());
32831OPGEN_RETURN(result);
32832#endif
32833break;
32834break;
32835case Opcode::LoadLinkAcq32:
32836#if CPU(ARM64)
32837jit.loadLinkAcq32(args[0].asAddress(), args[1].gpr());
32838OPGEN_RETURN(result);
32839#endif
32840break;
32841break;
32842case Opcode::StoreCond32:
32843#if CPU(ARM64)
32844jit.storeCond32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32845OPGEN_RETURN(result);
32846#endif
32847break;
32848break;
32849case Opcode::StoreCondRel32:
32850#if CPU(ARM64)
32851jit.storeCondRel32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32852OPGEN_RETURN(result);
32853#endif
32854break;
32855break;
32856case Opcode::LoadLink64:
32857#if CPU(ARM64)
32858jit.loadLink64(args[0].asAddress(), args[1].gpr());
32859OPGEN_RETURN(result);
32860#endif
32861break;
32862break;
32863case Opcode::LoadLinkAcq64:
32864#if CPU(ARM64)
32865jit.loadLinkAcq64(args[0].asAddress(), args[1].gpr());
32866OPGEN_RETURN(result);
32867#endif
32868break;
32869break;
32870case Opcode::StoreCond64:
32871#if CPU(ARM64)
32872jit.storeCond64(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32873OPGEN_RETURN(result);
32874#endif
32875break;
32876break;
32877case Opcode::StoreCondRel64:
32878#if CPU(ARM64)
32879jit.storeCondRel64(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32880OPGEN_RETURN(result);
32881#endif
32882break;
32883break;
32884case Opcode::Depend32:
32885#if CPU(ARM64)
32886jit.depend32(args[0].gpr(), args[1].gpr());
32887OPGEN_RETURN(result);
32888#endif
32889break;
32890break;
32891case Opcode::Depend64:
32892#if CPU(ARM64)
32893jit.depend64(args[0].gpr(), args[1].gpr());
32894OPGEN_RETURN(result);
32895#endif
32896break;
32897break;
32898case Opcode::Compare32:
32899switch (this->args[2].kind()) {
32900case Arg::Tmp:
32901jit.compare32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32902OPGEN_RETURN(result);
32903break;
32904break;
32905case Arg::Imm:
32906jit.compare32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32907OPGEN_RETURN(result);
32908break;
32909break;
32910default:
32911break;
32912}
32913break;
32914case Opcode::Compare64:
32915switch (this->args[2].kind()) {
32916case Arg::Tmp:
32917#if CPU(X86_64) || CPU(ARM64)
32918jit.compare64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32919OPGEN_RETURN(result);
32920#endif
32921break;
32922break;
32923case Arg::Imm:
32924#if CPU(X86_64)
32925jit.compare64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32926OPGEN_RETURN(result);
32927#endif
32928break;
32929break;
32930default:
32931break;
32932}
32933break;
32934case Opcode::Test32:
32935switch (this->args[1].kind()) {
32936case Arg::Addr:
32937case Arg::Stack:
32938case Arg::CallArg:
32939#if CPU(X86) || CPU(X86_64)
32940jit.test32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].gpr());
32941OPGEN_RETURN(result);
32942#endif
32943break;
32944break;
32945case Arg::Tmp:
32946switch (this->args[2].kind()) {
32947case Arg::Tmp:
32948jit.test32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32949OPGEN_RETURN(result);
32950break;
32951break;
32952case Arg::BitImm:
32953jit.test32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32954OPGEN_RETURN(result);
32955break;
32956break;
32957default:
32958break;
32959}
32960break;
32961default:
32962break;
32963}
32964break;
32965case Opcode::Test64:
32966switch (this->args[2].kind()) {
32967case Arg::Imm:
32968#if CPU(X86_64)
32969jit.test64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32970OPGEN_RETURN(result);
32971#endif
32972break;
32973break;
32974case Arg::Tmp:
32975#if CPU(X86_64) || CPU(ARM64)
32976jit.test64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32977OPGEN_RETURN(result);
32978#endif
32979break;
32980break;
32981default:
32982break;
32983}
32984break;
32985case Opcode::CompareDouble:
32986jit.compareDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr());
32987OPGEN_RETURN(result);
32988break;
32989break;
32990case Opcode::CompareFloat:
32991jit.compareFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr());
32992OPGEN_RETURN(result);
32993break;
32994break;
32995case Opcode::Branch8:
32996switch (this->args[1].kind()) {
32997case Arg::Addr:
32998case Arg::Stack:
32999case Arg::CallArg:
33000#if CPU(X86) || CPU(X86_64)
33001result = jit.branch8(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33002OPGEN_RETURN(result);
33003#endif
33004break;
33005break;
33006case Arg::Index:
33007#if CPU(X86) || CPU(X86_64)
33008result = jit.branch8(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
33009OPGEN_RETURN(result);
33010#endif
33011break;
33012break;
33013default:
33014break;
33015}
33016break;
33017case Opcode::Branch32:
33018switch (this->args[1].kind()) {
33019case Arg::Addr:
33020case Arg::Stack:
33021case Arg::CallArg:
33022switch (this->args[2].kind()) {
33023case Arg::Imm:
33024#if CPU(X86) || CPU(X86_64)
33025result = jit.branch32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33026OPGEN_RETURN(result);
33027#endif
33028break;
33029break;
33030case Arg::Tmp:
33031#if CPU(X86) || CPU(X86_64)
33032result = jit.branch32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr());
33033OPGEN_RETURN(result);
33034#endif
33035break;
33036break;
33037default:
33038break;
33039}
33040break;
33041case Arg::Tmp:
33042switch (this->args[2].kind()) {
33043case Arg::Tmp:
33044result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr());
33045OPGEN_RETURN(result);
33046break;
33047break;
33048case Arg::Imm:
33049result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32());
33050OPGEN_RETURN(result);
33051break;
33052break;
33053case Arg::Addr:
33054case Arg::Stack:
33055case Arg::CallArg:
33056#if CPU(X86) || CPU(X86_64)
33057result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress());
33058OPGEN_RETURN(result);
33059#endif
33060break;
33061break;
33062default:
33063break;
33064}
33065break;
33066case Arg::Index:
33067#if CPU(X86) || CPU(X86_64)
33068result = jit.branch32(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
33069OPGEN_RETURN(result);
33070#endif
33071break;
33072break;
33073default:
33074break;
33075}
33076break;
33077case Opcode::Branch64:
33078switch (this->args[1].kind()) {
33079case Arg::Tmp:
33080switch (this->args[2].kind()) {
33081case Arg::Tmp:
33082#if CPU(X86_64) || CPU(ARM64)
33083result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr());
33084OPGEN_RETURN(result);
33085#endif
33086break;
33087break;
33088case Arg::Imm:
33089#if CPU(X86_64) || CPU(ARM64)
33090result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32());
33091OPGEN_RETURN(result);
33092#endif
33093break;
33094break;
33095case Arg::Addr:
33096case Arg::Stack:
33097case Arg::CallArg:
33098#if CPU(X86_64)
33099result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress());
33100OPGEN_RETURN(result);
33101#endif
33102break;
33103break;
33104default:
33105break;
33106}
33107break;
33108case Arg::Addr:
33109case Arg::Stack:
33110case Arg::CallArg:
33111switch (this->args[2].kind()) {
33112case Arg::Tmp:
33113#if CPU(X86_64)
33114result = jit.branch64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr());
33115OPGEN_RETURN(result);
33116#endif
33117break;
33118break;
33119case Arg::Imm:
33120#if CPU(X86_64)
33121result = jit.branch64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33122OPGEN_RETURN(result);
33123#endif
33124break;
33125break;
33126default:
33127break;
33128}
33129break;
33130case Arg::Index:
33131#if CPU(X86_64)
33132result = jit.branch64(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].gpr());
33133OPGEN_RETURN(result);
33134#endif
33135break;
33136break;
33137default:
33138break;
33139}
33140break;
33141case Opcode::BranchTest8:
33142switch (this->args[1].kind()) {
33143case Arg::Addr:
33144case Arg::Stack:
33145case Arg::CallArg:
33146#if CPU(X86) || CPU(X86_64)
33147result = jit.branchTest8(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33148OPGEN_RETURN(result);
33149#endif
33150break;
33151break;
33152case Arg::Index:
33153#if CPU(X86) || CPU(X86_64)
33154result = jit.branchTest8(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
33155OPGEN_RETURN(result);
33156#endif
33157break;
33158break;
33159default:
33160break;
33161}
33162break;
33163case Opcode::BranchTest32:
33164switch (this->args[1].kind()) {
33165case Arg::Tmp:
33166switch (this->args[2].kind()) {
33167case Arg::Tmp:
33168result = jit.branchTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33169OPGEN_RETURN(result);
33170break;
33171break;
33172case Arg::BitImm:
33173result = jit.branchTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
33174OPGEN_RETURN(result);
33175break;
33176break;
33177default:
33178break;
33179}
33180break;
33181case Arg::Addr:
33182case Arg::Stack:
33183case Arg::CallArg:
33184#if CPU(X86) || CPU(X86_64)
33185result = jit.branchTest32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33186OPGEN_RETURN(result);
33187#endif
33188break;
33189break;
33190case Arg::Index:
33191#if CPU(X86) || CPU(X86_64)
33192result = jit.branchTest32(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
33193OPGEN_RETURN(result);
33194#endif
33195break;
33196break;
33197default:
33198break;
33199}
33200break;
33201case Opcode::BranchTest64:
33202switch (this->args[1].kind()) {
33203case Arg::Tmp:
33204switch (this->args[2].kind()) {
33205case Arg::Tmp:
33206#if CPU(X86_64) || CPU(ARM64)
33207result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33208OPGEN_RETURN(result);
33209#endif
33210break;
33211break;
33212#if USE(JSVALUE64)
33213case Arg::BitImm64:
33214#if CPU(ARM64)
33215result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm64());
33216OPGEN_RETURN(result);
33217#endif
33218break;
33219break;
33220#endif // USE(JSVALUE64)
33221case Arg::BitImm:
33222#if CPU(X86_64)
33223result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
33224OPGEN_RETURN(result);
33225#endif
33226break;
33227break;
33228default:
33229break;
33230}
33231break;
33232case Arg::Addr:
33233case Arg::Stack:
33234case Arg::CallArg:
33235switch (this->args[2].kind()) {
33236case Arg::BitImm:
33237#if CPU(X86_64)
33238result = jit.branchTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33239OPGEN_RETURN(result);
33240#endif
33241break;
33242break;
33243case Arg::Tmp:
33244#if CPU(X86_64)
33245result = jit.branchTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33246OPGEN_RETURN(result);
33247#endif
33248break;
33249break;
33250default:
33251break;
33252}
33253break;
33254case Arg::Index:
33255#if CPU(X86_64)
33256result = jit.branchTest64(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
33257OPGEN_RETURN(result);
33258#endif
33259break;
33260break;
33261default:
33262break;
33263}
33264break;
33265case Opcode::BranchTestBit64:
33266switch (this->args[1].kind()) {
33267case Arg::Tmp:
33268switch (this->args[2].kind()) {
33269case Arg::Imm:
33270#if CPU(X86_64)
33271result = jit.branchTestBit64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
33272OPGEN_RETURN(result);
33273#endif
33274break;
33275break;
33276case Arg::Tmp:
33277#if CPU(X86_64)
33278result = jit.branchTestBit64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33279OPGEN_RETURN(result);
33280#endif
33281break;
33282break;
33283default:
33284break;
33285}
33286break;
33287case Arg::Addr:
33288case Arg::Stack:
33289case Arg::CallArg:
33290#if CPU(X86_64)
33291result = jit.branchTestBit64(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33292OPGEN_RETURN(result);
33293#endif
33294break;
33295break;
33296default:
33297break;
33298}
33299break;
33300case Opcode::BranchTestBit32:
33301switch (this->args[1].kind()) {
33302case Arg::Tmp:
33303switch (this->args[2].kind()) {
33304case Arg::Imm:
33305#if CPU(X86) || CPU(X86_64)
33306result = jit.branchTestBit32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
33307OPGEN_RETURN(result);
33308#endif
33309break;
33310break;
33311case Arg::Tmp:
33312#if CPU(X86) || CPU(X86_64)
33313result = jit.branchTestBit32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33314OPGEN_RETURN(result);
33315#endif
33316break;
33317break;
33318default:
33319break;
33320}
33321break;
33322case Arg::Addr:
33323case Arg::Stack:
33324case Arg::CallArg:
33325#if CPU(X86) || CPU(X86_64)
33326result = jit.branchTestBit32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
33327OPGEN_RETURN(result);
33328#endif
33329break;
33330break;
33331default:
33332break;
33333}
33334break;
33335case Opcode::BranchDouble:
33336result = jit.branchDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr());
33337OPGEN_RETURN(result);
33338break;
33339break;
33340case Opcode::BranchFloat:
33341result = jit.branchFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr());
33342OPGEN_RETURN(result);
33343break;
33344break;
33345case Opcode::BranchAdd32:
33346switch (this->args.size()) {
33347case 4:
33348switch (this->args[1].kind()) {
33349case Arg::Tmp:
33350switch (this->args[2].kind()) {
33351case Arg::Tmp:
33352result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
33353OPGEN_RETURN(result);
33354break;
33355break;
33356case Arg::Addr:
33357case Arg::Stack:
33358case Arg::CallArg:
33359#if CPU(X86) || CPU(X86_64)
33360result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress(), args[3].gpr());
33361OPGEN_RETURN(result);
33362#endif
33363break;
33364break;
33365default:
33366break;
33367}
33368break;
33369case Arg::Addr:
33370case Arg::Stack:
33371case Arg::CallArg:
33372#if CPU(X86) || CPU(X86_64)
33373result = jit.branchAdd32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].gpr());
33374OPGEN_RETURN(result);
33375#endif
33376break;
33377break;
33378default:
33379break;
33380}
33381break;
33382case 3:
33383switch (this->args[1].kind()) {
33384case Arg::Tmp:
33385switch (this->args[2].kind()) {
33386case Arg::Tmp:
33387result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33388OPGEN_RETURN(result);
33389break;
33390break;
33391case Arg::Addr:
33392case Arg::Stack:
33393case Arg::CallArg:
33394#if CPU(X86) || CPU(X86_64)
33395result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress());
33396OPGEN_RETURN(result);
33397#endif
33398break;
33399break;
33400default:
33401break;
33402}
33403break;
33404case Arg::Imm:
33405switch (this->args[2].kind()) {
33406case Arg::Tmp:
33407result = jit.branchAdd32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33408OPGEN_RETURN(result);
33409break;
33410break;
33411case Arg::Addr:
33412case Arg::Stack:
33413case Arg::CallArg:
33414#if CPU(X86) || CPU(X86_64)
33415result = jit.branchAdd32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].asAddress());
33416OPGEN_RETURN(result);
33417#endif
33418break;
33419break;
33420default:
33421break;
33422}
33423break;
33424case Arg::Addr:
33425case Arg::Stack:
33426case Arg::CallArg:
33427#if CPU(X86) || CPU(X86_64)
33428result = jit.branchAdd32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33429OPGEN_RETURN(result);
33430#endif
33431break;
33432break;
33433default:
33434break;
33435}
33436break;
33437default:
33438break;
33439}
33440break;
33441case Opcode::BranchAdd64:
33442switch (this->args.size()) {
33443case 4:
33444switch (this->args[1].kind()) {
33445case Arg::Tmp:
33446switch (this->args[2].kind()) {
33447case Arg::Tmp:
33448result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
33449OPGEN_RETURN(result);
33450break;
33451break;
33452case Arg::Addr:
33453case Arg::Stack:
33454case Arg::CallArg:
33455#if CPU(X86) || CPU(X86_64)
33456result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress(), args[3].gpr());
33457OPGEN_RETURN(result);
33458#endif
33459break;
33460break;
33461default:
33462break;
33463}
33464break;
33465case Arg::Addr:
33466case Arg::Stack:
33467case Arg::CallArg:
33468#if CPU(X86) || CPU(X86_64)
33469result = jit.branchAdd64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].gpr());
33470OPGEN_RETURN(result);
33471#endif
33472break;
33473break;
33474default:
33475break;
33476}
33477break;
33478case 3:
33479switch (this->args[1].kind()) {
33480case Arg::Imm:
33481#if CPU(X86_64) || CPU(ARM64)
33482result = jit.branchAdd64(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33483OPGEN_RETURN(result);
33484#endif
33485break;
33486break;
33487case Arg::Tmp:
33488#if CPU(X86_64) || CPU(ARM64)
33489result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33490OPGEN_RETURN(result);
33491#endif
33492break;
33493break;
33494case Arg::Addr:
33495case Arg::Stack:
33496case Arg::CallArg:
33497#if CPU(X86_64)
33498result = jit.branchAdd64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33499OPGEN_RETURN(result);
33500#endif
33501break;
33502break;
33503default:
33504break;
33505}
33506break;
33507default:
33508break;
33509}
33510break;
33511case Opcode::BranchMul32:
33512switch (this->args.size()) {
33513case 3:
33514switch (this->args[1].kind()) {
33515case Arg::Tmp:
33516#if CPU(X86) || CPU(X86_64)
33517result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33518OPGEN_RETURN(result);
33519#endif
33520break;
33521break;
33522case Arg::Addr:
33523case Arg::Stack:
33524case Arg::CallArg:
33525#if CPU(X86) || CPU(X86_64)
33526result = jit.branchMul32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33527OPGEN_RETURN(result);
33528#endif
33529break;
33530break;
33531default:
33532break;
33533}
33534break;
33535case 4:
33536#if CPU(X86) || CPU(X86_64)
33537result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
33538OPGEN_RETURN(result);
33539#endif
33540break;
33541break;
33542case 6:
33543#if CPU(ARM64)
33544result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33545OPGEN_RETURN(result);
33546#endif
33547break;
33548break;
33549default:
33550break;
33551}
33552break;
33553case Opcode::BranchMul64:
33554switch (this->args.size()) {
33555case 3:
33556#if CPU(X86_64)
33557result = jit.branchMul64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33558OPGEN_RETURN(result);
33559#endif
33560break;
33561break;
33562case 6:
33563#if CPU(ARM64)
33564result = jit.branchMul64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33565OPGEN_RETURN(result);
33566#endif
33567break;
33568break;
33569default:
33570break;
33571}
33572break;
33573case Opcode::BranchSub32:
33574switch (this->args[1].kind()) {
33575case Arg::Tmp:
33576switch (this->args[2].kind()) {
33577case Arg::Tmp:
33578result = jit.branchSub32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33579OPGEN_RETURN(result);
33580break;
33581break;
33582case Arg::Addr:
33583case Arg::Stack:
33584case Arg::CallArg:
33585#if CPU(X86) || CPU(X86_64)
33586result = jit.branchSub32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress());
33587OPGEN_RETURN(result);
33588#endif
33589break;
33590break;
33591default:
33592break;
33593}
33594break;
33595case Arg::Imm:
33596switch (this->args[2].kind()) {
33597case Arg::Tmp:
33598result = jit.branchSub32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33599OPGEN_RETURN(result);
33600break;
33601break;
33602case Arg::Addr:
33603case Arg::Stack:
33604case Arg::CallArg:
33605#if CPU(X86) || CPU(X86_64)
33606result = jit.branchSub32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].asAddress());
33607OPGEN_RETURN(result);
33608#endif
33609break;
33610break;
33611default:
33612break;
33613}
33614break;
33615case Arg::Addr:
33616case Arg::Stack:
33617case Arg::CallArg:
33618#if CPU(X86) || CPU(X86_64)
33619result = jit.branchSub32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33620OPGEN_RETURN(result);
33621#endif
33622break;
33623break;
33624default:
33625break;
33626}
33627break;
33628case Opcode::BranchSub64:
33629switch (this->args[1].kind()) {
33630case Arg::Imm:
33631#if CPU(X86_64) || CPU(ARM64)
33632result = jit.branchSub64(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33633OPGEN_RETURN(result);
33634#endif
33635break;
33636break;
33637case Arg::Tmp:
33638#if CPU(X86_64) || CPU(ARM64)
33639result = jit.branchSub64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33640OPGEN_RETURN(result);
33641#endif
33642break;
33643break;
33644default:
33645break;
33646}
33647break;
33648case Opcode::BranchNeg32:
33649result = jit.branchNeg32(args[0].asResultCondition(), args[1].gpr());
33650OPGEN_RETURN(result);
33651break;
33652break;
33653case Opcode::BranchNeg64:
33654#if CPU(X86_64) || CPU(ARM64)
33655result = jit.branchNeg64(args[0].asResultCondition(), args[1].gpr());
33656OPGEN_RETURN(result);
33657#endif
33658break;
33659break;
33660case Opcode::MoveConditionally32:
33661switch (this->args.size()) {
33662case 5:
33663jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33664OPGEN_RETURN(result);
33665break;
33666break;
33667case 6:
33668switch (this->args[2].kind()) {
33669case Arg::Tmp:
33670jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33671OPGEN_RETURN(result);
33672break;
33673break;
33674case Arg::Imm:
33675jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33676OPGEN_RETURN(result);
33677break;
33678break;
33679default:
33680break;
33681}
33682break;
33683default:
33684break;
33685}
33686break;
33687case Opcode::MoveConditionally64:
33688switch (this->args.size()) {
33689case 5:
33690#if CPU(X86_64) || CPU(ARM64)
33691jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33692OPGEN_RETURN(result);
33693#endif
33694break;
33695break;
33696case 6:
33697switch (this->args[2].kind()) {
33698case Arg::Tmp:
33699#if CPU(X86_64) || CPU(ARM64)
33700jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33701OPGEN_RETURN(result);
33702#endif
33703break;
33704break;
33705case Arg::Imm:
33706#if CPU(X86_64) || CPU(ARM64)
33707jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33708OPGEN_RETURN(result);
33709#endif
33710break;
33711break;
33712default:
33713break;
33714}
33715break;
33716default:
33717break;
33718}
33719break;
33720case Opcode::MoveConditionallyTest32:
33721switch (this->args.size()) {
33722case 5:
33723switch (this->args[2].kind()) {
33724case Arg::Tmp:
33725jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33726OPGEN_RETURN(result);
33727break;
33728break;
33729case Arg::Imm:
33730#if CPU(X86) || CPU(X86_64)
33731jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr());
33732OPGEN_RETURN(result);
33733#endif
33734break;
33735break;
33736default:
33737break;
33738}
33739break;
33740case 6:
33741switch (this->args[2].kind()) {
33742case Arg::Tmp:
33743jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33744OPGEN_RETURN(result);
33745break;
33746break;
33747case Arg::BitImm:
33748jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33749OPGEN_RETURN(result);
33750break;
33751break;
33752default:
33753break;
33754}
33755break;
33756default:
33757break;
33758}
33759break;
33760case Opcode::MoveConditionallyTest64:
33761switch (this->args.size()) {
33762case 5:
33763switch (this->args[2].kind()) {
33764case Arg::Tmp:
33765#if CPU(X86_64) || CPU(ARM64)
33766jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33767OPGEN_RETURN(result);
33768#endif
33769break;
33770break;
33771case Arg::Imm:
33772#if CPU(X86_64)
33773jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr());
33774OPGEN_RETURN(result);
33775#endif
33776break;
33777break;
33778default:
33779break;
33780}
33781break;
33782case 6:
33783switch (this->args[2].kind()) {
33784case Arg::Tmp:
33785#if CPU(X86_64) || CPU(ARM64)
33786jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33787OPGEN_RETURN(result);
33788#endif
33789break;
33790break;
33791case Arg::Imm:
33792#if CPU(X86_64)
33793jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33794OPGEN_RETURN(result);
33795#endif
33796break;
33797break;
33798default:
33799break;
33800}
33801break;
33802default:
33803break;
33804}
33805break;
33806case Opcode::MoveConditionallyDouble:
33807switch (this->args.size()) {
33808case 6:
33809jit.moveConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33810OPGEN_RETURN(result);
33811break;
33812break;
33813case 5:
33814jit.moveConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr());
33815OPGEN_RETURN(result);
33816break;
33817break;
33818default:
33819break;
33820}
33821break;
33822case Opcode::MoveConditionallyFloat:
33823switch (this->args.size()) {
33824case 6:
33825jit.moveConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33826OPGEN_RETURN(result);
33827break;
33828break;
33829case 5:
33830jit.moveConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr());
33831OPGEN_RETURN(result);
33832break;
33833break;
33834default:
33835break;
33836}
33837break;
33838case Opcode::MoveDoubleConditionally32:
33839switch (this->args[1].kind()) {
33840case Arg::Tmp:
33841switch (this->args[2].kind()) {
33842case Arg::Tmp:
33843jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33844OPGEN_RETURN(result);
33845break;
33846break;
33847case Arg::Imm:
33848jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33849OPGEN_RETURN(result);
33850break;
33851break;
33852case Arg::Addr:
33853case Arg::Stack:
33854case Arg::CallArg:
33855#if CPU(X86) || CPU(X86_64)
33856jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33857OPGEN_RETURN(result);
33858#endif
33859break;
33860break;
33861default:
33862break;
33863}
33864break;
33865case Arg::Addr:
33866case Arg::Stack:
33867case Arg::CallArg:
33868switch (this->args[2].kind()) {
33869case Arg::Imm:
33870#if CPU(X86) || CPU(X86_64)
33871jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33872OPGEN_RETURN(result);
33873#endif
33874break;
33875break;
33876case Arg::Tmp:
33877#if CPU(X86) || CPU(X86_64)
33878jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33879OPGEN_RETURN(result);
33880#endif
33881break;
33882break;
33883default:
33884break;
33885}
33886break;
33887case Arg::Index:
33888#if CPU(X86) || CPU(X86_64)
33889jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33890OPGEN_RETURN(result);
33891#endif
33892break;
33893break;
33894default:
33895break;
33896}
33897break;
33898case Opcode::MoveDoubleConditionally64:
33899switch (this->args[1].kind()) {
33900case Arg::Tmp:
33901switch (this->args[2].kind()) {
33902case Arg::Tmp:
33903#if CPU(X86_64) || CPU(ARM64)
33904jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33905OPGEN_RETURN(result);
33906#endif
33907break;
33908break;
33909case Arg::Imm:
33910#if CPU(X86_64) || CPU(ARM64)
33911jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33912OPGEN_RETURN(result);
33913#endif
33914break;
33915break;
33916case Arg::Addr:
33917case Arg::Stack:
33918case Arg::CallArg:
33919#if CPU(X86_64)
33920jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33921OPGEN_RETURN(result);
33922#endif
33923break;
33924break;
33925default:
33926break;
33927}
33928break;
33929case Arg::Addr:
33930case Arg::Stack:
33931case Arg::CallArg:
33932switch (this->args[2].kind()) {
33933case Arg::Tmp:
33934#if CPU(X86_64)
33935jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33936OPGEN_RETURN(result);
33937#endif
33938break;
33939break;
33940case Arg::Imm:
33941#if CPU(X86_64)
33942jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33943OPGEN_RETURN(result);
33944#endif
33945break;
33946break;
33947default:
33948break;
33949}
33950break;
33951case Arg::Index:
33952#if CPU(X86_64)
33953jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33954OPGEN_RETURN(result);
33955#endif
33956break;
33957break;
33958default:
33959break;
33960}
33961break;
33962case Opcode::MoveDoubleConditionallyTest32:
33963switch (this->args[1].kind()) {
33964case Arg::Tmp:
33965switch (this->args[2].kind()) {
33966case Arg::Tmp:
33967jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33968OPGEN_RETURN(result);
33969break;
33970break;
33971case Arg::BitImm:
33972jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33973OPGEN_RETURN(result);
33974break;
33975break;
33976default:
33977break;
33978}
33979break;
33980case Arg::Addr:
33981case Arg::Stack:
33982case Arg::CallArg:
33983#if CPU(X86) || CPU(X86_64)
33984jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33985OPGEN_RETURN(result);
33986#endif
33987break;
33988break;
33989case Arg::Index:
33990#if CPU(X86) || CPU(X86_64)
33991jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33992OPGEN_RETURN(result);
33993#endif
33994break;
33995break;
33996default:
33997break;
33998}
33999break;
34000case Opcode::MoveDoubleConditionallyTest64:
34001switch (this->args[1].kind()) {
34002case Arg::Tmp:
34003switch (this->args[2].kind()) {
34004case Arg::Tmp:
34005#if CPU(X86_64) || CPU(ARM64)
34006jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34007OPGEN_RETURN(result);
34008#endif
34009break;
34010break;
34011case Arg::Imm:
34012#if CPU(X86_64)
34013jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34014OPGEN_RETURN(result);
34015#endif
34016break;
34017break;
34018default:
34019break;
34020}
34021break;
34022case Arg::Addr:
34023case Arg::Stack:
34024case Arg::CallArg:
34025switch (this->args[2].kind()) {
34026case Arg::Imm:
34027#if CPU(X86_64)
34028jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34029OPGEN_RETURN(result);
34030#endif
34031break;
34032break;
34033case Arg::Tmp:
34034#if CPU(X86_64)
34035jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34036OPGEN_RETURN(result);
34037#endif
34038break;
34039break;
34040default:
34041break;
34042}
34043break;
34044case Arg::Index:
34045#if CPU(X86_64)
34046jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34047OPGEN_RETURN(result);
34048#endif
34049break;
34050break;
34051default:
34052break;
34053}
34054break;
34055case Opcode::MoveDoubleConditionallyDouble:
34056jit.moveDoubleConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34057OPGEN_RETURN(result);
34058break;
34059break;
34060case Opcode::MoveDoubleConditionallyFloat:
34061jit.moveDoubleConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
34062OPGEN_RETURN(result);
34063break;
34064break;
34065case Opcode::MemoryFence:
34066jit.memoryFence();
34067OPGEN_RETURN(result);
34068break;
34069break;
34070case Opcode::StoreFence:
34071jit.storeFence();
34072OPGEN_RETURN(result);
34073break;
34074break;
34075case Opcode::LoadFence:
34076jit.loadFence();
34077OPGEN_RETURN(result);
34078break;
34079break;
34080case Opcode::Jump:
34081result = jit.jump();
34082OPGEN_RETURN(result);
34083break;
34084break;
34085case Opcode::RetVoid:
34086jit.retVoid();
34087OPGEN_RETURN(result);
34088break;
34089break;
34090case Opcode::Ret32:
34091jit.ret32(args[0].gpr());
34092OPGEN_RETURN(result);
34093break;
34094break;
34095case Opcode::Ret64:
34096#if CPU(X86_64) || CPU(ARM64)
34097jit.ret64(args[0].gpr());
34098OPGEN_RETURN(result);
34099#endif
34100break;
34101break;
34102case Opcode::RetFloat:
34103jit.retFloat(args[0].fpr());
34104OPGEN_RETURN(result);
34105break;
34106break;
34107case Opcode::RetDouble:
34108jit.retDouble(args[0].fpr());
34109OPGEN_RETURN(result);
34110break;
34111break;
34112case Opcode::Oops:
34113jit.oops();
34114OPGEN_RETURN(result);
34115break;
34116break;
34117case Opcode::EntrySwitch:
34118OPGEN_RETURN(EntrySwitchCustom::generate(*this, jit, context));
34119break;
34120case Opcode::Shuffle:
34121OPGEN_RETURN(ShuffleCustom::generate(*this, jit, context));
34122break;
34123case Opcode::Patch:
34124OPGEN_RETURN(PatchCustom::generate(*this, jit, context));
34125break;
34126case Opcode::CCall:
34127OPGEN_RETURN(CCallCustom::generate(*this, jit, context));
34128break;
34129case Opcode::ColdCCall:
34130OPGEN_RETURN(ColdCCallCustom::generate(*this, jit, context));
34131break;
34132case Opcode::WasmBoundsCheck:
34133OPGEN_RETURN(WasmBoundsCheckCustom::generate(*this, jit, context));
34134break;
34135default:
34136break;
34137}
34138RELEASE_ASSERT_NOT_REACHED();
34139return result;
34140}
34141} } } // namespace JSC::B3::Air
34142#endif // AirOpcodeGenerated_h
34143