1/*
2 * Copyright (C) 2008-2019 Apple Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#pragma once
27
28#include "Options.h"
29#include <wtf/NumberOfCores.h>
30
31namespace JSC {
32
33#if USE(JSVALUE64)
34using CPURegister = int64_t;
35using UCPURegister = uint64_t;
36#else
37using CPURegister = int32_t;
38using UCPURegister = uint32_t;
39#endif
40
41constexpr bool isARMv7IDIVSupported()
42{
43#if HAVE(ARM_IDIV_INSTRUCTIONS)
44 return true;
45#else
46 return false;
47#endif
48}
49
50constexpr bool isARM64()
51{
52#if CPU(ARM64)
53 return true;
54#else
55 return false;
56#endif
57}
58
59constexpr bool isARM64E()
60{
61#if CPU(ARM64E)
62 return true;
63#else
64 return false;
65#endif
66}
67
68constexpr bool isX86()
69{
70#if CPU(X86_64) || CPU(X86)
71 return true;
72#else
73 return false;
74#endif
75}
76
77constexpr bool isX86_64()
78{
79#if CPU(X86_64)
80 return true;
81#else
82 return false;
83#endif
84}
85
86constexpr bool is64Bit()
87{
88#if USE(JSVALUE64)
89 return true;
90#else
91 return false;
92#endif
93}
94
95constexpr bool is32Bit()
96{
97 return !is64Bit();
98}
99
100constexpr bool isAddress64Bit()
101{
102 return sizeof(void*) == 8;
103}
104
105constexpr bool isAddress32Bit()
106{
107 return !isAddress64Bit();
108}
109
110constexpr bool isMIPS()
111{
112#if CPU(MIPS)
113 return true;
114#else
115 return false;
116#endif
117}
118
119inline bool optimizeForARMv7IDIVSupported()
120{
121 return isARMv7IDIVSupported() && Options::useArchitectureSpecificOptimizations();
122}
123
124inline bool optimizeForARM64()
125{
126 return isARM64() && Options::useArchitectureSpecificOptimizations();
127}
128
129inline bool optimizeForX86()
130{
131 return isX86() && Options::useArchitectureSpecificOptimizations();
132}
133
134inline bool optimizeForX86_64()
135{
136 return isX86_64() && Options::useArchitectureSpecificOptimizations();
137}
138
139inline bool hasSensibleDoubleToInt()
140{
141 return optimizeForX86();
142}
143
144#if (CPU(X86) || CPU(X86_64)) && OS(DARWIN)
145bool isKernTCSMAvailable();
146bool enableKernTCSM();
147int kernTCSMAwareNumberOfProcessorCores();
148int64_t hwL3CacheSize();
149int32_t hwPhysicalCPUMax();
150#else
151ALWAYS_INLINE bool isKernTCSMAvailable() { return false; }
152ALWAYS_INLINE bool enableKernTCSM() { return false; }
153ALWAYS_INLINE int kernTCSMAwareNumberOfProcessorCores() { return WTF::numberOfProcessorCores(); }
154ALWAYS_INLINE int64_t hwL3CacheSize() { return 0; }
155ALWAYS_INLINE int32_t hwPhysicalCPUMax() { return kernTCSMAwareNumberOfProcessorCores(); }
156#endif
157
158} // namespace JSC
159
160